Abstract: An embodiment of the present disclosure discloses a wireless charging device comprising a wireless receiving module, a controller, a first charging module, and a second charging module. The wireless receiving module is configured to receive a wireless charging signal in response to the wireless charging device being in a wireless sensing area, transmit a state indication signal to the controller, receive a charging indication signal from the controller, and determine whether to transmit the wireless charging signal to the first charging module according to the charging indication signal.

Abstract: A whole-airspace satellite search method and device based on a phased array antenna are provided. The present disclosure combines electronic scanning implemented by the phased array antenna with mechanical scanning implemented by a mechanical actuator. As for low-orbit satellite communication, the present disclosure achieves rapid search and aiming through the phased array antenna, and solves the problem of limited electronic scanning angle of the phased array antenna through a servo system of the mechanical actuator. On the other hand, the present disclosure supports whole-airspace search and aiming of high, medium, and low-orbit satellites through the combination of the electronic scanning implemented by the phased array antenna and the mechanical scanning implemented by the mechanical actuator.

Abstract: An automated deployment method for upgrading a client's internal business software system includes: obtaining a configuration template from a runtime configuration of a business software system, unifying and updating a format of the configuration template; automatically adjusting middleware using the obtained configuration template; and performing fast cross-version upgrading. Compared with existing technologies, the method realizes automatic generation of the configuration template and reduces the demand on professional skill of the field operators. Irrespective of upgrading by direct connection to the upgrade server of the service provider or upgrading directly at the client site, the method is faster and more resource-saving than existing technologies.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: Implementations are described herein for leveraging an agricultural knowledge graph to generate messages automatically. In various implementations, an agricultural event may trigger proactive performance of one or more of the following operations. Nodes of the agricultural knowledge graph may be identified as related to the agricultural event, including field node(s) representing subject agricultural field(s) to which the agricultural event is relevant and other node(s) connected to one or more of the field nodes by edge(s). Machine learning model(s) may be accessed based on the identified nodes and/or the edges that connect the identified nodes. Data relevant to the subject agricultural field(s) may be retrieved from data source(s) controlled by an agricultural entity and processed based on the machine learning model(s) to generate inference(s) about the subject agricultural field(s).

Abstract: Provided herein are methods and compositions for the identification of modulators of LILRB3 activation. Also provided herein are methods of treating cancer comprising the administration of an inhibitor LILRB3 activation. Also provided are methods of treating autoimmune disease or inhibiting the onset of transplant rejection or treating an inflammatory disorder comprising administering an agonist of LILRB3 activation to a subject.

Abstract: A boundary protection method and system of a radiation detection robot. The boundary protection method comprises: a first laser radar and a second laser radar are arranged diagonally, a first marking rod and a second marking rod are arranged diagonally; a boundary of an interlocking zone is defined by the first laser radar, the second laser radar, the first marking rod and the second marking rod; the object to be detected is placed in the interlocking zone; the radiation detection robot uses rays to detect the object to be detected in the interlocking zone; an early warning zone is provided outside the interlocking zone; wherein when it is detected that a person or object has intruded into the interlocking zone, the radiation detection robot stops emitting rays; and when it is detected that a person or object has intruded into the early warning zone, a warning is issued directly.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

Abstract: Disclosed are a display substrate. The display substrate includes a drive backplane; a first electrode layer disposed on a side of the drive backplane; a pixel definition layer disposed on a side, distal to the drive backplane, of the first electrode layer; an organic light-emitting layer disposed on a side, distal to the drive backplane, of the pixel definition layer, wherein the organic light-emitting layer comprises: a plurality of organic material layers stacked in a direction perpendicular to and away from the drive backplane, and a portion of the organic material layer disposed inside the partition groove is separated from a portion of the organic material layer disposed outside the partition groove; and a second electrode layer disposed on a side, distal to the drive backplane, of the organic light-emitting layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 ?1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.

Abstract: A memory device includes a substrate, a reference layer, a tunneling layer, a film stack, and a capping layer. The reference layer is disposed on the substrate. The tunneling layer is disposed on the reference layer. The film stack is formed over the tunneling layer and on the substrate, wherein the film stack includes a first free layer, a spacer with high exchange stiffness constant and a second free layer. The first free layer is in contact with the tunneling layer and the film stack. The spacer with high exchange stiffness constant is sandwiched between the first free layer and the second free layer. The capping layer is disposed on and electrically connected to the film stack.

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a memory cell array comprising a plurality of magnetic tunnel junction (MTJ) memory cells arranged in columns and rows, a read bias circuit connected to the memory cell array and configured to provide a reading bias for a MTJ memory cell of the memory cell array, and a first non-linear resistance device connected in series and between the MTJ memory cell and the read bias circuit. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

Abstract: A method includes forming a channel region above a (110)-orientated substrate and having a length extending in a <100> direction; epitaxial growing a plurality of source/drain regions on either side the channel region; forming a gate structure surrounding the channel region; forming a plurality of source/drain contacts on the source/drain regions.

Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.

Abstract: A method of forming a semiconductor device includes forming a fin on a substrate, the fin comprising alternately stacked first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form a plurality of spaces each between adjacent two of the second semiconductor layers, implanting oxygen into the second semiconductor layers, and forming a gate structure wrapping around the second semiconductor layers.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device also includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device further includes a ferroelectric layer in contact with the channel layer.