Abstract: Aspects of the invention include systems and methods configured to provide parasitic capacitance-aware dummy metal fill methodologies. A non-limiting example computer-implemented method includes selecting one or more layers in a circuit design layout for interlayer parasitic capacitance reduction. One or more dummy metal shapes in each of the one or more layers selected for interlayer parasitic capacitance reduction is adjusted (e.g., trimmed, moved, and/or reshaped). One or more adjusted dummy metal shapes are modified until the circuit design layout satisfies design rule checking (DRC) analysis and timing is closed.

Abstract: Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.

Abstract: A resistive processing unit cell includes a weight storage device to store a weight value of the resistive processing unit cell, and multiple circuit blocks. Each circuit block includes a weight update circuit coupled to dedicated update control lines, and a weight read circuit coupled to dedicated read control lines. The circuit blocks are configured to operate in parallel to (i) perform separate weight read operations in which each read circuit generates a read current based on a stored weight value, and outputs the read current on the dedicated read control lines of the read circuit, and (ii) perform separate weight update operations in which each update circuit receives respective update control signals on the dedicated update control lines, generates update currents based on the respective update control signals, and applies the update current to the weight storage device to adjust the weight value based on the update current.

Abstract: Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.

Abstract: A resistive processing unit cell includes a weight storage device to store a weight value of the resistive processing unit cell, and multiple circuit blocks. Each circuit block includes a weight update circuit coupled to dedicated update control lines, and a weight read circuit coupled to dedicated read control lines. The circuit blocks are configured to operate in parallel to (i) perform separate weight read operations in which each read circuit generates a read current based on a stored weight value, and outputs the read current on the dedicated read control lines of the read circuit, and (ii) perform separate weight update operations in which each update circuit receives respective update control signals on the dedicated update control lines, generates update currents based on the respective update control signals, and applies the update current to the weight storage device to adjust the weight value based on the update current.

Abstract: Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.

Abstract: Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.

Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

Abstract: FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal.

Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.

Abstract: A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.

Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.

Abstract: Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.

Abstract: SOI structures with silicon layers less than 20 nm thick are used to form ETSOI semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and lowers the drain induced bias and sub-threshold swings. The structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, during STI and contact formation.

Abstract: A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs.

Abstract: A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs.

Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

Abstract: A method for playing an enterprise color ringback tone is disclosed, including the following steps: establishing, by a service switching entity, a connection with a service access entity in accordance with an EVC access code; searching, by the service access entity, for a connection identifier of a destination terminal corresponding to a service identifier of the destination terminal in accordance with a correspondence relationship between the service identifier and the connection identifier of the terminal, and sending the connection identifier of the destination terminal to the service switching entity; and establishing, by the service switching entity, a connection between the source terminal and the destination terminal in accordance with the connection identifier of the destination terminal, and playing an enterprise CRBT to the source terminal. A system and a device for playing an enterprise color ringback tone are also disclosed.

Abstract: Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings.

Abstract: Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.