Patents by Inventor Zhibin Ren
Zhibin Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8410544Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.Type: GrantFiled: September 9, 2011Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
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Patent number: 8338292Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.Type: GrantFiled: February 17, 2010Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
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Patent number: 8329564Abstract: A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure.Type: GrantFiled: October 26, 2007Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventors: Jin Cai, Amlan Majumdar, Tak H. Ning, Zhibin Ren
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Patent number: 8314463Abstract: A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure.Type: GrantFiled: August 18, 2009Date of Patent: November 20, 2012Assignee: International Business Machines CorporationInventors: Jin Cai, Amlan Majumdar, Tak H. Ning, Zhibin Ren
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Patent number: 8299546Abstract: A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.Type: GrantFiled: March 25, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Zhibin Ren, Kevin K. Chan, Chung-Hsun Lin, Xinhui Wang
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Patent number: 8288826Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: GrantFiled: November 7, 2011Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Patent number: 8236661Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.Type: GrantFiled: September 28, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Brian J. Greene, Zhibin Ren, Xinlin Wang
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Publication number: 20120168864Abstract: A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Dennard, Brian J. Greene, Zhibin Ren, Xinlin Wang
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Patent number: 8202780Abstract: A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.Type: GrantFiled: July 31, 2009Date of Patent: June 19, 2012Assignee: International Business Machines CorporationInventors: Zhibin Ren, Xinhui Wang, Kevin K. Chan, Ying Zhang
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Patent number: 8198673Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation.Type: GrantFiled: April 6, 2011Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: Haizhou Yin, Xinhui Wang, Kevin K. Chan, Zhibin Ren
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Patent number: 8149998Abstract: A method for playing an enterprise color ringback tone is disclosed, including the following steps: establishing, by a service switching entity, a connection with a service access entity in accordance with an EVC access code; searching, by the service access entity, for a connection identifier of a destination terminal corresponding to a service identifier of the destination terminal in accordance with a correspondence relationship between the service identifier and the connection identifier of the terminal, and sending the connection identifier of the destination terminal to the service switching entity; and establishing, by the service switching entity, a connection between the source terminal and the destination terminal in accordance with the connection identifier of the destination terminal, and playing, by the service access entity, an enterprise CRBT to the source terminal. A system and a device for playing an enterprise color ringback tone are also disclosed.Type: GrantFiled: July 29, 2009Date of Patent: April 3, 2012Assignee: Huawei Technologies Co., Ltd.Inventors: Guihua Li, Zhihong Sun, Yiqiang Bao, Zhibin Ren
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Publication number: 20120063583Abstract: A method for playing an enterprise color ringback tone is disclosed, including the following steps: establishing, by a service switching entity, a connection with a service access entity in accordance with an EVC access code; searching, by the service access entity, for a connection identifier of a destination terminal corresponding to a service identifier of the destination terminal in accordance with a correspondence relationship between the service identifier and the connection identifier of the terminal, and sending the connection identifier of the destination terminal to the service switching entity; and establishing, by the service switching entity, a connection between the source terminal and the destination terminal in accordance with the connection identifier of the destination terminal, and playing an enterprise CRBT to the source terminal. A system and a device for playing an enterprise color ringback tone are also disclosed.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Applicant: Huawei Technologies Co., Ltd.Inventors: Guihua LI, Zhihong SUN, Yiqiang BAO, Zhibin REN
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Publication number: 20120049317Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: ApplicationFiled: November 7, 2011Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Publication number: 20110316081Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.Type: ApplicationFiled: September 9, 2011Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
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Patent number: 8053373Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: GrantFiled: May 20, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Patent number: 8043920Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.Type: GrantFiled: September 17, 2009Date of Patent: October 25, 2011Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
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Publication number: 20110233688Abstract: A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhibin Ren, Kevin K. Chan, Chung-Hsun Lin, Xinhui Wang
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Publication number: 20110227159Abstract: Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings.Type: ApplicationFiled: March 16, 2010Publication date: September 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang
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Patent number: 8021956Abstract: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.Type: GrantFiled: January 6, 2010Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Zhibin Ren, Ghavam Shahidi, Dinkar V. Singh, Jeffrey W. Sleight, Xinhui Wang
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Patent number: 8012820Abstract: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.Type: GrantFiled: March 21, 2011Date of Patent: September 6, 2011Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Amlan Majumdar, Gen Pei, Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight