Abstract: An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.

Abstract: There are provided a method of manufacturing a display substrate, a method of manufacturing a display device, and a display substrate. The method of manufacturing a display substrate comprises: providing a base substrate; forming a thin film transistor on the base substrate; forming a first conductive layer on the base substrate on which the thin film transistor is formed, the first conductive layer being electrically connected to a drain of the thin film transistor; forming a light-emitting material block; and transferring the light-emitting material block to a surface of the first conductive layer.

Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.

Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.

Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket, a method of forming the TL-LGA socket, and a semiconductor package assembly. The TL-LGA socket includes interconnects having a vertical portion and a horizontal portion. The TL-LGA socket has a housing body, where the vertical portions are disposed in the housing body, and the interconnects are disposed in the housing body in a cascaded configuration. The interconnect may have the horizontal portion coupled to the vertical portion and a pad on a conductive base layer of a package. The conductive base layer may include pads and corresponding pad openings surrounding the pads. The TL-LGA socket may have the horizontal portion disposed between and parallel to the base layer and a top conductive layer of the housing body. The TL-LGA socket may have the base layer and/or the conductive layer coupled to a ground reference.

Abstract: High-speed data transmissions through a CPU socket are facilitated with CPU socket contacts that have a CPU socket contact body that improves bandwidth throughput. The CPU socket contact body is partially suspended from a CPU socket contact and may include a cavity. The CPU socket contact body includes capacitive impedance that substantially cancels an inductive impedance of the CPU socket contact. Canceling the inductive impedance causes the CPU socket contact to operate like an impedance-matched coaxial transmission line, which enables better bandwidth throughput than a non-impedance matched transmission line.

Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate. The electronic device package can also include a processor mounted on the package substrate. Additionally, the electronic device package can include a memory socket mounted on the package substrate and operably coupled to the processor. The memory socket can be operable to removably couple with a memory module and facilitate electrical communication between the processor and the memory module. A memory module can include a plurality of printed circuit boards (PCBs). Each PCB can have a bottom edge and a plurality of contact pads located about the bottom edge. Additionally, the memory module can include a memory device mounted on at least one of the plurality of PCBs and electrically connected to at least one of the pluralities of contact pads to facilitate electrically coupling the memory module with an external electronic component, such as a processor.

Abstract: One embodiment provides an apparatus. The apparatus includes a dual in-line memory module (DIMM). The DIMM includes at least one memory module integrated circuit (IC); a DIMM printed circuit board (PCB); a plurality of DIMM PCB contacts; and a capacitive structure. Each DIMM PCB contact is to couple the memory module IC to a respective DIMM connector pin. The capacitive structure is to provide a mutual capacitance between a first DIMM connector signal pin and a second DIMM connector signal pin.

Abstract: There are provided a method of manufacturing a display substrate, a method of manufacturing a display device, and a display substrate. The method of manufacturing a display substrate comprises: providing a base substrate; forming a thin film transistor on the base substrate; forming a first conductive layer on the base substrate on which the thin film transistor is formed, the first conductive layer being electrically connected to a drain of the thin film transistor; forming a light-emitting material block; and transferring the light-emitting material block to a surface of the first conductive layer.

Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.

Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.

Abstract: High-speed data transmissions through a CPU socket are facilitated with CPU socket contacts that have a CPU socket contact body that improves bandwidth throughput. The CPU socket contact body is partially suspended from a CPU socket contact and may include a cavity. The CPU socket contact body includes capacitive impedance that substantially cancels an inductive impedance of the CPU socket contact. Canceling the inductive impedance causes the CPU socket contact to operate like an impedance-matched coaxial transmission line, which enables better bandwidth throughput than a non-impedance matched transmission line.