Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support.

Abstract: An LED filament and an LED light bulb applying the same are provided. The LED filament includes a conductive section including a conductor; two or more LED sections connected to each other by the conductive section, and each of the LED sections includes two or more LED chips electrically connected to each other through a wire; two electrodes, electrically connected to the LED section; and a light conversion layer with a top layer and a base layer, covering the LED sections, the conductive section and the two electrodes, and a part of each of the two electrodes is exposed respectively. The LED filament is supplied with electric power no more than 8 W, when the LED filament is lit, at least 4 lm of white light is emitted per millimeter of filament length.

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

Abstract: An LED filament and an LED light bulb applying the same are provided. The LED filament includes a conductive section including a conductor; two or more LED sections connected to each other by the conductive section, and each of the LED sections includes two or more LED chips electrically connected to each other through a wire; two electrodes, electrically connected to the LED section; and a light conversion layer with a top layer and a base layer, covering the LED sections, the conductive section and the two electrodes, and a part of each of the two electrodes is exposed respectively. The LED filament is supplied with electric power no more than 8 W, when the LED filament is lit, at least 4 lm of white light is emitted per millimeter of filament length.

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

Abstract: A method and device for fingerprint recognition, a terminal, and a storage medium are provided, which belong to the technical field of information processing. The method is applicable to a terminal and includes the following. When a touch operation performed on a specified function widget of a current display interface of the terminal is detected and duration of the touch operation reaches preset duration, a fingerprint sensor disposed under a display area displaying the specified function widget is activated. Fingerprint information entered via the touch operation is collected with the fingerprint sensor. Security verification is performed on the fingerprint information. If the security verification of the fingerprint information passes, a function of the specified function widget is triggered.

Abstract: Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Abstract: A fingerprint identification method, a device, a mobile terminal, and a storage medium, belong to the technical field of information processing technology. The method is applied to a terminal, response to detecting a touch operation on a specified application icon, obtaining fingerprint information corresponding to the touch operation; transmitting the fingerprint information to an application corresponding to the specified application icon; the application performing a safety authentication to the fingerprint information; and response to determining that the fingerprint information passes the safety authentication, the application entering an application display interface.

Abstract: An LED filament and an LED light bulb applying the same are provided. The LED filament includes a conductive section including a conductor; two or more LED sections connected to each other by the conductive section, and each of the LED sections includes two or more LED chips electrically connected to each other through a wire; two electrodes, electrically connected to the LED section; and a light conversion layer with a top layer and a base layer, covering the LED sections, the conductive section and the two electrodes, and a part of each of the two electrodes is exposed respectively. The LED filament is supplied with electric power no more than 8W, when the LED filament is lit, at least 4 lm of white light is emitted per millimeter of filament length.

Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Abstract: A mask, a manufacturing method thereof, and a patterning method employing the mask. In the mask, a plurality of masks can be combined into one mask. The pattern area (01) of the mask is provided with a first pattern section (10) and a second pattern section (20) which are not overlapped with each other; light of a first wavelength can run through the first pattern section (10) but light of a second wavelength cannot run through the first pattern section; the light of the second wavelength can run thorough the second pattern section (20) but the light of the first wavelength cannot run through the second pattern section; and the light of the first wavelength and the light of the second wavelength can run through the non-pattern area, or any of the light of the first wavelength and the light of the second wavelength cannot run through the non-pattern area. The mask is obtained by combining a plurality of masks.

Abstract: A system for a three-dimensional (“3D”) printed circuit board (“PCB”) to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.