Abstract: The present invention proposes a method of forming a dual contact plug, comprising steps of: forming a source/drain region and a sacrificed gate structure on a semiconductor substrate, the sacrificed gate structure including a sacrificed gate; depositing a first inter-layer dielectric layer; planarizing the first inter-layer dielectric layer to expose the sacrificed gate in the sacrificed gate structure; removing the sacrificed gate and depositing to form a metal gate; etching to form a first source/drain contact opening in the first inter-layer dielectric layer; sequentially depositing a liner and filling conductive metal in the first source/drain contact opening to form a first source/drain contact plug; depositing a second inter-layer dielectric layer on the first inter-layer dielectric layer; etching to form a second source/drain contact opening and a gate contact opening in the second inter-layer dielectric layer; and sequentially depositing a liner and filling conductive metal in the second source/drain

Abstract: The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material.

Abstract: A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.

Abstract: A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer comprising a plurality of semiconductor sub-layers; and a plurality of fins formed in the semiconductor layer and adjoining the semiconductor layer, wherein at least two of the plurality of fins comprise different numbers of the semiconductor sub-layers and have different heights. According to the present disclosure, a plurality of semiconductor devices with different dimensions and different driving abilities can be integrated on a single wafer.

Abstract: The present invention relates to a semiconductor structure and a method for manufacturing the same.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under the backgates in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the backgates of the respective adjacent MOSFETs.

Abstract: Semiconductor devices and methods for manufacturing the semiconductor devices are disclosed. A semiconductor device includes a substrate, a fin formed above the substrate with a semiconductor layer formed between the substrate and the fin, and a gate stack crossing over the fin. The fin and the semiconductor layer may include different materials and have etching selectivity with respect to each other. A patterning of the fin can be stopped reliably on the semiconductor layer. Therefore, it is possible to better control the height of the fin and thus the channel width of the final device.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing a substrate, and forming a dielectric layer and a dummy gate layer on the substrate; performing doping and annealing to the dummy gate layer; patterning the dummy gate layer to form a dummy gate, wherein the top cross section of the dummy gate is larger than the bottom cross section of the dummy gate; forming sidewall spacers and source/drain regions; depositing an interlayer dielectric layer and planarizing the same; removing the dummy gate to form an opening within the sidewall spacers; and forming a gate in the opening. Accordingly, the present invention further provides a semiconductor structure.

Abstract: A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices.

Abstract: A method for manufacturing a transistor and a semiconductor device is provided. The method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack or a dummy gate stack, a source/drain extension region, a spacer and a source/drain region, wherein the source/drain extension region is embedded in the active area and self-aligned on both sides of the gate stack or dummy gate stack, the spacer surrounds the gate stack or dummy gate stack, and the source/drain region is embedded in the active area and self-aligned outside the spacer; removing at least a portion of the spacer to expose a portion of the active area; and forming an interlayer dielectric layer which covers the gate stack or dummy gate stack, the spacer and the exposed active area, wherein the dielectric constant of the material of the interlayer dielectric layer is smaller than that of the removed material of the spacer.

Abstract: The present invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the steps of providing a substrate on which a graphene layer or carbon nanotube layer is formed; exposing part of the graphene layer or carbon nanotube layer after forming a gate structure on the graphene layer or carbon nanotube layer, wherein the gate structure comprises a gate stack, a spacer and a cap layer, the cap layer is located on the gate stack, and the spacer surrounds the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; and forming a metal contact layer on the semiconductor layer. In the present invention, the semiconductor layer is formed on the graphene layer or carbon nanotube layer, and then the metal contact layer is formed on the semiconductor layer, instead of forming the metal contact layer directly from the graphene layer or carbon nanotube layer.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.

Abstract: Tensile stress is applied to the channel region of an N-type metal oxide semiconductor (NMOS) transistor by directly forming a material having a tensile stress, for example, tungsten, in the contact holes on the source region and drain region of the NMOS. Then, the dummy gate layer in the gate stack of the NMOS transistor is removed, so as to further reduce the counter force of the gate stack on the channel region, thereby increasing the tensile stress in the channel region, enhancing the drift mobility of the carrier, and improving the performance of the transistor. The present invention avoids using a separate stress layer to create tensile stress in the channel region of an NMOS transistor, which advantageously simplifies the transistor manufacturing process and improves sizes and performance of the transistor.

Abstract: The present invention relates to a method of forming an isolation structure and a semiconductor structure. The method of forming the isolation structure comprises the steps of: providing a silicon substrate having a (110) crystal plane or a (112) crystal plane and determining the [111] direction of the silicon substrate; forming first trenches in the silicon substrate by wet etching the silicon substrate, the extension direction of the first trenches being substantially perpendicular to the [111] direction; filling the first trenches with a first insulating material to form a first isolator; forming second trenches in the silicon substrate by dry etching the silicon substrate, the extension direction of the second trenches being perpendicular to the extension direction of the first trenches; filling the second trenches with a second insulating material to form a second isolator.

Abstract: An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.