Abstract: Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.

Abstract: A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located on the base region (100), and the base region (100) is supported on the substrate (130) by the support structure (131), wherein the sidewall cross-section of the support structure (131) is in a shape of a concave curve; an isolation structure (123) is formed beneath the edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and there exists a source/drain region at least on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.

Abstract: The present invention provides a semiconductor structure comprising: a semiconductor base located on an insulating layer, wherein the insulating layer is located on a semiconductor substrate; source/drain regions, which are in contact with first sidewalls of the semiconductor base opposite to each other; gates located on second sidewalls of the semiconductor base opposite to each other; an insulating via located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer sandwiched between the insulating via and the semiconductor base. The present invention further provides a method for manufacturing a semiconductor structure comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor base on the insulating layer; forming a void within the semiconductor base, wherein the void exposes the semiconductor substrate; forming an epitaxial layer in the void through selective epitaxy; and forming an insulating via within the void.

Abstract: A semiconductor structure is provided, comprising a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located above the base region (100), and the base region (100) is supported above the substrate (130) by the support structure (131), wherein the support structure (131) has a sigma-shaped lateral cross-section; an isolation structure (123) is formed below edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and a source/drain region is formed on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also provided.

Abstract: The present invention relates to enhancing MOSFET performance with the corner stresses of STI.

Abstract: The present invention provides a solar cell unit, which comprises a semiconductor plate of first-type doping or second-type doping; wherein the semiconductor plate has a first surface and a second surface opposite to the first surface; the semiconductor plate comprises a first-type doping region and second-type doping region, both the first-type doping region and the second-type doping region are located on the first surface of the semiconductor plate; a first sheet is provided on the side surface of the semiconductor plate that is adjacent to the first-type doping region, and a second sheet is provided on the side surface of the semiconductor plate that is adjacent to the second type doping region.

Abstract: Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.

Abstract: A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.

Abstract: Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

Abstract: Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled.

Abstract: The devices are manufactured by replacement gate process and replacement sidewall spacer process, and both tensile stress in the channel region of NMOS device and compressive stress in the channel region of PMOS device are increased by forming a first stress layer with compressive stress in the space within the first metal gate layer of NMOS and a second stress layer with tensile stress in the space within the second metal gate layer of PMOS, respectively. After formation of the stress layers, sidewall spacers of the gate stacks of PMOS and NMOS devices are removed so as to release stress in the channel regions. In particular, stress structure with opposite stress may be formed on sidewalls of the gate stacks of the NMOS device and PMOS device and on a portion of the source region and the drain region, in order to further increase both tensile stress of the NMOS device and compressive stress of the PMOS device.

Abstract: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs.

Abstract: Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.

Abstract: A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates.

Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate, which comprises, from top to bottom, an SOI layer (100), a BOX layer (110) and a base layer (130); forming a dummy gate stack on the SOI substrate and an implantation barrier layer on both sides of the dummy gate stack; removing the dummy gate stack to form a gate recess (220); and performing, via the gate recess (220), implantation of stress inducing ions to the semiconductor structure and annealing to form, right below the gate recess (220), a stress inducing region (150) under the BOX layer (110) of the SOI substrate. Accordingly, the present invention further provides a semiconductor structure manufactured according to the above method.

Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.

Abstract: A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.