Abstract: A method for detecting a bright dot or a dark dot in a LCD comprising applying a first detection voltage to a color filter substrate common electrode and forming a first voltage difference between the color filter substrate common electrode and a pixel electrode on an array substrate; collecting a first luminance value of the bright dot or the dark dot after the bright dot or the dark dot is observed; switching the first detection voltage applied to the color filter substrate common electrode to a second detection voltage, and thus forming a second voltage difference between the color filter substrate common electrode and the pixel electrode; collecting a second luminance value of the bright dot or the dark dot; determining the difference between the first luminance value and the second luminance value, so that the bright dot or the dark dot can be determined to result from a liquid crystal cell defect or an array substrate defect.

Abstract: Embodiments of the invention relates to a metal thin film connection structure, comprising a first metal layer pattern; a second metal layer pattern which is separately disposed with the first metal layer pattern; a first insulating layer formed on the first metal layer pattern and the second metal layer pattern; a plurality of first via holes formed over the first metal layer pattern; a plurality of second via holes formed over the second metal layer pattern; and a plurality of third metal layer patterns formed on the first insulating layer, the third metal layer patterns being filled in the first via holes and the second via holes and electrically connect the first metal layer pattern and the second metal layer pattern through the first and second via holes. The embodiments of the invention also provide an array substrate comprising the metal thin film connection structure and a manufacturing method for the metal thin film connection structure.

Abstract: An array substrate of a LCD and a method for repairing a broken line thereof are provided. The array substrate comprises pixel regions defined by the gate lines and the data lines, and each of the pixel regions comprises a thin film transistor and a pixel electrode. At least two overlapping strips are formed between two adjacent pixel regions, one end of the overlapping strip overlap the pixel electrode within one the pixel regions, the other end thereof overlaps the pixel electrode within the other pixel regions, and the central portion thereof overlaps the gate line and/or the data line. The repairing method comprises connecting two parts of the broken gate line and/or data line on both sides of the breaking point again through the overlapping strip and the pixel electrode, and disabling the TFT corresponding to the pixel electrode by laser cutting.

Abstract: The invention provides a method for forming a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The formed testing wiring structure comprises a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring. A pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring. The pixel electrode layer testing wiring is electrically connected to the drain layer metallic testing wiring to be a redundant testing wiring of the drain layer metallic testing wiring.

Abstract: The invention provides a method for forming a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The formed testing wiring structure comprises a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring. A pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring. The pixel electrode layer testing wiring is electrically connected to the drain layer metallic testing wiring to be a redundant testing wiring of the drain layer metallic testing wiring.

Abstract: An embodiment of the invention provide a liquid crystal panel comprising a driving chip assembly comprising: a chip lead wiring and a chip repair line, which are overlapped but insulated from each other; an array substrate comprising an array substrate lead wiring and an array substrate repair line, which are overlapped but insulated from each other; wherein the driving chip assembly is mounted on the array substrate which is electrically connected with the corresponding chip lead wiring connection, and the two ends of the chip repair line is electrically connected with the corresponding two ends of the array substrate repair line respectively.

Abstract: The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The testing wiring structure comprises a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring. The gate layer metallic testing wiring are connected to a portion of the plurality of signal lines and the drain layer metallic testing wiring both are connected to remaining portion of the plurality of signal lines. A pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring.

Abstract: Embodiments of the invention relates to a metal thin film connection structure, comprising a first metal layer pattern; a second metal layer pattern which is separately disposed with the first metal layer pattern; a first insulating layer formed on the first metal layer pattern and the second metal layer pattern; a plurality of first via holes formed over the first metal layer pattern; a plurality of second via holes formed over the second metal layer pattern; and a plurality of third metal layer patterns formed on the first insulating layer, the third metal layer patterns being filled in the first via holes and the second via holes and electrically connect the first metal layer pattern and the second metal layer pattern through the first and second via holes. The embodiments of the invention also provide an array substrate comprising the metal thin film connection structure and a manufacturing method for the metal thin film connection structure.

Abstract: A mask comprises a channel region half-exposure mask structure, a drain mask structure, and a source mask structure, wherein the channel region half-exposure mask structure comprises a channel region peripheral half-exposure mask structure, which extends from a portion that corresponds to a channel region of the TFT and is outside the portion. According to the present invention, problems such as a connection of the source/drain and a disconnection of the active layer in the channel region can be effectively prevented.

Abstract: An array substrate comprises a plurality of pixel units defined by interacting of a plurality of gate lines along a row direction and a plurality of data lines along a column direction, and a pixel electrode formed within each of the pixel units. Each row of the pixel units are provide with a first gate line and a second gate line in the gate lines, and each of the pixel units is provides with a first thin film transistor and a second thin film transistor; the first thin film transistor is connected with the first gate line, and the second thin film transistor is connected with the second gate line; the first thin film transistor is connected with the data line at one side of the pixel unit, and the second thin film transistor is connected with the data line at the other side of the pixel unit, and the second thin film transistors of the pixel units in one row and the first thin film transistors of the pixel units in an adjacent row within the same columns are connected to the same column of the data lines.

Abstract: The present invention provides an array substrate and a method for manufacturing the same. The array substrate comprises a substrate and a plurality of gate lines parallel to each other and a plurality of data lines parallel to each other formed on the substrate, the gate lines intersecting the data lines to define a plurality of pixel region arranged in a matrix, each pixel region comprising a thin film transistor, a pixel electrode and a thin film diode. With respect to each pixel region in a row, the pixel electrode is connected with the gate line in the present row through the thin film transistor and is connected with the gate line in a previous row through the thin film diode.

Abstract: A test substrate for measuring contact force and a method for measuring contact force are provided in the technology. The substrate may comprises: a base substrate, and a piezoelectric element provided on a surface of the base substrate. One end of the piezoelectric portion is a detecting voltage input terminal and the other end thereof is a detecting voltage output terminal. According to the technology, the substrate and method for measuring contact force can be used to measure the contact force applied to the substrate by the cleaning apparatus or conveying apparatus, and thus the contact force can be properly controlled and the adverse influence on the substrate from the conveying apparatus or cleaning apparatus can be decreased or eliminated.

Abstract: Provided is a thin film transistor liquid crystal display (TFT LCD), comprising a color filter substrate and an array substrate disposed opposite to each other; wherein the array substrate comprises a base substrate, data lines and gate lines formed on the base substrate, and an insulating protective layers on the data lines or gate lines; the color filter substrate and the array substrate are assembled with each other in a peripheral portion with sealant mixed with metal micro-balls at a ratio, and a top conductive film is formed on the insulating protective layer above the data lines or gate lines below the sealant in the peripheral portion.

Abstract: A detection circuit and a detection method for liquid crystal display are provided. The detection circuit comprises gate driver for providing row scan signal to liquid crystal cell to be detected; signal source for providing polarity inversion signal to source driver, polarity inversion signal comprises continuous high level signal and continuous low level signal; source driver for performing digital-analogue conversion on received display data signal according to preset reference voltage and polarity inversion signal, generating pixel voltage signal, and sending pixel voltage signal to liquid crystal cell to be detected, polarity inversion mode formed by pixel voltage signal is column inversion mode. The polarity inversion mode of column inversion, formed by pixel voltage signal in technical solution makes white dot of damaged area of alignment film is more prominent during detection process, so it would be easy for the operator to recognize it and avoid the issue of missing detection.

Abstract: A method for detecting line broken faults of common electrode lines of liquid crystal display comprising: loading detection picture to the liquid crystal display, wherein said detection picture comprises at least one detection picture for line broken of common electrode lines, wherein, in the detection picture of same frame, the voltage difference of storage capacitor corresponding to pixel electrode with one polarity is larger than voltage difference of a storage capacitor corresponding to pixel electrode with another polarity; when the detection picture for line broken of common electrode line is displayed on the liquid crystal display, detecting whether there is black line or white line gradually changed in horizontal direction in said detection picture for line broken of common electrode line, and determining line broken fault of common electrode line exists in the liquid crystal display when there is a black line or white line gradually changed in horizontal direction.

Abstract: The present invention discloses a switch control unit, a test apparatus and method for a liquid crystal cell. The switch control unit controls a signal input to the liquid crystal display driver and controls the output of the signal from the liquid crystal display driver accordingly, and includes a control signal generator and a switch module. The test apparatus for the liquid crystal cell comprises: a switch control unit connected with a gate driver, for controlling ON and OFF of a signal input to the gate driver and controlling ON and OFF of a gate scan signal accordingly. The test method for the liquid crystal cell comprises: inputting a test signal; controlling ON and OFF of a gate scan signal by controlling ON and OFF of a signal input to a gate driver so as to determine the badness positions on a screen.

Abstract: A method for detecting a bright dot or a dark dot in a LCD comprising applying a first detection voltage to a color filter substrate common electrode and forming a first voltage difference between the color filter substrate common electrode and a pixel electrode on an array substrate; collecting a first luminance value of the bright dot or the dark dot after the bright dot or the dark dot is observed; switching the first detection voltage applied to the color filter substrate common electrode to a second detection voltage, and thus forming a second voltage difference between the color filter substrate common electrode and the pixel electrode; collecting a second luminance value of the bright dot or the dark dot; determining the difference between the first luminance value and the second luminance value, so that the bright dot or the dark dot can be determined to result from a liquid crystal cell defect or an array substrate defect.

Abstract: An array substrate of a LCD and a method for repairing a broken line thereof are provided. The array substrate comprises pixel regions defined by the gate lines and the data lines, and each of the pixel regions comprises a thin film transistor and a pixel electrode. At least two overlapping strips are formed between two adjacent pixel regions, one end of the overlapping strip overlap the pixel electrode within one the pixel regions, the other end thereof overlaps the pixel electrode within the other pixel regions, and the central portion thereof overlaps the gate line and/or the data line. The repairing method comprises connecting two parts of the broken gate line and/or data line on both sides of the breaking point again through the overlapping strip and the pixel electrode, and disabling the TFT corresponding to the pixel electrode by laser cutting.

Abstract: An embodiment of the invention provides a method for repairing a broken signal line of a liquid crystal display device, comprising determining a position of a breaking point on the broken signal line and a pixel where the breaking point is located on an array substrate; and welding two parts of the broken signal line at both sides of the breaking point to a pixel electrode of the pixel by laser welding and disabling a thin film transistor as a switching device of the pixel by laser cutting. Also, there is provided a liquid crystal display device.

Abstract: The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The testing wiring structure comprises a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring. The gate layer metallic testing wiring are connected to a portion of the plurality of signal lines and the drain layer metallic testing wiring both are connected to remaining portion of the plurality of signal lines. A pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring.