Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: The present disclosure relates generally to ion implantation, and more particularly, to systems and processes for adjusting a ribbon beam angle of an ion implantation system. An exemplary ion implantation system includes an ion source configured to generate a ribbon beam, a wafer chuck configured to hold a wafer during implantation by the ribbon beam, a dipole magnet disposed between the ion source and the wafer chuck, and a controller. The dipole magnet includes at least two coils configured to adjust a ribbon beam angle of the ribbon beam at one or more locations along a path of the ribbon beam between the ion source and the wafer held in the wafer chuck. The controller is configured to control the ion source, the wafer chuck, and the dipole magnet.

Abstract: Methods and apparatuses for providing an anisotropic ion beam for etching and treatment of substrate are discussed. In one embodiment, a system for processing a substrate includes a chamber, a chuck assembly, an ion source, and a grid system. The ion source includes grid system interfaces both the chamber and the ion source and includes a plurality of holes through which ions are extracted from the ion source to form an ion beam. The grid system is oriented so the ion beam is directed into the chamber toward the substrate support, and the array of holes of the grid system is defined vertically by a y-axis and horizontally by an x-axis, The array of holes is defined by hole densities that vary vertically in the y-axis such that the ion beam is caused to have an energy density gradient that is defined vertically in the y-axis.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.

Abstract: The present disclosure relates generally to ion implantation, and more particularly, to systems and processes for adjusting a ribbon beam angle of an ion implantation system. An exemplary ion implantation system includes an ion source configured to generate a ribbon beam, a wafer chuck configured to hold a wafer during implantation by the ribbon beam, a dipole magnet disposed between the ion source and the wafer chuck, and a controller. The dipole magnet includes at least two coils configured to adjust a ribbon beam angle of the ribbon beam at one or more locations along a path of the ribbon beam between the ion source and the wafer held in the wafer chuck. The controller is configured to control the ion source, the wafer chuck, and the dipole magnet.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: An integrated circuit package includes a first die and second die above a substrate, and a vapor chamber above at least one of the first and second die. A vapor space within the vapor chamber is separated into at least a first section and a second section. The first section may be over the first die, and the second section may be over the second die, for example. The structure separating the first and second sections at least partly restricts flow of vapor between the first and second sections, thereby preventing or reducing thermal cross talk between the first and second dies. In some cases, an anisotropic thermal material is above one of the first or second die, wherein the anisotropic thermal material has substantially higher thermal conductivity in a direction of a heat sink than a thermal conductivity in a direction of a section of the vapor chamber.

Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.

Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.

Abstract: The present disclosure belongs to the technical field of virus immunoassay and provides a broad-spectrum peptide antigen of SARS-CoV-2, a specific neutralizing antibody and use thereof. A broad-spectrum peptide antigen of SARS-CoV-2, with an amino acid sequence set forth in SEQ ID NO: 1, reacts with human SARS-CoV-2 positive serum, and can specifically bind to a novel coronavirus antibody. Based on the peptide sequence of the present disclosure, a fusion protein with broad-spectrum triple tandem peptides of SARS-CoV-2 is prepared using PCR, prokaryotic expression and protein purification technology to simulate the trimeric mode of SARS-CoV-2 S protein in its natural state. The fusion protein is used as an antigen to immunize mice, and can produce a specific anti-SARS-CoV-2 neutralizing antibody. The neutralizing antibody may be promising in anti-infective treatment, vaccine development and detection kit development for SARS-CoV-2.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

Abstract: A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.