Patents by Inventor Zhimin Wan

Zhimin Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11558207
    Abstract: Provided are a method and apparatus for starting up a blockchain system and a non-transitory computer-readable a storage medium. The method includes operating a main program of a blockchain system to initialize a kernel engine and a kernel component, wherein the main program of the blockchain system comprises an initialization method of the kernel engine and an initialization method of at least one kernel component; obtaining operation configuration information of the blockchain system through a program configuration file to instantiate the kernel engine and the kernel component, wherein the operation configuration information of the blockchain system comprises specification selection information of the kernel engine and specification selection information of the at least one kernel component; starting up and operating the kernel engine and the main program of the blockchain system; and starting up a port monitoring service to operate the blockchain system.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: January 17, 2023
    Assignee: Beijing Baidu Netcom Science Technology Co., Ltd.
    Inventors: Chunhui Wan, Zhimin Wei, Tong Jin
  • Publication number: 20230005701
    Abstract: The present disclosure relates generally to ion implantation, and more particularly, to systems and processes for adjusting a ribbon beam angle of an ion implantation system. An exemplary ion implantation system includes an ion source configured to generate a ribbon beam, a wafer chuck configured to hold a wafer during implantation by the ribbon beam, a dipole magnet disposed between the ion source and the wafer chuck, and a controller. The dipole magnet includes at least two coils configured to adjust a ribbon beam angle of the ribbon beam at one or more locations along a path of the ribbon beam between the ion source and the wafer held in the wafer chuck. The controller is configured to control the ion source, the wafer chuck, and the dipole magnet.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Applicant: Advanced Ion Beam Technology, Inc.
    Inventors: Zhimin WAN, Chi-ming HUANG, Shao-Yu HU
  • Publication number: 20220400018
    Abstract: Provided are a method and apparatus for starting up a blockchain system and a non-transitory computer-readable a storage medium. The method includes operating a main program of a blockchain system to initialize a kernel engine and a kernel component, wherein the main program of the blockchain system comprises an initialization method of the kernel engine and an initialization method of at least one kernel component; obtaining operation configuration information of the blockchain system through a program configuration file to instantiate the kernel engine and the kernel component, wherein the operation configuration information of the blockchain system comprises specification selection information of the kernel engine and specification selection information of the at least one kernel component; starting up and operating the kernel engine and the main program of the blockchain system; and starting up a port monitoring service to operate the blockchain system.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 15, 2022
    Applicant: Beijing Baidu Netcom Science Technology Co., Ltd.
    Inventors: Chunhui WAN, Zhimin WEI, Tong JIN
  • Patent number: 11521914
    Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Cheng Xu, Yikang Deng, Junnan Zhao, Ying Wang, Chong Zhang, Kyu Oh Lee, Chandra Mohan Jha, Chia-Pin Chiu
  • Patent number: 11502017
    Abstract: An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Zhimin Wan, Lingtao Liu, Yikang Deng, Junnan Zhao, Chandra Mohan Jha, Kyu-oh Lee
  • Patent number: 11482471
    Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
  • Patent number: 11456232
    Abstract: Disclosed herein are thermal assemblies for multi-chip packages (MCPs), as well as related methods and devices. For example, in some embodiments, a thermal assembly for an MCP may include a heat pipe having a ring shape.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 27, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Je-Young Chang, Chia-Pin Chiu, Shankar Devasenathipathy, Betsegaw Kebede Gebrehiwot, Chandra Mohan Jha
  • Patent number: 11444003
    Abstract: An integrated heat spreader includes channel structures assembled in a frame. Each channel structure is independent of the other, and can be used to dissipate heat from integrated circuitry at a specific location within a package, and without allowing heat from that particular location to propagate to integrated circuitry at other locations within the package. Each channel structure can be implemented with metal having a high thermal conductivity (e.g., copper). The channel structures can be used in conjunction with liquid-based cooling or air-based cooling. The frame can be implemented with low thermal conductivity molding compound or plastic so the heat transfer from one channel structure to another is inhibited. The channel structures can have different configurations (e.g., straight, pillars, and/or pin fins) to provide different rates of flow, mixing, and/or cooling. The flow direction of air or liquid for the channel structures can be the same (parallel) or different (counter).
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chia-Pin Chiu, Chandra Mohan Jha, Weihua Tang, Shankar Devasenathipathy
  • Publication number: 20220263670
    Abstract: Provided are a method and apparatus for operating a blockchain system, a device and a storage medium. The method is described below. To-be-processed blockchain data is acquired through a kernel engine of a blockchain system. The to-be-processed blockchain data is processed through the kernel engine, and a kernel component interface provided by a component adaptor is called during the processing process of the to-be-processed blockchain data to call a kernel component.
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Applicant: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventors: Chunhui WAN, Tong JIN, Zhimin WEI, Jiaxiang LIU, Lei ZHANG, Bingxin FAN
  • Patent number: 11398414
    Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chia-Pin Chiu, Pooya Tadayon, Joe F. Walczyk, Chandra Mohan Jha, Weihua Tang, Shrenik Kothari, Shankar Devasenathipathy
  • Patent number: 11387224
    Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Zhimin Wan, Yikang Deng, Junnan Zhao, Chong Zhang, Chandra Mohan M Jha, Ying Wang, Kyu-oh Lee
  • Publication number: 20220199482
    Abstract: Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Chia-Pin CHIU, Zhimin WAN, Peng LI, Deepak GOYAL
  • Publication number: 20220102624
    Abstract: One or more layers of a magnetic random access memory (MRAM) stack on a substrate are etched by ion beam etching. An ion beam of an inert gas is generated in an ion beam source chamber and applied to a substrate in a continuous or pulsed manner. Without passing through the ion beam source chamber, a reactive gas is flowed directly into a processing chamber in which the substrate is located, where the reactive gas is pulsed or continuously provided into the processing chamber. The reactive gas may include a carbon-containing gas having a hydroxyl group that is flowed towards the substrate to limit re-deposition of sputtered atoms on exposed surfaces of the substrate from ion beam etching.
    Type: Application
    Filed: January 29, 2020
    Publication date: March 31, 2022
    Inventors: Seokmin YUN, Zhimin WAN, Shuogang HUANG, Weiyi LI, Gowri Channa KAMARTHY
  • Patent number: 11222877
    Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Robert L. Sankman, Nitin A. Deshpande, Mitul Modi, Thomas J. De Bonis, Robert M. Nickerson, Zhimin Wan, Haifa Hariri, Sri Chaitra J. Chavali, Nazmiye Acikgoz Akbay, Fadi Y. Hafez, Christopher L. Rumer
  • Publication number: 20210398966
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.
    Type: Application
    Filed: August 31, 2021
    Publication date: December 23, 2021
    Inventors: Robert L. Sankman, Pooya Tadayon, Weihua Tang, Chandra M. Jha, Zhimin Wan
  • Patent number: 11127727
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Pooya Tadayon, Weihua Tang, Chandra M. Jha, Zhimin Wan
  • Publication number: 20210257277
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 19, 2021
    Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
  • Publication number: 20210249324
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Inventors: Zhimin WAN, Chia-Pin CHIU, Chandra Mohan JHA
  • Publication number: 20210193548
    Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Zhimin WAN, Chia-Pin CHIU, Peng LI, Shankar DEVASENATHIPATHY
  • Publication number: 20210193552
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Zhimin WAN, Jin YANG, Chia-Pin CHIU, Peng LI, Deepak GOYAL