Abstract: The present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (S/D) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an S/D epitaxial feature interfacing both the S/D formation assistance region and lateral ends of the channel layers. The S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer. The isolation layer separates the semiconductor seed layer from physically contacting the substrate.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

Abstract: The present invention provides a diaryl compound as a tubulin/Src dual target inhibitor. The present invention also provides a diaryl compound represented by formula I, a tautomer, a stereoisomer, a solvate, a pharmaceutically acceptable salt, or a prodrug thereof. The diaryl compound can be used as a dual target inhibitor against tubulin and Src kinase and can also be used as a mono-target inhibitor against tubulin or Src kinase. The compound of the present invention can significantly inhibit the polymerization of tubulin monomers and cell proliferation.

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of at least one of the particles with a ray-tracing method, identifying a voxel unit in the voxel mesh that intersects the flight path, determining a surface reaction between the one of the particles and the voxel unit, and adding an extra voxel unit adjacent to the voxel unit based on the determining of the surface reaction.

Abstract: A method for forming a semiconductor memory structure includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.

Abstract: A magnetic tunnel junction (MTJ) structure and a memory cell are provided. The MTJ includes a barrier layer, a free layer and a metal oxide cap layer. The free layer is disposed on the barrier layer. The metal oxide cap layer is disposed on the free layer. The metal oxide cap layer has a first surface and a second surface opposite to the first surface. The first surface of the metal oxide cap layer is in contact with the free layer. In a direction of a thickness of the metal oxide cap layer, both of an oxygen concentration at the first surface of the metal oxide cap layer and an oxygen concentration at the second surface of the metal oxide cap layer are higher than an oxygen concentration in a middle portion of the metal oxide cap layer.

Abstract: An assembled sliding frame for trailer, including longitudinal beams each including a top wall, a side wall, and a bottom wall, with an opening formed between inner edges of the top wall and the bottom wall; transverse beams each including a top plate, two side plates, a bottom plate, and an end plate. The top plate is fixedly connected to the top wall by a first bolt extending traversely therethrough; brackets each including an outer bracket, an inner bracket, and a connecting base. The outer bracket has a flat portion abutting against an outer surface of the side wall, the flat portion, the side wall and the end plate are fixedly connected by using a second bolt extending traversely therethrough. The inner bracket is fixedly connected with a connecting plate, and the connecting plate is fixedly connected to the bottom plate by using a second bolt extending traversely therethrough.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: A semiconductor device includes a substrate including a planar portion and a mesa portion over the planar portion; an oxide layer over the mesa portion; a ferroelectric material strip covering a protruding plane of the oxide layer and exposing a side plane of the oxide layer; and a gate strip over the ferroelectric material strip and overlapping the oxide layer.

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Abstract: A locking mechanism of a trailer carriage includes a transmission shaft, two bolts, an airbag, and a swing arm. The transmission shaft is pivoted to the carriage and extends in a length direction of the carriage; the two bolts are movably connected to two sides of the carriage in a penetrating manner, the bolt is movable in a width direction of the carriage between a first position where the bolt is accommodated in the carriage and a second position where the bolt protrudes from a side edge of the carriage; and one end of the swing arm is connected to the transmission shaft and a connecting seat is formed at the other end of the swing arm, and one end of the airbag is connected to the carriage and the other end of the airbag is connected to the connecting seat.

Abstract: A trailer carriage includes two longitudinal beams and at least two cross beams between the two longitudinal beams. The longitudinal beam includes a side wall, an upper connecting wall and a lower connecting wall. The cross beam includes an upper connecting plate, a lower connecting plate below the upper connecting plate, and an end plate between the upper connecting plate and the lower connecting plate. The upper connecting plate abuts against a bottom of the upper connecting wall, the lower connecting plate abuts against a top of the lower connecting wall, the end plate abuts against an inner side of the side wall. The upper connecting plate is connected with the upper connecting wall via a first huck bolt, the lower connecting plate is connected with the lower connecting wall via a second huck bolt, the end plate is connected with the side wall via a third huck bolt.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a stack of first semiconductor layers and second semiconductor layers over a substrate, etching the stack to form a source/drain (S/D) recess in exposing the substrate, and forming an S/D formation assistance region in the S/D recess. The S/D formation assistance region is partially embedded in the substrate and includes a semiconductor seed layer embedded in an isolation layer. The isolation layer electrically isolates the semiconductor seed layer from the substrate. The method also includes epitaxially growing an S/D feature in the S/D recess from the semiconductor seed layer. The S/D feature is in physical contact with the second semiconductor layers.

Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

Abstract: Provided is a sliding frame for trailers, which includes a side beam, wherein the side beam includes a horizontally extending top wall and a vertically extending side wall, an upper surface of the top wall is provided with a wear-resistant pad extending along the length direction of the side beam; a guide rail clip is fixed on an outer surface of the side wall, wherein the guide rail clip includes a connection part fixed to the side wall, and a limiting part located above the connection part, and a backing plate is sandwiched between the connection part and the side wall, a part of the backing plate extends upward to an inner side of the limiting part, and a gap with openings at the top and both front and rear ends is formed between the limiting part and the backing plate.

Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.

Abstract: A method includes: providing a substrate including a planar portion and a mesa portion over the planar portion; depositing an oxide layer over the mesa portion; depositing a ferroelectric material strip over the oxide layer and aligned with the mesa portion; and depositing a gate strip crossing the ferroelectric material strip and over the oxide layer.

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.