Patents by Inventor Zhiqiang Wu

Zhiqiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101667
    Abstract: Provided herein are methods and compositions for the identification of modulators of LILRB3 activation. Also provided herein are methods of treating cancer comprising the administration of an inhibitor LILRB3 activation. Also provided are methods of treating autoimmune disease or inhibiting the onset of transplant rejection or treating an inflammatory disorder comprising administering an agonist of LILRB3 activation to a subject.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 28, 2024
    Inventors: Chengcheng ZHANG, Guojin WU, Jaehyup KIM, Heyu CHEN, Mi DENG, Zhiqiang AN, Ningyan ZHANG, Ryan HUANG
  • Patent number: 11942134
    Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Sheng Wei, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 11938639
    Abstract: A boundary protection method and system of a radiation detection robot. The boundary protection method comprises: a first laser radar and a second laser radar are arranged diagonally, a first marking rod and a second marking rod are arranged diagonally; a boundary of an interlocking zone is defined by the first laser radar, the second laser radar, the first marking rod and the second marking rod; the object to be detected is placed in the interlocking zone; the radiation detection robot uses rays to detect the object to be detected in the interlocking zone; an early warning zone is provided outside the interlocking zone; wherein when it is detected that a person or object has intruded into the interlocking zone, the radiation detection robot stops emitting rays; and when it is detected that a person or object has intruded into the early warning zone, a warning is issued directly.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: March 26, 2024
    Assignees: TSINGHUA UNIVERSITY, NUCTECH COMPANY LIMITED
    Inventors: Zhiqiang Chen, Jin Cui, Bin Hu, Dong Lin, Huawei Wu
  • Publication number: 20240099066
    Abstract: Disclosed are a display substrate. The display substrate includes a drive backplane; a first electrode layer disposed on a side of the drive backplane; a pixel definition layer disposed on a side, distal to the drive backplane, of the first electrode layer; an organic light-emitting layer disposed on a side, distal to the drive backplane, of the pixel definition layer, wherein the organic light-emitting layer comprises: a plurality of organic material layers stacked in a direction perpendicular to and away from the drive backplane, and a portion of the organic material layer disposed inside the partition groove is separated from a portion of the organic material layer disposed outside the partition groove; and a second electrode layer disposed on a side, distal to the drive backplane, of the organic light-emitting layer.
    Type: Application
    Filed: May 31, 2022
    Publication date: March 21, 2024
    Applicants: Yunnan Invensight Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yuhao LEE, Xue DONG, Xiaochuan CHEN, Hui TONG, Xiaobin SHEN, Kuanta HUANG, Cao WU, Weiliang BU, Hui WANG, Zhiqiang JIAO
  • Publication number: 20240063263
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 ?1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Tzer-Min SHEN, Zhiqiang WU
  • Patent number: 11908919
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11889674
    Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Publication number: 20240023338
    Abstract: A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Chun Liou, Zhiqiang Wu, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin
  • Publication number: 20240016066
    Abstract: A memory device includes a substrate, a reference layer, a tunneling layer, a film stack, and a capping layer. The reference layer is disposed on the substrate. The tunneling layer is disposed on the reference layer. The film stack is formed over the tunneling layer and on the substrate, wherein the film stack includes a first free layer, a spacer with high exchange stiffness constant and a second free layer. The first free layer is in contact with the tunneling layer and the film stack. The spacer with high exchange stiffness constant is sandwiched between the first free layer and the second free layer. The capping layer is disposed on and electrically connected to the film stack.
    Type: Application
    Filed: July 10, 2022
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Sheng Lu, Zhi-Ren Xiao, Nuo Xu, Zhiqiang Wu
  • Patent number: 11862218
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a memory cell array comprising a plurality of magnetic tunnel junction (MTJ) memory cells arranged in columns and rows, a read bias circuit connected to the memory cell array and configured to provide a reading bias for a MTJ memory cell of the memory cell array, and a first non-linear resistance device connected in series and between the MTJ memory cell and the read bias circuit. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gaurav Gupta, Zhiqiang Wu
  • Publication number: 20230420506
    Abstract: A method includes forming a channel region above a (110)-orientated substrate and having a length extending in a <100> direction; epitaxial growing a plurality of source/drain regions on either side the channel region; forming a gate structure surrounding the channel region; forming a plurality of source/drain contacts on the source/drain regions.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju LEE, Chun-Fu CHENG, Chung-Wei WU, Zhiqiang WU
  • Patent number: 11855143
    Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20230411480
    Abstract: A method of forming a semiconductor device includes forming a fin on a substrate, the fin comprising alternately stacked first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form a plurality of spaces each between adjacent two of the second semiconductor layers, implanting oxygen into the second semiconductor layers, and forming a gate structure wrapping around the second semiconductor layers.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhi-Ren XIAO, Nuo XU, Zhiqiang WU
  • Publication number: 20230411399
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: July 20, 2023
    Publication date: December 21, 2023
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20230413571
    Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device also includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device further includes a ferroelectric layer in contact with the channel layer.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Inventors: Wen-Ling LU, Yu-Chien CHIU, Chih-Yu CHANG, Hung-Wei LI, Ya-Yun CHENG, Zhiqiang WU, Yu-Ming LIN, Mauricio MANFRINI
  • Patent number: 11849589
    Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a first conductive region and a second conductive region at the first surface, wherein the first conductive region is apart from the second conductive region, a gate feature, wherein a top surface of the gate feature is above the first conductive region, a stack unit coupled to the first conductive region, wherein the stack unit includes a plurality of ferroelectric layers stacking with a plurality of metal layers, wherein each of the plurality of ferroelectric layers separates adjacent two metal layers.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Jong Chia, Yu-Ming Lin, Zhiqiang Wu, Sai-Hooi Yeong
  • Patent number: 11843032
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Siang Lan, Sathaiya Mahaveer Dhanyakumar, Tzer-Min Shen, Zhiqiang Wu
  • Publication number: 20230394641
    Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of one of the particles with a ray-tracing method by a parallel processing thread in a hardware accelerator, identifying a surface normal of a voxel unit in the voxel mesh that intersects the flight path by the parallel processing thread, determining a surface reaction between the one of the particles and the voxel unit by a central processing unit (CPU), and updating the voxel mesh based on the determining of the surface reaction.
    Type: Application
    Filed: June 4, 2022
    Publication date: December 7, 2023
    Inventors: Nuo Xu, Zhengping Jiang, Ji-Ting Li, Yuan Hao Chang, Zhiqiang Wu, Wen-Hsing Hsieh
  • Publication number: 20230394210
    Abstract: An exemplary method for semiconductor device simulation includes receiving a device structure, generating a mesh for the device structure, simulating electrical behavior of the device structure using the mesh, and adaptively adjusting the mesh during the simulating. The adaptively adjusting the mesh includes performing a multi-level restriction-prolongation (MLRP) process that decreases and increases a resolution of the mesh. The semiconductor device simulation can be performed by a semiconductor simulation system that includes a central processing unit, a memory, and a hardware accelerator. The MLRP process is at least partially parallelized on the hardware accelerator, such as a GPU.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Nuo Xu, Zhengping Jiang, Zhiqiang Wu
  • Publication number: 20230394642
    Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of at least one of the particles with a ray-tracing method, identifying a voxel unit in the voxel mesh that intersects the flight path, determining a surface reaction between the one of the particles and the voxel unit, and adding an extra voxel unit adjacent to the voxel unit based on the determining of the surface reaction.
    Type: Application
    Filed: June 4, 2022
    Publication date: December 7, 2023
    Inventors: Zhengping Jiang, Nuo Xu, Ji-Ting Li, Yuan Hao Chang, Zhiqiang Wu, Wen-Hsing Hsieh