Patents by Inventor Zhiqiang Wu

Zhiqiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220250784
    Abstract: An embodiment of the disclosure provides a tray, including at least one loading chamber, the loading chamber including: a first restriction recess and a second restriction recess located within an edge of a bottom face of the first restriction recess, wherein the first restriction recess is configured to load a touch cover and limit the touch cover, and the second restriction recess is configured to load a liquid crystal module and limit the liquid crystal module. The tray according to the embodiment of the disclosure can satisfy with the carrying requirements of the LCM and the TLCM, so that the carrying cost and the waste of resources can be effectively reduced. An embodiment of the disclosure also provides a loading device of a display product.
    Type: Application
    Filed: September 27, 2021
    Publication date: August 11, 2022
    Inventors: Yanli ZHAO, Xiaoji LI, Hailong WU, Gang CHEN, Pengbing XIE, Zhiqiang LIU, Jiaqin LI
  • Patent number: 11411261
    Abstract: Lithium-based and sodium-based batteries and capacitors using metal foil current collectors, coated with porous layers of particles of active electrode materials for producing an electric current, may adapted to produce heat for enhancing output when the cells are required to periodically operate during low ambient temperatures. A self-heating cell may be placed in heat transfer contact with a working cell that is temporarily in a cold environment. Or one or both of the anode current collector and cathode current collectors of a heating cell may be formed with shaped extended portions, uncoated with electrode materials, through which cell current may be passed for resistance heating of the extended current collector areas. These extended current collector areas may be used to heat the working area of the cell in which they are incorporated, or to contact and heat an adjacent working cell.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 9, 2022
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Zhiqiang Yu, Haijing Liu, Xiaochao Que, Dave G. Rich, Saad Hasan, Meiyuan Wu
  • Patent number: 11407233
    Abstract: The present disclosure discloses a heat transfer printing on-line code printing system. A conveyor belt is arranged on a worktable. A pressing conveyor and a code printer are erected on the worktable. The pressing conveyor includes a mounting frame. An adjustment frame located above the conveyor belt is arranged on the mounting frame. Two roller groups that are arranged opposite to each other are rotatably arranged on the inner side of the adjustment frame. Acting sides of the two roller groups penetrate out from the bottom of the adjustment frame to the position above of the conveyor belt. The two roller groups are in coaxial transmission. The adjustment frame is connected to the mounting frame, and the mounting frame is in threaded connection with an adjustment rod. The inner side of the mounting frame is connected with multiple support components that are elastically pressed against the adjustment frame.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 9, 2022
    Assignee: SICHUAN PETROCHEMICAL YASHI PAPER CO., LTD.
    Inventors: Zhiyong Liao, Bing Xu, Shijun Wu, Qiang Xu, Zhiqiang Li, Jinguo Yang
  • Publication number: 20220245807
    Abstract: The present disclosure provides a method of remotely measuring a size of a pupil, including: acquiring an image of a to-be-measured person by using a detection device; acquiring an image of a pupil of the to-be-measured person from the image of the to-be-measured person; measuring a distance between the to-be-measured person and the detection device by using the detection device; and calculating an actual size of the pupil of the to-be-measured person based on the measured distance and the image of the pupil of the to-be-measured person. The present disclosure further provides an apparatus for remotely measuring a size of a pupil, an electronic device, and a non-transitory computer-readable medium.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 4, 2022
    Applicants: Tsinghua University, Nuctech Company Limited
    Inventors: Zhiqiang CHEN, Yuanjing LI, Jianmin LI, Xianghao WU, Bin LIU, Guocheng AN
  • Patent number: 11397357
    Abstract: A dimming panel and a manufacturing method thereof are provided. The dimming panel includes: a first base substrate and a second base substrate opposite to the first substrate; a first electrode on the first base substrate; a second electrode on the second base substrate; and a liquid crystal layer between the first and second base substrate. The first electrode includes a plurality of first electrode strips arranged at intervals in a first direction and a plurality of second electrode strips arranged at intervals in the first direction, the plurality of first electrode strips are located in a first electrode layer, the plurality of second electrode strips are located in a second electrode layer on a side of the first electrode layer away from the first base substrate. An orthographic projection of a combination of first and second electrode strips on the first base substrate is an integrated plane without gaps.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: July 26, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiaxing Wang, Hongliang Yuan, Xiaojuan Wu, Qi Zheng, Yao Bi, Zhiqiang Zhao, Xuan Zhong, Zhangxiang Cheng, Donghua Zhang, Ce Wang
  • Patent number: 11393926
    Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Publication number: 20220216223
    Abstract: A semiconductor memory structure includes a substrate, two doped regions in the substrate, a plurality of gate layers, a plurality of insulating layers, a column over the substrate, a charge-trapping layer, and a channel layer. The substrate includes dopants of a first conductivity type, and the two doped regions include dopants of a second conductivity type complementary to the first conductivity type. The gate layers and the insulating layers are alternately stacked over the substrate. The column penetrates the gate layers and the insulating layers, and includes an isolation structure, a source structure and a drain structure. at two sides of the isolation structure. The charge-trapping layer is at two sides of the column, and the channel layer is between the charge-trapping layer and the column. A bottom surface of the charge-trapping layer is in contact with the substrate and separated from the two doped regions.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: NUO XU, SAI-HOOI YEONG, YU-MING LIN, ZHIQIANG WU
  • Publication number: 20220216222
    Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Kuo-Cheng Chiang, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Publication number: 20220215869
    Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Gaurav Gupta, Zhiqiang Wu, Yih Wang
  • Patent number: 11378854
    Abstract: The present disclosure provides a sub-pixel structure, a liquid crystal panel and a reflective liquid crystal display device. The sub-pixel structure includes a pixel electrode, and a first thin film transistor and a second thin film transistor integrated on an array substrate; the first thin film transistor and the second thin film transistor are respectively close to a first side and a second side, opposite to each other, of the pixel electrode, and are adjacent to and are connected to two scanning lines in the array substrate, respectively; and a length of a channel region of the first thin film transistor is greater than a first length threshold, and a length of a channel region of the second thin film transistor is greater than a second length threshold.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: July 5, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaojuan Wu, Xuan Zhong, Hongliang Yuan, Qi Zheng, Zhangxiang Cheng, Yao Bi, Zhiqiang Zhao, Jiaxing Wang, Donghua Zhang
  • Patent number: 11380783
    Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Carlos H. Diaz, Chih-Hao Wang, Zhiqiang Wu
  • Patent number: 11374843
    Abstract: A method of measuring a network speed, a computing device, and a computer-program product are provided. The method includes: obtaining a downloading duration and a downloading byte count of each of N consecutive video segments upon receiving a network speed measurement command during downloading video content, wherein the video content comprises multiple video segments; calculating out a total downloading duration and a total downloading byte count of the N video segments according to the downloading duration and the downloading byte count of each of the N video segments; and calculating out a current network speed according to the total downloading duration and the total downloading byte count.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: June 28, 2022
    Assignee: Shanghai Bilibili Technology Co., Ltd.
    Inventors: Hanchao Zheng, Zhiqiang Wu, Hui Chen
  • Publication number: 20220181202
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Yu LIN, Chun-Fu CHENG, Chung-Wei WU, Zhiqiang WU
  • Publication number: 20220165842
    Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: Chih-Ching Wang, Wen-Hsing Hsieh, Jon-Hsu HO, Wen-Yuan Chen, Chia-Ying Su, Chung-Wei WU, Zhiqiang Wu
  • Patent number: 11342016
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first read bias transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first read bias transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gaurav Gupta, Zhiqiang Wu
  • Patent number: 11342422
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes providing a substrate including a channel region for conducting current; shaping the substrate to form a protruding plane, a bottom plane and a side plane connected between the protruding plane and the bottom plane for the channel region; forming an oxide layer covering the channel region; forming a ferroelectric material strip, extending in a first direction, on a protruding plane of the oxide layer; and forming a gate strip, extending in a second direction orthogonal with the first direction, on the ferroelectric material strip and a side plane and a bottom plane of the oxide layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nuo Xu, Zhiqiang Wu
  • Patent number: 11336711
    Abstract: A method of playing audio and video is provided. The method includes: obtaining a streaming media content to be encapsulated, and parsing the streaming media content to obtain audio parameter information and/or video parameter information; forming a Media Presentation Description (MPD) file in JavaScript Object Notation (JSON) format according to the audio parameter information and/or the video parameter information, wherein the MPD file in JSON format includes multiple streaming media content segments, each streaming media content segment includes a video segment and/or an audio segment, each of the video segment and the audio segment includes multiple arrays, and each array includes the audio parameter information or the video parameter information; sending the MPD file in JSON format to a client.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: May 17, 2022
    Assignee: Shanghai Bilibili Technology Co., Ltd.
    Inventors: Sheng Wang, Hanchao Zheng, Zhiqiang Wu, Hui Chen, Jianqiang Ding, Wenjie Fan, Zhaoxin Tan
  • Patent number: 11327961
    Abstract: A system includes reception of a first instruction at a first system to effect a first change to a hierarchy data model, storage of a first record including first values specifying the first change in a local memory of the first system, reception of a second instruction to effect a second change to the hierarchy data model, storage of a second record including second values specifying the second change in the local memory of the first computer system, reception of an instruction to save the changed hierarchy data model, and, in response to the instruction, transmit the first record and the second record to a second system. The first record and the second record are received and merged to generate a third record including third values specifying a third change to the hierarchy data model, and a query language statement is generated to effect the third change to the hierarchy data model based on the third record.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: May 10, 2022
    Assignee: SAP SE
    Inventors: Zhiqiang Wu, Shichang Li
  • Patent number: 11309005
    Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, Zhiqiang Wu, Yih Wang
  • Patent number: 11303949
    Abstract: A method of switching resolution is provided. The method includes: in playing audio and/or video using DASH, acquiring a media presentation description (MPD) file and obtaining resolution information through parsing the MPD file; during the playing of the audio and/or video, periodically determining a currently secure downloading speed according to a preset time interval and determining whether a resolution switching for the audio and/or video currently being played is required according to the secure downloading speed and the resolution information; and in accordance with a determination that the resolution switching is required, determining a switching time point according to an elapsed duration of a currently playing segment and a preset secure buffering duration and performing resolution switching at the switching time point.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: April 12, 2022
    Assignee: Shanghai Bilibili Technology Co., Ltd.
    Inventors: Zhiqiang Wu, Hanchao Zheng, Hui Chen, Jianqiang Ding, Zhaoxin Tan