Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a plurality of ferroelectric layers stacking over the first surface, and a plurality of metal layers stacking over the first surface of the substrate, wherein each of the metal layers is on each of the ferroelectric layers. The operations of the method for manufacturing the semiconductor structure includes providing a substrate having a first surface, and forming a plurality of stack units over the first surface of the substrate The forming of each of the stack units includes the operations of forming a ferroelectric layer and forming a metal layer on the ferroelectric layer.

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

Abstract: A semiconductor device includes a substrate, a plurality of nanowires, a gate structure, a source/drain epitaxy structure, and a semiconductor layer. The substrate has a protrusion portion. The nanowires extend in a first direction above the protrusion portion of the substrate, the nanowires being arranged in a second direction substantially perpendicular to the first direction. The gate structure wraps around each of the nanowires. The source/drain epitaxy structure is in contact with an end surface of each of the nanowires, in which a bottom surface of the source/drain epitaxy structure is lower than a top surface of the protrusion portion of the substrate. The semiconductor layer is in contact with the bottom surface of the epitaxy structure, in which the semiconductor layer is spaced from the protrusion portion of the substrate.

Abstract: A semiconductor device includes a channel region comprising dopants, a gate structure over the channel region and a deactivated region underneath the gate structure and partially within the channel region. Dopants within the deactivated region are deactivated. The deactivated region includes carbon. The deactivated region is physically separated from a top surface of a substrate by a portion of the substrate that is free of carbon.

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first read bias transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first read bias transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.

Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer.

Abstract: A blowing-suction machine includes an engine, a volute, a vent assembly and a vacuum pipe. The engine is installed at an upper end of the volute; the vent assembly is installed at a front end of the volute; an output shaft of the engine in the volute is coupled to a vane; a first shaft of a self-propelled device is coupled to a lower end of the first shaft; both ends of a second shaft of the self-propelled device are coupled to a wheel self-propelled device and a rolling-sweeping-combing device respectively; and the vacuum pipe has an end coupled to the vent assembly and the other end disposed in front of a garbage deposit box. This disclosure features a simple structure and a clever design and provides the self-propelled, automatic sweeping, automatic grass combing, and garbage crushing functions to improve the blowing-suction rate significantly and provide a convenient use.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain trench; laterally etching the first semiconductor layers through the source/drain trench; forming an inner spacer layer, in the source/drain trench, at least on lateral ends of the etched first semiconductor layers; forming a seeding layer on the inner spacer layer; and growing a source/drain epitaxial layer in the source/drain trench, wherein the growing of the source/drain epitaxial layer includes growing the source/drain epitaxial layer from the seeding layer.

Abstract: Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs), and disclosed are the associated devices. An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.

Abstract: An EUV collector mirror for an extreme ultra violet (EUV) radiation source apparatus includes an EUV collector mirror body on which a reflective layer as a reflective surface is disposed, a trajectory correcting device attached to or embedded in the EUV collector mirror body and a trajectory correcting device to adjust the trajectory of metal from the reflective surface of the EUV collector mirror body to an opposite side of the EUV collector mirror body.

Abstract: Provided is a permission-controlled smart contract upgrade method. The method deploys a contract upgrade smart contract, and deploys a smart contract to be upgraded including information of contract participants and a required minimum number of agreements on passing a proposal related to the contract. Any of the blockchain nodes receives a contract upgrade proposal submitted by user to the smart contract, the proposal carrying address of the contract to be upgraded and binary information of a new contract. After the smart contract determines to pass the proposal, a proposing event is generated and forwarded to each user client participating in the contract. After the client receives the event, the client receives user's vote and feeds back to the smart contract. If the number of agreements exceeds the required minimum number, the proposal is passed and employed, and a binary replacement is performed to complete upgrade of the smart contract.

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.