Patents by Inventor Zhiyuan Wu
Zhiyuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250132165Abstract: Methods of removing molybdenum oxide from a surface of a substrate comprise exposing the substrate having a molybdenum oxide layer on the substrate to a halide etchant having the formula RmSiX4-m, wherein m is an integer from 1 to 3, X is selected from iodine (I) and bromine (Br) and R is selected from the group consisting of a methyl group, ethyl group, propyl group, butyl group, cyclohexyl group and cyclopentyl group. The methods may be performed in a back-end-of-the line (BEOL) process, and the substrate contains a low-k dielectric material.Type: ApplicationFiled: October 20, 2023Publication date: April 24, 2025Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Feng Q. Liu, Zheng Ju, Zhiyuan Wu, Kevin Kashefi, Mark Saly, Xianmin Tang
-
Publication number: 20250112090Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.Type: ApplicationFiled: December 12, 2024Publication date: April 3, 2025Applicant: Applied Materials, Inc.Inventors: Ge Qu, Zhiyuan Wu, Feng Chen, Carmen Leal Cervantes, Yong Jin Kim, Kevin Kashefi, Xianmin Tang, Wenjing Xu, Lu Chen, Tae Hong Ha
-
Publication number: 20250062160Abstract: A method of forming a metal interconnect in a semiconductor structure includes performing a barrier layer deposition process to deposit a barrier layer within an opening formed through a dielectric layer, performing a liner deposition process to deposit a liner layer on the barrier layer, performing a metal treatment process to implant metal dopants into a surface of the liner layer, and performing a gap fill process to form a metal interconnect on the metal treated surface of the liner layer within the opening.Type: ApplicationFiled: June 20, 2024Publication date: February 20, 2025Inventors: Ge QU, Zhiyuan WU, Jiajie CEN, Feng CHEN, Kevin KASHEFI, Chengyu LIU
-
Patent number: 12211743Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.Type: GrantFiled: September 3, 2021Date of Patent: January 28, 2025Assignee: Applied Materials, Inc.Inventors: Ge Qu, Zhiyuan Wu, Feng Chen, Carmen Leal Cervantes, Yong Jin Kim, Kevin Kashefi, Xianmin Tang, Wenjing Xu, Lu Chen, Tae Hong Ha
-
Publication number: 20250009913Abstract: Compounds comprising a tetrapyrrole macrocycle that includes a radionuclide; a hydrogelator attached to the tetrapyrrole macrocycle; a water solubilizing group attached to the hydrogelator; and a cleavage site that is between the hydrogelator and the water solubilizing group are described herein along with their methods of use. Two or more compounds of the present invention may two or more compounds may self-assemble (e.g., aggregate), optionally in vivo.Type: ApplicationFiled: June 26, 2024Publication date: January 9, 2025Inventors: Qihui Liu, Zhiyuan Wu, Jonathan S. Lindsey
-
Publication number: 20240419659Abstract: A method and system are provided for processing natural language user queries for commanding a user interface to perform functions. Individual user queries are classified in accordance with the types of functions and a plurality of user queries may be related to define a particular command. To assist with classification, a query type for each user query is determined where the query type is one of a functional query requesting a particular new command to perform a particular type of function, an entity query relating to an entity associated with the particular new command having the particular type of function and a clarification query responding to a clarification question posed to clarify a prior user query having the particular type of function. Functional queries may be processed using a plurality of natural language processing techniques and scores from each technique combined to determine which type of function is commanded.Type: ApplicationFiled: August 26, 2024Publication date: December 19, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Kaheer SULEMAN, Joshua R. PANTONY, Wilson HSU, Zhiyuan WU, Phil TREGENZA, Sam PASUPALAK
-
Publication number: 20240420997Abstract: Methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. A metal liner is selectively deposited on the barrier layer on the sidewall over the passivation layer on the bottom.Type: ApplicationFiled: June 19, 2023Publication date: December 19, 2024Applicant: Applied Materials, Inc.Inventors: Yang Zhou, Jiajie Cen, Zhiyuan Wu, Ge Qu, Yong Jin Kim, Zheng Ju, Feng Chen, Kevin Kashefi
-
Publication number: 20240420996Abstract: Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.Type: ApplicationFiled: June 13, 2023Publication date: December 19, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Zhiyuan Wu, Kevin Kashefi, Yong Jin Kim, Yang Zhou, Zheng Ju
-
Publication number: 20240420966Abstract: Embodiments of the disclosure relate to methods of etching a copper material. In some embodiments, the copper material is exposed to a halide reactant to form a copper halide species. The substrate is then heated to remove the copper halide species. In some embodiments, the etching methods are performed at relatively low temperatures. Additional embodiments of the disclosure relate to methods of copper gapfill. In some embodiments, a copper material within a substrate feature is exposed to a halide reactant to form a copper halide species. The copper halide species is then heated and flowed to fill at least a portion of the substrate feature. The reflow methods are performed at lower temperatures than similar reflow methods without formation of the copper halide species.Type: ApplicationFiled: June 16, 2023Publication date: December 19, 2024Applicant: Applied Materials, Inc.Inventors: Zhiyuan Wu, Zheng Ju, Feng Chen, Kevin Kashefi, Feng Q. Liu, Jeffrey W. Anthis
-
Publication number: 20240404803Abstract: Embodiments of the present disclosure generally relate to a low temperature non-plasma containing preclean process to selectively remove contaminants from the surface of a substrate, such as halogen containing and/or metal oxide containing contaminants. The non-plasma containing precleaning process is performed at a low temperature by use of a microwave source that is configured to provide microwave energy to the processing gases disposed within a processing chamber. The non-plasma low temperature preclean process is effective in reducing halogen containing residues, such as fluorine and chlorine containing residues formed on a surface of a substrate.Type: ApplicationFiled: April 26, 2024Publication date: December 5, 2024Inventors: Yoon Ah SHIN, Jiajie CEN, Zhiyuan WU, Bencherki MEBARKI, Kevin KASHEFI, Joung Joo LEE, Xianmin TANG
-
Publication number: 20240339358Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM has a general formula I to XIX, wherein R, R?, R1, R2, R3, R4, and R5 are independently selected from hydrogen (H), alkyl, alkene, alkyne, and aryl, n is from 1 to 20, m is from 1 to 20, x is from 1 to 2, and y is from 1 to 2. A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.Type: ApplicationFiled: April 7, 2023Publication date: October 10, 2024Applicant: Applied Materials, Inc.Inventors: Jesus Candelario Mendoza-Gutierrez, Aaron Dangerfield, Bhaskar Jyoti Bhuyan, Mark Saly, Yang Zhou, Yong Jin Kim, Carmen Leal Cervantes, Ge Qu, Zhiyuan Wu, Feng Chen, Kevin Kashefi
-
Publication number: 20240332075Abstract: Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the microelectronic device with a plasma to remove a first portion of the second self-assembled monolayer (SAM); selectively depositing a metal liner on the barrier layer on the sidewall; removing a second portion of the second self-assembled monolayer (SAM); and performing a gap fill process on the metal liner.Type: ApplicationFiled: March 22, 2024Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Kevin Kashefi, Zhiyuan Wu, Yang Zhou, Yong Jin Kim, Carmen Leal Cervantes, Ge Qu, Zheng Ju
-
Publication number: 20240321633Abstract: Methods for depositing ultra-thin films are disclosed. Some embodiments of the disclosure utilize ultra-thin films as barrier layers, liner layers, or nucleation layers to decrease interconnect resistance. Some embodiments advantageously provide continuous films with thicknesses of less than or equal to about 20 ?. Some embodiments advantageously provide films with decreased roughness.Type: ApplicationFiled: March 17, 2023Publication date: September 26, 2024Applicant: Applied Materials, Inc.Inventors: Zhiyuan Wu, Zheng Ju, Feng Chen
-
Patent number: 12093804Abstract: The present disclosure provides a satellite anomaly detection method and system for an adversarial network auto-encoder. The method includes: obtaining a variational auto-encoder and a generative adversarial network; adding the generative adversarial network to the variational auto-encoder, and determining an optimized variational auto-encoder; obtaining to-be-detected satellite telemetry data; and determining a current operating status of a satellite based on the to-be-detected satellite telemetry data by using the optimized variational auto-encoder, where the current operating status includes a normal operating state or an abnormal operating state. The satellite anomaly detection method and system for an adversarial network according to the present disclosure solve the low accuracy problem of automatic satellite anomaly detection in the prior art.Type: GrantFiled: February 18, 2020Date of Patent: September 17, 2024Assignee: NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICSInventors: Dechang Pi, Junfu Chen, Zhiyuan Wu
-
Publication number: 20240290655Abstract: A method of selectively filling a via with a simultaneous liner deposition in a semiconductor structure includes forming a passivation layer selectively on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer, selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench, and filling the remaining of the via and the trench with a second conductive material.Type: ApplicationFiled: February 28, 2023Publication date: August 29, 2024Inventors: Zheng JU, Zhiyuan WU, Jiajie CEN, Feng Q. LIU, Feng CHEN
-
Patent number: 12072877Abstract: A method and system are provided for processing natural language user queries for commanding a user interface to perform functions. Individual user queries are classified in accordance with the types of functions and a plurality of user queries may be related to define a particular command. To assist with classification, a query type for each user query is determined where the query type is one of a functional query requesting a particular new command to perform a particular type of function, an entity query relating to an entity associated with the particular new command having the particular type of function and a clarification query responding to a clarification question posed to clarify a prior user query having the particular type of function. Functional queries may be processed using a plurality of natural language processing techniques and scores from each technique combined to determine which type of function is commanded.Type: GrantFiled: May 13, 2019Date of Patent: August 27, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Kaheer Suleman, Joshua R. Pantony, Wilson Hsu, Zhiyuan Wu, Phil Tregenza, Sam Pasupalak
-
Publication number: 20240258103Abstract: Embodiments of the disclosure relate to methods for forming electrical interconnects. Additional embodiments provide methods of forming and treating barrier and liner layers to improve film and material properties. In some embodiments, the resulting composite layers provide improved resistivity, decrease void formation and improve device reliability.Type: ApplicationFiled: January 25, 2024Publication date: August 1, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Ge Qu, Shinjae Hwang, Zheng Ju, Yang Zhou, Zhiyuan Wu, Feng Chen, Kevin Kashefi
-
Publication number: 20240194605Abstract: A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 ? and 40 ?.Type: ApplicationFiled: December 8, 2023Publication date: June 13, 2024Inventors: Mohammad Mahdi TAVAKOLI, Avgerinos V. GELATOS, Jiajie CEN, Kevin KASHEFI, Joung Joo LEE, Zhihui LIU, Yang ZHOU, Zhiyuan WU, Meng-Shan WU
-
Publication number: 20240186181Abstract: Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.Type: ApplicationFiled: December 2, 2022Publication date: June 6, 2024Inventors: Ge QU, Qihao ZHU, Zheng JU, Yang ZHOU, Jiajie CEN, Feng Q. LIU, Zhiyuan WU, Feng CHEN, Kevin KASHEFI, Xianmin TANG, Jeffrey W. ANTHIS, Mark Joseph SALY
-
Patent number: 11990368Abstract: Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.Type: GrantFiled: June 23, 2022Date of Patent: May 21, 2024Assignee: Applied Materials, Inc.Inventors: Mehul B. Naik, Zhiyuan Wu