Patents by Inventor Zhongze Wang

Zhongze Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190156895
    Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventors: Xia LI, Xiao LU, Xiaonan CHEN, Zhongze WANG
  • Patent number: 10290352
    Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Xiao Lu, Xiaonan Chen, Zhongze Wang
  • Publication number: 20190035796
    Abstract: An apparatus includes first means for routing current coupled to a bit cell. The apparatus includes third means for routing current. The third means for routing current includes a write word line coupled to the bit cell. The apparatus includes second means for routing current. The second means for routing current is between the first means for routing current and the third means for routing current. The second means for routing current includes two read word lines coupled to the bit cell.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 10194529
    Abstract: A partial metal fill is provided within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Guoqing Chen
  • Patent number: 10141317
    Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 10037795
    Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: July 31, 2018
    Assignees: QUALCOMM Incorporated, INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 9941154
    Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 10, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, John Jianhong Zhu
  • Publication number: 20180082776
    Abstract: A partial metal fill is provided within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Zhongze Wang, Guoqing Chen
  • Patent number: 9876017
    Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: January 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Kern Rim, Choh Fei Yeap
  • Patent number: 9876123
    Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Jeffrey Junhao Xu, Xiao Lu, Bin Yang, Jun Yuan, Xiaonan Chen, Zhongze Wang
  • Patent number: 9875788
    Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: January 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
  • Patent number: 9865330
    Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: January 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Mingu Kang, Hyunkook Park, Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han, Lixin Ge, Zhongze Wang
  • Patent number: 9842802
    Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, John Jianhong Zhu, Xia Li
  • Patent number: 9812188
    Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: November 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Zhongze Wang, Xiaonan Chen, Stanley Seungchul Song, Choh Fei Yeap
  • Patent number: 9806083
    Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Kern Rim, Choh Fei Yeap
  • Patent number: 9786356
    Abstract: A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a supply voltage. For example, a first target voltage level for a first operating frequency of the multiple operating frequencies is determined. The method includes accessing first data from the memory device while the memory device is operating at the first operating frequency and is powered by the supply voltage having a first voltage level. The method includes determining a first number of errors associated with the first data. The method further includes, in response to the first number of errors satisfying a threshold, adjusting the supply voltage to a second voltage level that is greater than the first voltage level.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Niladri Narayan Mojumder, Jonathan Liu, Choh Fei Yeap
  • Patent number: 9773567
    Abstract: A method and apparatus for balancing voltage stress at a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory array is disclosed. A particular cell of the SONOS flash memory array is selected for programming. A first voltage stress associated with a first SONOS transistor is determined if the particular cell is programmed. The first SONOS transistor is included in a first unselected cell of the SONOS flash memory array. A second voltage stress associated with a second SONOS transistor is determined if the particular cell is programmed. The first voltage stress and the second voltage stress are balanced prior to programming the particular cell.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: September 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Guoqing Chen, Paul Hoayun
  • Patent number: 9691868
    Abstract: Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 9666481
    Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 30, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, Niladri Mojumder, Mustafa Badaroglu
  • Publication number: 20170110364
    Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 20, 2017
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, John Jianhong Zhu