Patents by Inventor Zhongze Wang

Zhongze Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170062439
    Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.
    Type: Application
    Filed: November 9, 2016
    Publication date: March 2, 2017
    Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 9576801
    Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Jeffrey Junhao Xu, Zhongze Wang, Bin Yang, Xiaonan Chen, Yu Lu
  • Patent number: 9564361
    Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: February 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, John Jianhong Zhu
  • Patent number: 9536596
    Abstract: An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm).
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: January 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 9524972
    Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: December 20, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 9508589
    Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 29, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Kern Rim, Zhongze Wang, Jeffrey Junhao Xu, Xiangdong Chen, Choh Fei Yeap
  • Patent number: 9508439
    Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 29, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Jeffrey Junhao Xu, Xiao Lu, Matthew Michael Nowak, Seung Hyuk Kang, Xiaonan Chen, Zhongze Wang, Yu Lu
  • Patent number: 9502424
    Abstract: One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 22, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, John Jianhong Zhu, Xia Li
  • Patent number: 9495503
    Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Herbert Fischer, Manish Garg, Zhongze Wang
  • Patent number: 9496048
    Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaonan Chen, Zhongze Wang, Xia Li
  • Publication number: 20160322391
    Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 3, 2016
    Inventors: Stanley Seungchul SONG, Zhongze WANG, Choh Fei YEAP
  • Patent number: 9478490
    Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 25, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: John Jianhong Zhu, Stanley Seungchul Song, Kern Rim, Zhongze Wang, Jeffrey Junhao Xu
  • Patent number: 9460777
    Abstract: A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: October 4, 2016
    Assignees: Qualcomm Incorporated, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Zhongze Wang, Choh fei Yeap
  • Patent number: 9461055
    Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: October 4, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xia Li, Zhongze Wang, Daniel Wayne Perry
  • Patent number: 9455026
    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 27, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Ping Liu, Kern Rim, Choh Fei Yeap
  • Patent number: 9449709
    Abstract: A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 20, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xia Li, Xiaonan Chen, Niladri Narayan Mojumder, Zhongze Wang, Weidan Li
  • Publication number: 20160268002
    Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 15, 2016
    Inventors: Xiaonan CHEN, Zhongze WANG, Xia LI
  • Publication number: 20160254056
    Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: Xia LI, Xiao LU, Xiaonan CHEN, Zhongze WANG
  • Patent number: 9431097
    Abstract: A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaonan Chen, Zhongze Wang, Xia Li
  • Publication number: 20160247554
    Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.
    Type: Application
    Filed: February 25, 2015
    Publication date: August 25, 2016
    Inventors: Niladri Narayan Mojumder, Zhongze Wang, Xiaonan Chen, Stanley Seungchul Song, Choh Fei Yeap