Patents by Inventor Zhongze Wang

Zhongze Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METAL-GATE WITH AN AMORPHOUS METAL LAYER
    Publication number: 20160086805
    Abstract: A particular semiconductor device includes a substrate, a source contact, a drain contact, and a metal-gate. The substrate includes a source region, a drain region, and a channel. The source contact is coupled to the source region. The drain contact is coupled to the drain region. The metal-gate is coupled to the channel. The metal-gate includes an amorphous metal layer.
    Type: Application
    Filed: February 19, 2015
    Publication date: March 24, 2016
    Inventors: Jeffrey Junhao Xu, Zhongze Wang, Kern Rim, Stanley Seungchul Song, Choh Fei Yeap
  • CAPACITOR FROM SECOND LEVEL MIDDLE-OF-LINE LAYER IN COMBINATION WITH DECOUPLING CAPACITORS
    Publication number: 20160071795
    Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 10, 2016
    Inventors: John Jianhong ZHU, Stanley Seungchul SONG, Kern RIM, Zhongze WANG, Jeffrey Junhao XU
  • SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE
    Publication number: 20160064068
    Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Niladri Mojumder, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • THREE-PORT BIT CELL HAVING INCREASED WIDTH
    Publication number: 20160064067
    Abstract: An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm).
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features
    Patent number: 9263279
    Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: February 16, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: John J. Zhu, Zhongze Wang, Da Yang
  • FIN FIELD-EFFECT TRANSISTOR STATIC RANDOM ACCESS MEMORY DEVICES WITH P-CHANNEL METAL-OXIDE-SEMICONDUCTOR PASS GATE TRANSISTORS
    Publication number: 20160043092
    Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 11, 2016
    Inventors: Niladri Narayan MOJUMDER, Stanley Seungchul SONG, Zhongze WANG, Choh Fei YEAP
  • Heterogeneous channel material integration into wafer
    Patent number: 9257407
    Abstract: Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 9, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, Niladri Narayan Mojumder
  • NON-VOLATILE ONE-TIME PROGRAMMABLE MEMORY DEVICE
    Publication number: 20160020220
    Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 21, 2016
    Inventors: Xia Li, Jeffrey Junhao Xu, Xiao Lu, Bin Yang, Jun Yuan, Xiaonan Chen, Zhongze Wang
  • NON-VOLATILE MULTIPLE TIME PROGRAMMABLE MEMORY DEVICE
    Publication number: 20160012896
    Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.
    Type: Application
    Filed: January 21, 2015
    Publication date: January 14, 2016
    Inventors: Xia Li, Jeffrey Junhao Xu, Xiao Lu, Matthew Michael Nowak, Seung Hyuk Kang, Xiaonan Chen, Zhongze Wang, Yu Lu
  • SELF-ALIGNED VIA FOR GATE CONTACT OF SEMICONDUCTOR DEVICES
    Publication number: 20160005822
    Abstract: Systems and methods are directed to a three-terminal semiconductor device including a self-aligned via for connecting to a gate terminal Hardmasks and spacers formed over top portions and sidewall portions of a drain connection to a drain terminal and a source connection to a source terminal protect and insulate the drain connection and the source connection, such that short circuits are avoided between the source and drain connections and the self-aligned via. The self-aligned via provides a direct metal-gate connection path between the gate terminal and a metal line such as a M1 metal line while avoiding a separate gate connection layer.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: Stanley Seungchul SONG, Choh Fei YEAP, Kern RIM, Zhongze WANG
  • DUAL WRITE WORDLINE MEMORY CELL
    Publication number: 20150380080
    Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang
  • Via material selection and processing
    Patent number: 9196583
    Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: November 24, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventors: John Jianhong Zhu, Jeffrey Junhao Xu, Stanley Seungchul Song, Kern Rim, Zhongze Wang
  • ADVANCED METAL-NITRIDE-OXIDE-SILICON MULTIPLE-TIME PROGRAMMABLE MEMORY
    Publication number: 20150333072
    Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 19, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Xia LI, Zhongze WANG, Daniel Wayne PERRY
  • HIGH DENSITY STATIC RANDOM ACCESS MEMORY ARRAY HAVING ADVANCED METAL PATTERNING
    Publication number: 20150333131
    Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 19, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Niladri MOJUMDER, Stanley Seungchul SONG, Zhongze WANG, Choh Fei YEAP
  • HIGH DENSITY SRAM ARRAY DESIGN WITH SKIPPED, INTER-LAYER CONDUCTIVE CONTACTS
    Publication number: 20150325514
    Abstract: A static random access memory (SRAM) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer. The SRAM cell also includes a second via coupling the wordline landing pad and the wordline of the second conductive layer.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Niladri Narayan MOJUMDER, Zhongze WANG, Stanley Seungchul SONG, Choh Fei YEAP
  • VIA MATERIAL SELECTION AND PROCESSING
    Publication number: 20150325515
    Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: John Jianhong ZHU, Jeffrey Junhao XU, Stanley Seungchul SONG, Kern RIM, Zhongze WANG
  • DATA PATH SYSTEM ON CHIP DESIGN METHODOLOGY
    Publication number: 20150317426
    Abstract: Integrated circuit (IC) technology design may include binning data paths of an IC device of a current technology node to bins based on a performance of each of the data paths. Each of the plurality of bins is mapped to a representative circuit unit data path configured according to a predetermined set of electrical and/or physical parameters. The representative circuit unit data paths are calibrated according to updated electrical and/or physical parameters to increase the performance of the representative circuit unit data paths to improve the performance of the IC device in an advanced technology node.
    Type: Application
    Filed: September 26, 2014
    Publication date: November 5, 2015
    Inventors: Stanley Seungchul SONG, Niladri Narayan MOJUMDER, Zhongze WANG, Choh Fei YEAP
  • REDUCED HEIGHT M1 METAL LINES FOR LOCAL ON-CHIP ROUTING
    Publication number: 20150262930
    Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Stanley Seungchul SONG, Choh Fei YEAP, Zhongze WANG, Niladri MOJUMDER, Mustafa BADAROGLU
  • SYSTEM AND METHOD FOR MODIFICATION OF CODED INSTRUCTIONS IN READ-ONLY MEMORY USING ONE-TIME PROGRAMMABLE MEMORY
    Publication number: 20150242213
    Abstract: Various embodiments of methods and systems for flexible read only memory (“ROM”) storage of coded instructions in a portable computing device (“PCD”) are disclosed. Because certain instructions and/or data associated with a primary boot loader (“PBL”) may be defective or in need of modification after manufacture of a mask ROM component, embodiments of flexible ROM storage (“FRS”) systems and methods use a closely coupled one-time programmable (“OTP”) memory component to store modified instructions and/or data. Advantageously, because the OTP memory component may be manufactured “blank” and programmed at a later time, modifications to code and/or data stored in an unchangeable mask ROM may be accomplished via pointers in fuses of a security controller that branch the request to the OTP and bypass the mask ROM.
    Type: Application
    Filed: February 23, 2014
    Publication date: August 27, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: YANRU LI, DEXTER TAMIO CHUN, DHAMIM PACKER ALI, GREGORY AMERIADA UVIEGHARA, ZHONGZE WANG
  • GROUNDING DUMMY GATE IN SCALED LAYOUT DESIGN
    Publication number: 20150235948
    Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.
    Type: Application
    Filed: May 9, 2014
    Publication date: August 20, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Stanley Seungchul SONG, Zhongze WANG, Ohsang KWON, Kern RIM, John Jianhong ZHU, Xiangdong CHEN, Foua VANG, Raymond George STEPHANY, Choh Fei YEAP