Abstract: A wheeled carrying apparatus includes a frame structure including a standing frame, a wheel mount carrying a wheel and pivotally connected with the standing frame, the wheel being rotatable relative to the first wheel mount about a wheel axis, a locking assembly including a wheel mount latch movably connected with the standing frame, the wheel mount latch being engaged with the wheel mount to rotationally lock the first wheel mount with respect to the standing frame, and disengaged from the wheel mount to unlock the wheel mount for rotation of the wheel mount to change an orientation of the wheel axis, an actuating assembly coupled to the wheel mount latch and including one or more linking part, and a release mechanism including an operating part provided on the frame structure that is operable to cause the actuating assembly to pull the wheel mount latch to disengage from the wheel mount.

Abstract: An electrical connector includes at least one electrical module. The electrical module includes: an insulating body, where multiple first accommodating slots are concavely provided on a first side toward a second side of the insulating body; multiple first terminal assemblies, respectively accommodated in the corresponding first accommodating slots; and a first grounding member, having multiple first spokes and multiple second spokes. Each first terminal assembly includes a first insulating block, a pair of first signal terminals, and a first shielding shell. Each first shielding shell has a first shielding side surface exposed to the first side. Each first spoke is in mechanical contact with the first shielding shells of a same electrical module, and each second spoke is in contact with the first shielding side surface of the corresponding first shielding shell, thus achieving conduction between the first shielding shells and the first grounding member.

Abstract: Certain aspects of the present disclosure provide techniques for reporting an indication of a PHR when the UE's assigned of UL resources is insufficient to transmit both UL data and a PHR. Additionally, aspects described herein introduce a negative PHR used to indicate the UE requires additional UL resources.

Abstract: A linker peptide for constructing a fusion protein. The linker peptide comprises a flexible peptide and a rigid peptide. The flexible peptide consists of one or more flexible units. The rigid peptide consists of one or more rigid units. The flexible unit comprises two or more amino acid residues selected from Gly, Ser, Ala, and Thr. The rigid unit comprises a human chorionic gonadotropin ?-subunit carboxy-terminal peptide (CTP) bearing a plurality of glycosylation sites. The linker peptide can more effectively eliminate mutual steric hindrance of two fusion molecules, decreasing a reduction/loss of polymerization or activity resulting from improper folding of an active protein or a conformational change. On the other hand, the negatively charged, highly sialylated CTP can resist renal clearance, further prolonging a half-life of a fused molecule and enhancing bioavailability of a fused protein.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.

Abstract: Video processing methods, systems and appratrus are described. One example method includes performing a conversion between a video block of a video and a bitstream of the video using a palette mode in which samples of the video block are represented using a palette of representive color values. A size of the palette of the video block is determined based on whether a local dual tree is applied for the conversion.

Abstract: A method for implementing an adaptive colour transform (ACT) mode during image/video encoding and decoding includes performing a conversion between a current video block of a video and a bitstream of the video, wherein the current video block is coded using the ACT mode, wherein the conversion comprises applying an inverse ACT transform on the current video block according to a rule, and wherein the rule specifies that a clipping operation, based on a bit depth of the current video block, is applied to an input of the inverse ACT transform.

Abstract: Methods and apparatus for video processing are disclosed. The processing may include video encoding, video decoding, or video transcoding. One example method includes performing a conversion between a current block of a video and a bitstream of the video. The bitstream conforms to a rule that specifies that a context index offset is used for including a first sign flag of a first coefficient in the bitstream. The rule specifies that a value of the context index offset is based on whether a first coding mode is applied on the current block in the bitstream.

Abstract: Apparatuses, systems, and methods for providing maximum transmit power control when utilizing multiple radio access technologies. For example, a wireless communication device comprising two cellular radios may intend to transmit on the first radio, while concurrently transmitting on the second radio. To ensure compliance with a maximum transmit power limitation, the device may determine an allowed transmit power level of the first radio, representing a difference between the maximum transmit power limitation and the current transmit power level being transmitted by the second radio. The device may also determine a threshold power level for a communication by the first radio. If the allowed transmit power level meets the threshold power level, then the device may transmit the first communication having a power level between the threshold power level and the allowed transmit power level. Otherwise, the device may forego transmission of the first communication.

Abstract: An example method includes receiving, at a module management unit (MMU) associated with a battery cell, a battery cell parameter measurement associated with the battery cell. The MMU in is communication with a battery radio frequency module via a first link. The method further includes performing, by the MMU, a first function based at least in part on the battery cell parameter measurement to generate a first signal, and transmitting, from the MMU, the first signal to the battery radio frequency module via the first link. The method further includes performing, by the battery radio frequency module, a second function based at least in part on the first signal to generate a second signal. The method further includes transmitting, from the battery radio frequency module, the second signal to a controller, and performing, by the controller, a third function based at least in part on the second signal.

Abstract: A method of video processing, including performing a conversion between a video unit of a video and a bitstream of the video according to a rule, wherein the rule specifies that whether a cross-component adaptive loop filter (CC-ALF) mode and an adaptive loop filter (ALF) mode are enabled for coding the video unit are indicated in the bitstream in a mutually independent manner.

Abstract: Video processing methods, systems and apparatus are described. One example method includes performing a conversion between a video block of a video and a bitstream of the video using a palette mode in which samples of the video block are represented using a palette of representative color values. A size of the palette of the video block is determined based on whether a local dual tree is applied for the conversion.

Abstract: A display panel, including: a substrate base plate; touch electrodes; touch lead wires on the substrate base plate, one end of the touch lead wire is coupled with the touch electrode, the other end thereof is in a peripheral area, the touch lead wires in the display panel are divided into touch lead wire sets, each touch lead wire set includes touch lead wires; data lead wires on the substrate base plate in the peripheral area, the data lead wires are divided into data lead wire sets, each data lead wire set includes data lead wires, the touch lead wire sets and the data lead wire sets are distributed in a staggered manner; at least one shielding line on the substrate base plate in the peripheral area, an orthographic projection of the shielding line is between orthographic projections of the touch lead wire and the data lead wire.

Abstract: A display substrate, a display panel and a display apparatus are provided. The display substrate includes a base substrate, a first display region, and a second display region, and a light transmittance of the first display region is greater than that of the second display region A plurality of sub-pixels are arranged on the base substrate and in the first display region, wherein the sub-pixels include a first pixel driving circuit and a first light-emitting device, and the first pixel driving circuit includes a compensation transistor, a switching transistor, and a light-emitting device initialization transistor each having an active layer. A scan signal line is provided in the first display region. An orthographic projection of the scan signal line on the base substrate overlaps with that of the active layer of each of the compensation transistor, the switching transistor and the light-emitting device initialization transistor on the base substrate.

Abstract: A display substrate includes first and second display regions, and a base substrate. A plurality of sub-pixels are arranged on a side of the base substrate, where the-sub-pixels include a first pixel driving circuit and a first light-emitting device connected to each other in the first display region, and the first pixel driving circuit includes at least a compensation transistor, a switching transistor, and a light-emitting device initialization transistor each having an active layer. A scan signal line is provided in the first display region. An orthographic projection of the scan signal line on the base substrate overlaps with that of the active layer of each of the compensation transistor and the light-emitting device initialization transistor, or that of the active layer of each of the switching transistor and the light-emitting device initialization transistor on the base substrate.

Abstract: A display panel, a driving method and a display apparatus are disclosed. The display panel includes: a substrate, an active semiconductor layer, a gate insulating layer, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a first interlayer insulating layer, a third conductive layer including a plurality of first signal lines, a second interlayer insulating layer, a fourth conductive layer including a plurality of second signal lines stacked in that order. Orthographic projections of the first signal lines on the substrate and orthographic projections of the second signal lines on the substrate are arranged in an intersecting manner.

Abstract: A shift register, comprising an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to transmit a first voltage signal from a first voltage signal terminal to a first node under the control of an input signal from a signal input terminal. The first control circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a second node under the control of a first clock signal from a first clock signal terminal and the voltage of the first node. The second control circuit is configured to transmit a second clock signal from a second clock signal terminal to a third node under the control of the voltage of the second node. The output circuit is configured to transmit the first voltage signal from the first voltage signal terminal to a scan signal output terminal under the control of the voltage of the third node.

Abstract: Provided is a tetanus toxin protein variant, the tetanus toxin protein variant comprising a C fragment of the tetanus toxin protein and a partial fragment of a translocation region of the tetanus toxin protein. Further provided is a proteoglycan conjugate, the proteoglycan conjugate comprising a polysaccharide from Streptococcus pneumoniae and a truncated tetanus toxin protein. Also provided is a method for improving immunogenicity, the method comprising the following steps: providing a proteoglycan conjugate comprising a polysaccharide from Streptococcus pneumoniae and a truncated tetanus toxin protein.

Abstract: A linker peptide for constructing a fusion protein. The linker peptide comprises a flexible peptide and a rigid peptide. The flexible peptide consists of one or more flexible units. The rigid peptide consists of one or more rigid units. The flexible unit comprises two or more amino acid residues selected from Gly, Ser, Ala, and Thr. The rigid unit comprises a human chorionic gonadotropin ?-subunit carboxy-terminal peptide (CTP) bearing a plurality of glycosylation sites. The linker peptide can more effectively eliminate mutual steric hindrance of two fusion molecules, decreasing a reduction/loss of polymerization or activity resulting from improper folding of an active protein or a conformational change. On the other hand, the negatively charged, highly sialylated CTP can resist renal clearance, further prolonging a half-life of a fused molecule and enhancing bioavailability of a fused protein.

Abstract: Provided is a shift register. The shift register comprising: an input circuit, an intermediate circuit and an output circuit; the input circuit is connected to a first power supply terminal, a second power supply terminal, an input voltage terminal and a first clock signal terminal, and the input circuit is configured to output an intermediate input signal to the intermediate circuit; the intermediate circuit is connected to the first power supply terminal, the second power supply terminal and a second clock signal terminal, and the intermediate circuit is configured to output a first node signal to the output circuit; and the output circuit is connected to the first power supply terminal, the second power supply terminal, a first output terminal and a second output terminal, and the output circuit is configured to output a first output signal and a second output signal.