Abstract: A shift register includes a first input sub-circuit being configured to transmit an input signal to a first node under control of a first clock signal; a second input sub-circuit being configured to transmit a first voltage signal to a second node under control of the first clock signal; a first control sub-circuit being configured to transmit a second clock signal to a third node under control of a voltage at the second node; a second control sub-circuit being configured to transmit the first voltage signal to a fourth node under control of a third clock signal; a noise reduction sub-circuit being configured to transmit the first voltage signal to a signal output terminal under control of a voltage at the fourth node; and an output sub-circuit being configured to transmit a second voltage signal to the signal output terminal under control of a voltage at the third node.

Abstract: A pixel circuit includes a light-emitting element, a driving circuit, a compensation control circuit, a data writing-in circuit, a first reset circuit, a light-emitting control circuit and an energy storage circuit; the compensation control circuit controls to connect the control end and the first end of the driving circuit; the data writing-in circuit writes a data voltage into the second end of the driving circuit; the first reset circuit writes a reference voltage into the control end of the driving circuit under the control of a reset control signal; the energy storage circuit is electrically connected to the control end of the driving circuit and the first electrode of the light-emitting element, and is configured to store electrical energy; the driving circuit controls to connect the first end and the second end of the driving circuit under the control of the control end thereof.

Abstract: The invention relates to a pixel circuit, a driving method thereof, a display substrate and a display apparatus. The pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a light emitting control sub-circuit and a drive sub-circuit. The first node control sub-circuit is configured to supply a signal of the initial signal terminal to the first node and the fourth node under the control of the first reset signal terminal and the second scan signal terminal, and supply a signal of the second node to the first node under the control of the third scan signal terminal. The second node control sub-circuit is configured to supply a signal of the reference signal terminal to the second node and a signal of the data signal terminal to the third node under the control of the second reset signal terminal and the first scan signal terminal.

Abstract: Provided are a display panel, a fabricating method thereof, and a display device. The method includes: forming and patterning a first source-drain material film layer, forming a first source-drain layer in a display region, forming at least one isolation pillar transition pattern in a via-hole encapsulation region; etching a second metal layer to form a recessed part; forming an anode material film layer on the first source-drain layer; forming a first pad located on the protective layer and a second pad located around the isolation pillar; forming a photoresist material film layer on the anode material film layer, exposing the photoresist material film layer to form a patterned photoresist layer in the display region, and completely retaining the photoresist material film layer in the via-hole encapsulation region; etching the anode material film layer to form an anode layer; and stripping off the photoresist material film layer.

Abstract: A display substrate includes a drive structure layer disposed on a base substrate. The drive structure layer includes multiple circuit units, multiple data signal lines, multiple first connection lines and multiple second connection lines. On a plane perpendicular to the display substrate, the drive structure layer includes multiple conductive layers sequentially disposed on a base substrate. A data signal line, a first connection line and a second connection line are provided in different conductive layers. The second connection line extending in a second direction is connected to the first connection line extending in a first direction, and the first connection line extending in a first direction is connected to the data signal line extending in a second direction.

Abstract: A display substrate includes a plurality of sub-pixels, wherein at least one sub-pixel includes a driving circuit layer and a light emitting structure layer disposed on the driving circuit layer; the driving circuit layer includes a pixel driving circuit, and the light emitting structure layer includes a light emitting device connected with the pixel driving circuit; the pixel driving circuit includes a reset sub-circuit, a writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit and a light emitting control sub-circuit; and at least one of the reset sub-circuit, the compensation sub-circuit, and the writing sub-circuit includes an oxide transistor and a one-way conductive device.

Abstract: A display panel, a driving method and a display apparatus are disclosed. The display panel includes: a substrate, an active semiconductor layer, a gate insulating layer, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a first interlayer insulating layer, a third conductive layer including a plurality of first signal lines, a second interlayer insulating layer, a fourth conductive layer including a plurality of second signal lines stacked in that order. Orthographic projections of the first signal lines on the substrate and orthographic projections of the second signal lines on the substrate are arranged in an intersecting manner.

Abstract: A pixel circuit includes a light-emitting element, a driving circuit, a compensation control circuit, a data writing-in circuit, a first reset circuit, a light-emitting control circuit and an energy storage circuit; the compensation control circuit controls to connect the control end and the first end of the driving circuit; the data writing-in circuit writes a data voltage into the second end of the driving circuit; the first reset circuit writes a reference voltage into the control end of the driving circuit under the control of a reset control signal; the energy storage circuit is electrically connected to the control end of the driving circuit and the first electrode of the light-emitting element, and is configured to store electrical energy; the driving circuit controls to connect the first end and the second end of the driving circuit under the control of the control end thereof.

Abstract: A display substrate includes a first wiring region (110) and a second wiring region (120), wherein the first wiring region (110) is provided with at least one first wiring (71) and a light emitting device, the second wiring region (120) is provided with at least one second wiring (72) and a light emitting device, and the light emitting device at least includes an anode (90). The first wiring region (110) further includes at least one first compensation line (81), an orthographic projection of the at least one anode (90) in the plane of the display substrate at least partially overlaps with an orthographic projection of the first compensation line (81) in the plane of the display substrate.

Abstract: A shift register includes a first input sub-circuit being configured to transmit an input signal to a first node under control of a first clock signal; a second input sub-circuit being configured to transmit a first voltage signal to a second node under control of the first clock signal; a first control sub-circuit being configured to transmit a second clock signal to a third node under control of a voltage at the second node; a second control sub-circuit being configured to transmit the first voltage signal to a fourth node under control of a third clock signal; a noise reduction sub-circuit being configured to transmit the first voltage signal to a signal output terminal under control of a voltage at the fourth node; and an output sub-circuit being configured to transmit a second voltage signal to the signal output terminal under control of a voltage at the third node.

Abstract: A driving circuit of a display panel includes: a first driving control circuit configured to, in a first display state, provide a signal of an OFF signal terminal to a starting node of a first light emitting signal driver according to a control signal of an ON level provided by a control signal terminal; the first light emitting signal driver configured to, in the first display state, control a light emitting signal output terminal to provide an OFF-level signal to a light emitting control terminal of a pixel driving circuit in a first display region according to the signal of the OFF signal terminal; and a second light emitting signal driver configured to, in the first display state, control a light emitting signal output terminal to provide a light emitting signal to a light emitting control terminal of a pixel driving circuit in a second display region.

Abstract: Disclosed is a display substrate, which includes a base substrate, a plurality of first-region light emitting elements and a plurality of first-region pixel circuit. The base substrate includes a display region and a peripheral region at least partially surrounding the display region, wherein the display region includes a transparent display region. A plurality of first-region light emitting elements and a plurality of first-region pixel circuits are located in the transparent display region. At least one first-region pixel circuit of the plurality of first-region pixel circuits is electrically connected with at least two first-region light emitting elements emitting light in a same color. An orthographic projection of at least one first-region pixel circuit on the base substrate is overlapped with an orthographic projection of at least one first-region light emitting element on the base substrate.

Abstract: An all-analog spiking neural network circuit including at least one ReRAM-crossbar synapse array that conducts multiply-accumulate operations in parallel and a spike response model (SRM) neuron circuit, which is built with complementary metal-oxide-semiconductor (CMOS) technology. The neuron circuits receive outputs from the ReRAM-crossbar synapse array and directly process the output currents from the ReRAM-crossbar synapse arrays to complete the multiply-accumulate operation and produce processed voltage spike trains.

Abstract: The present disclosure provides a shift register unit and a driving method therefor, a gate drive circuit, and a display device, belonging to the field of display technologies. In the shift register unit, a first input circuit can control a potential of a first node under control of a first clock signal provided by a first clock terminal and control a potential of a third node under control of a potential of a second node. A second input circuit can control the potential of the second node under control of the first clock signal, an input control signal provided by an input control terminal, the potential of the third node, and the potential of the first node. An output circuit can transmit a pull-up power signal at a high potential or a pull-down power signal at a low potential to an output terminal under control of the third node.

Abstract: A shift register includes an input circuit, a first output circuit, a first control circuit, a second control circuit and a second output circuit. The input circuit is configured to transmit an input signal provided by an input signal terminal to a first node. The first output circuit is configured to transmit a first output signal provided by a first output signal terminal to a scan signal terminal. The first control circuit is configured to transmit a third output signal provided by a third output signal terminal to a second node. The second control circuit is configured to control a potential at the first node and a potential at the second node to be two inverted potentials. The second output circuit is configured to transmit a second output signal provided by a second output signal terminal to the scan signal terminal.

Abstract: A display substrate includes a plurality of sub-pixels, wherein at least one sub-pixel includes a driving circuit layer and a light emitting structure layer disposed on the driving circuit layer; the driving circuit layer includes a pixel driving circuit, and the light emitting structure layer includes a light emitting device connected with the pixel driving circuit; the pixel driving circuit includes a reset sub-circuit, a writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, an energy storage sub-circuit and a light emitting control sub-circuit; and at least one of the reset sub-circuit, the compensation sub-circuit, and the writing sub-circuit includes an oxide transistor and a one-way conductive device.

Abstract: Provided are a display panel and a display apparatus. The display panel includes: a substrate; a plurality of touch electrodes at least partially located on the substrate in a display area; a plurality of touch leads located on the substrate, one ends of the touch leads being coupled to the touch electrodes, and the other ends of the touch leads being located in a peripheral area; a plurality of data leads located on the substrate in the peripheral area; and a plurality of shield lines located on the substrate in the peripheral area, orthographic projections of the shield lines on the substrate being located between orthographic projections of the touch leads on the substrate and orthographic projections of the data leads on the substrate, and at least two of the plurality of shield lines in the display panel being connected to each other in a shorted manner.

Abstract: An electrical connector includes at least one electrical module. The electrical module includes: an insulating body, where multiple first accommodating slots are concavely provided on a first side toward a second side of the insulating body; multiple first terminal assemblies, respectively accommodated in the corresponding first accommodating slots; and a first grounding member, having multiple first spokes and multiple second spokes. Each first terminal assembly includes a first insulating block, a pair of first signal terminals, and a first shielding shell. Each first shielding shell has a first shielding side surface exposed to the first side. Each first spoke is in mechanical contact with the first shielding shells of a same electrical module, and each second spoke is in contact with the first shielding side surface of the corresponding first shielding shell, thus achieving conduction between the first shielding shells and the first grounding member.

Abstract: A linker peptide for constructing a fusion protein. The linker peptide comprises a flexible peptide and a rigid peptide. The flexible peptide consists of one or more flexible units. The rigid peptide consists of one or more rigid units. The flexible unit comprises two or more amino acid residues selected from Gly, Ser, Ala, and Thr. The rigid unit comprises a human chorionic gonadotropin ?-subunit carboxy-terminal peptide (CTP) bearing a plurality of glycosylation sites. The linker peptide can more effectively eliminate mutual steric hindrance of two fusion molecules, decreasing a reduction/loss of polymerization or activity resulting from improper folding of an active protein or a conformational change. On the other hand, the negatively charged, highly sialylated CTP can resist renal clearance, further prolonging a half-life of a fused molecule and enhancing bioavailability of a fused protein.

Abstract: A display panel, including: a substrate base plate; touch electrodes; touch lead wires on the substrate base plate, one end of the touch lead wire is coupled with the touch electrode, the other end thereof is in a peripheral area, the touch lead wires in the display panel are divided into touch lead wire sets, each touch lead wire set includes touch lead wires; data lead wires on the substrate base plate in the peripheral area, the data lead wires are divided into data lead wire sets, each data lead wire set includes data lead wires, the touch lead wire sets and the data lead wire sets are distributed in a staggered manner; at least one shielding line on the substrate base plate in the peripheral area, an orthographic projection of the shielding line is between orthographic projections of the touch lead wire and the data lead wire.