Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.

Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

Abstract: A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.

Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.

Abstract: Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.

Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.

Abstract: A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device.

Abstract: Provided are an apparatus, storage device, and method for compressing error vectors for decoding logic to store compressed in an decoder memory used by the decoding logic. A decoder decodes codewords to produce error vectors used to decode the codewords. A decoder memory device stores the error vectors. A compression unit receives the error vector from the decoder during decoding of the codeword. Each bit in the error vector has one of a first value and a second value. A determination is made of at least one bit location in the error vector having the first value. At least one pointer is stored in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.

Abstract: An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.

Abstract: Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.

Abstract: One-sided soft reads can enable improved error-correction over regular reads without significantly increasing the latency for reads. In one example, a flash storage device includes an array of storage cells and a controller to access the array of storage cells. The controller is to perform at least one read of a storage cell to cause a read strobe to be applied at an expected read reference voltage and also cause one or more additional read strobes to be applied at voltages on only one side of the expected read reference voltage (e.g., which in some cases involves applying the additional one or more read strobes at a voltage with a slightly lower or higher magnitude than the magnitude of the expected read reference voltage). The controller can then provide a logic value and one or more bits indicating confidence or reliability of the logic value's accuracy based on an electrical response of the storage cell to the read strobe and the one or more additional read strobes.

Abstract: Devices, systems, and methods that reduce the latency of detecting that a codeword is uncorrectable are disclosed and described. Such devices, systems, and methods allow the determination that a codeword is uncorrectable prior to determining error locations in the codeword, thus eliminating the need for such an error location search.

Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.

Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.

Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device. Additional embodiments may be described and claimed.

Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.

Abstract: A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

Abstract: Provided are an apparatus, storage device, and method for compressing error vectors for decoding logic to store compressed in an decoder memory used by the decoding logic. A decoder decodes codewords to produce error vectors used to decode the codewords. A decoder memory device stores the error vectors. A compression unit receives the error vector from the decoder during decoding of the codeword. Each bit in the error vector has one of a first value and a second value. A determination is made of at least one bit location in the error vector having the first value. At least one pointer is stored in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.