Abstract: Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus related to non-volatile memory page sector rotation are described. In one embodiment, logic rotates the order of one or more sectors by a rotation value prior to storage of the one or more sectors in a non-volatile memory device. Logic then rotates the one or more sectors back by the rotation value after reading the one or more sectors from the non-volatile memory device. Furthermore, at least one indirection block (corresponding to the one or more sectors) is stored in at least two different logical memory pages of the non-volatile memory. Other embodiments are also disclosed and claimed.

Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

Abstract: Embodiments are generally directed to errors and erasures decoding from multiple memory devices. An apparatus may include logic to store a portion of an error correction codeword in each of multiple memory devices, and logic to decode errors and erasures for the memory devices. The decoding of the errors and erasures includes reading the portions of the error correction codeword from a subset of the memory devices to generate a partial codeword, with the subset excluding at least one of the memory devices. The decoding of the errors and erasures further includes decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword if the errors and erasures can be decoded from the partial codeword, and, upon determining that the errors and erasures cannot be decoded from the partial codeword, then reading the one or more portions of the error correction codeword from the memory devices excluded from the first subset to generate a complete codeword.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to load an error correction codeword retrieved from a memory and apply a first error correction decoder to decode the error correction codeword, wherein the first error correction decoder implements a bit-flipping error correction algorithm which utilizes a variable bit-flipping threshold to determine whether to flip a bit in an error correction codeword. Other embodiments are also disclosed and claimed.

Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

Abstract: Apparatus, systems, and methods for AES integrity check in memory are described. In one embodiment, a controller comprises logic to receive a write request from a host device to write a line of data to the memory device, determine a first plaintext cyclic redundancy check from the line of data, encrypt the line of data, encrypt the first plaintext CRC with a unique value to generate a first encrypted CRC, and store the encrypted line of data and the first encrypted CRC in memory. Other embodiments are also disclosed and claimed.

Abstract: Techniques for error correction of encoded data are described. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is then made as to whether the ECC encoded data includes a single error, two errors or more than two errors. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes two errors, first and second error locations are identified. If the ECC encoded data includes more than two errors, separate error locations are identified for the more than two errors. The single error, the two errors or the more than two errors is/are corrected and the ECC encoded data is then be decoded.

Abstract: In various embodiments, an iterative decoder may compute, from sign bits of log likelihood ratios associated with x bits of a plurality of bits of encoded data, a first combination of the x bits having a higher associated log density ratio than any other combination of the x bits. In various embodiments, the iterative decoder may further be configured to compute m combinations of the x bits having m highest associated log density ratios, based on reductions in log density ratios associated with one or more sub-combinations of the x bits and the computed first combination of the x bits. In various embodiments, a variable node associated with the iterative decoder may be updated with the m combinations of the x bits.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for dividing error correcting code (“ECC”) codewords into portions and storing the portions among multiple die of non-volatile memory (“NVM”). For example, a device may include memory including a first die and a second die, and a memory controller configured to store a first portion of a codeword for use with an error correcting code in a first segment of the first die and to store a second portion of the codeword in a first segment of the second die. In various embodiments, the first segment of the second die may be offset from the first segment of the first die. Other embodiments may be described and/or claimed.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to load an error correction codeword retrieved from a memory and apply a first error correction decoder to decode the error correction codeword, wherein the first error correction decoder implements a bit-flipping error correction algorithm which utilizes a variable bit-flipping threshold to determine whether to flip a bit in an error correction codeword. Other embodiments are also disclosed and claimed.

Abstract: A codeword may have errors and erasures. In embodiments, an apparatus may include a syndrome calculator configured to generate partial syndromes of the codeword, an erasure locator configured to generate an erasure locator polynomial, and a syndrome modifier configured to generate modified partial syndromes based at least in part on the partial syndromes and the erasure locator polynomial. The apparatus may further include an error locator configured to generate an error locator polynomial using the modified partial syndromes, for error and erasure decoding of the codeword.

Abstract: Methods and apparatus related to non-volatile memory page sector rotation are described. In one embodiment, logic rotates the order of one or more sectors by a rotation value prior to storage of the one or more sectors in a non-volatile memory device. Logic then rotates the one or more sectors back by the rotation value after reading the one or more sectors from the non-volatile memory device. Furthermore, at least one indirection block (corresponding to the one or more sectors) is stored in at least two different logical memory pages of the non-volatile memory. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for performing data decoding and error correction. In various embodiments, a plurality of bits of encoded data may be received, e.g., by an iterative decoder. In various embodiments, the iterative decoder may generate a set of m tuples A, each tuple in set A including a symbol comprising a group of bits of the encoded data and a probability associated with the symbol. In various embodiments, the encoded data may be decoded using the set of m tuples. In various embodiments, this may include allocating fewer bits to storage of a probability associated with a first tuple of the set A than are allocated for storage of a probability associated with a second tuple of the set A. Other embodiments may be described and/or claimed.

Abstract: Techniques and mechanisms to facilitate data error detection by a memory controller. In an embodiment, the memory controller calculates, for each of a plurality of data blocks, a respective result based on a first metadata value and data of that data block, where the first metadata value describes a characteristic which is common to each of the plurality of data blocks. With each such calculated result, the memory controller further performs a respective error detection analysis, wherein such analysis is based on a retrieved error correction code for a corresponding one of the plurality of data blocks. In another embodiment, a single version of the metadata value is stored by the memory controller, where the single version of the metadata value is made available to facilitate error detection for any of the plurality of data blocks.

Abstract: Examples are disclosed for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is made as to whether the ECC encoded data includes either a single error or more than one error. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes more than one error, separate error locations are identified for the more than one error. The single error or the more than one error is corrected and the ECC encoded data is then be decoded.

Abstract: Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.

Abstract: Embodiments of apparatus and methods for decoding errors and erasures are described. A codeword may have errors and erasures. In embodiments, an apparatus may include a syndrome calculator configured to generate partial syndromes of the codeword, an erasure locator configured to generate an erasure locator polynomial, and a syndrome modifier configured to generate modified partial syndromes based at least in part on the partial syndromes and the erasure locator polynomial. The apparatus may further include an error locator configured to generate an error locator polynomial using the modified partial syndromes, for error and erasure decoding of the codeword. Other embodiments may be described and/or claimed.