Abstract: Techniques and mechanisms to facilitate data error detection by a memory controller. In an embodiment, the memory controller calculates, for each of a plurality of data blocks, a respective result based on a first metadata value and data of that data block, where the first metadata value describes a characteristic which is common to each of the plurality of data blocks. With each such calculated result, the memory controller further performs a respective error detection analysis, wherein such analysis is based on a retrieved error correction code for a corresponding one of the plurality of data blocks. In another embodiment, a single version of the metadata value is stored by the memory controller, where the single version of the metadata value is made available to facilitate error detection for any of the plurality of data blocks.

Abstract: Examples are disclosed for techniques for error correction of encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data includes one or more errors. A determination may be made as to whether the ECC encoded data includes a single error, two errors or more than two errors. If the ECC encoded data includes a single error, an error location of the error may be identified. If the ECC encoded data includes two errors, first and second error locations may be identified. If the ECC encoded data includes more than two errors, separate error locations may be identified for the more than two errors. The single error, the two errors or the more than two errors may be corrected and the ECC encoded data may then be decoded. Other examples are described and claimed.

Abstract: Examples are disclosed for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data includes one or more errors. A determination may be made as to whether the ECC encoded data includes either a single error or more than one error. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes more than one error, separate error locations may be identified for the more than one error. The single error or the more than one error may be corrected and the ECC encoded data may then be decoded. Other examples are described and claimed.

Abstract: Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.

Abstract: Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for dividing error correcting code (“ECC”) codewords into portions and storing the portions among multiple die of non-volatile memory (“NVM”). For example, a device may include memory including a first die and a second die, and a memory controller configured to store a first portion of a codeword for use with an error correcting code in a first segment of the first die and to store a second portion of the codeword in a first segment of the second die. In various embodiments, the first segment of the second die may be offset from the first segment of the first die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for data decoding and/or error correction. In various embodiments, an iterative decoder may compute, from sign bits of log likelihood ratios associated with x bits of a plurality of bits of encoded data, a first combination of the x bits having a higher associated log density ratio than any other combination of the x bits. In various embodiments, the iterative decoder may further be configured to compute m combinations of the x bits having m highest associated log density ratios, based on reductions in log density ratios associated with one or more sub-combinations of the x bits and the computed first combination of the x bits. In various embodiments, a variable node associated with the iterative decoder may be updated with the m combinations of the x bits. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for performing data decoding and error correction. In various embodiments, a plurality of bits of encoded data may be received, e.g., by an iterative decoder. In various embodiments, the iterative decoder may generate a set of m tuples A, each tuple in set A including a symbol comprising a group of bits of the encoded data and a probability associated with the symbol. In various embodiments, the encoded data may be decoded using the set of m tuples. In various embodiments, this may include allocating fewer bits to storage of a probability associated with a first tuple of the set A than are allocated for storage of a probability associated with a second tuple of the set A. Other embodiments may be described and/or claimed.

Abstract: Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion; an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword; a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder; and a correction unit to correct the data portion of the codeword via the generated first parity portion.

Abstract: Methods and apparatuses for Bose-Chaudhuri-Hocquenghem (BCH) decoding utilizing Berlekamp-Massey Algorithm (BMA) and Chien Search. The BMA may utilize one or more of a scalable semi-parallel shared multiplier array, a conditional q-ary inversionless BMA and/or a conditional binary Inversionless BMA. The Chien Search may be accomplished utilizing a non-rectangular multiplier array.

Abstract: Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion; an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword; a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder; and a correction unit to correct the data portion of the codeword via the generated first parity portion.

Abstract: Methods and apparatuses for Bose-Chaudhuri-Hocquenghem (BCH) decoding utilizing Berlekamp-Massey Algorithm (BMA) and Chien Search. The BMA may utilize one or more of a scalable semi-parallel shared multiplier array, a conditional q-ary inversionaless BMA and/or a conditional binary Inversionless BMA. The Chien Search may be accomplished utilizing a non-rectangular multiplier array.