Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer over an inner wall and a bottom of the trench. The method includes forming a mask layer over the gate dielectric layer over the bottom. The method includes removing the gate dielectric layer over the inner wall. The method includes removing the mask layer. The method includes forming a gate electrode in the trench.

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure including a stack of alternating first and second semiconductor layers on a substrate, removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers. The method also includes depositing a first oxygen blocking layer and removing the native oxide thereof, depositing an n-type work function layer, and forming a second oxygen blocking layer in sequence on the gate dielectric layer to surround the second semiconductor layers in the same process chamber. The second oxygen blocking layer includes a capping layer and a capping film. The method further includes forming a metal gate fill material over the capping film to form a gate-all-around structure.

Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure including a stack of alternating first and second semiconductor layers on a substrate, removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers. The method also includes depositing a first oxygen blocking layer and removing the native oxide thereof, depositing an n-type work function layer, and forming a second oxygen blocking layer in sequence on the gate dielectric layer to surround the second semiconductor layers in the same process chamber. The second oxygen blocking layer includes a capping layer and a capping film. The method further includes forming a metal gate fill material over the capping film to form a gate-all-around structure.

Abstract: A method of forming a semiconductor device includes forming a hafnium-containing layer over a semiconductor layer, simultaneously performing a thermal annealing process and applying an electrical field to the hafnium-containing layer to form a ferroelectric hafnium-containing layer, and forming a gate electrode over the ferroelectric hafnium-containing layer.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

Abstract: A method for forming a semiconductor arrangement includes forming a fin. A diffusion process is performed to diffuse a first dopant into the channel region of the fin. A first gate electrode is formed over the channel region of the fin after the first dopant is diffused into the channel region of the fin.

Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive feature over a semiconductor substrate. The method includes forming an oxygen-absorbing layer on a surface of the first conductive feature. The oxygen-absorbing layer absorbs oxygen from the first conductive feature and becomes an oxygen-containing layer. The method includes removing the oxygen-containing layer to expose the surface originally covered by the oxygen-containing layer. The method includes forming a metal-containing layer on the surface. The method includes forming a second conductive feature on the metal-containing layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

Abstract: Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool.

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Abstract: A method of forming a semiconductor device includes forming a hafnium-containing layer over a semiconductor layer, simultaneously performing a thermal annealing process and applying an electrical field to the hafnium-containing layer to form a ferroelectric hafnium-containing layer, and forming a gate electrode over the ferroelectric hafnium-containing layer.

Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.