DA conversion device
A DA conversion device includes a level determiner determining whether a level of the digital signal or the analog signal is higher than a predetermined threshold value; a DA converter including plural capacitors, an operational amplifier which generates the analog signal, and a plurality of transistors which connects each of the plural capacitors to a first or a second reference voltage according to the digital signal in a first connection state and connects the plural capacitors between an input terminal and an output terminal of the operational amplifier in a second connection state; and a setting part which receives a clock signal and sets gate-source voltages of the plurality of transistors such that the plurality of transistors is in the first connection state in a first period of the clock signal and the plurality of transistors is in the second connection state in a second period of the clock signal.
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This application claims the priority benefit of Japanese Patent Application No. 2019-075776, filed on Apr. 11, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND Technical FieldThe disclosure relates to a DA conversion device.
Description of Related ArtA circuit configuration of the DA converter 14 is shown in
Specifically, in
The operation of the DA converter 14 will be described below. The DA converter 14 has a sampling phase (first period) in which charge is charged into C1, C2 . . . Ci according to an input digital signal and a transfer phase (second period) in which charges of C1, C2 . . . Ci charged in the sampling phase are transferred to Cfb. The sampling phase and the transfer phase are alternatively generated. The controller controls the switches such that the plurality of capacitors C1, C2 . . . Ci are connected to the first reference voltage Vr+ or the second reference voltage Vr− according to input digital signals D1, D2 . . . Di. Specifically, when the input digital signal Di is a high voltage, the capacitor Ci is connected to the first reference voltage Vr+ and the analog reference voltage AGND and positive charge is charged thereinto in the sampling phase. When the input digital signal Di is a low voltage, the capacitor Ci is connected to the second reference voltage Vr− and analog reference voltage AGND and negative charge is charged thereinto. Meanwhile, the controller controls the switches such that the capacitors C1, C2 . . . Ci are connected between the input terminal and the output terminal of the operational amplifier 15 in the transfer phase. Here, the capacitors C1, C2 . . . Ci are connected in parallel between the input terminal and the output terminal of the operational amplifier 15, for example, as shown in
When the output signal Vout of the DA converter 14 is high, generation of significant distortion at the output of the DA converter 14 is conceivable. Since the transistor switches SY1, SY2 . . . SYi of
The disclosure provides a DA conversion device which suppress the increase in power consumption while improving distortion characteristics.
In one embodiment, the disclosure provides a DA conversion device which converts a digital signal into an analog signal. The DA conversion device includes: a level determiner which determines whether a level of the digital signal or the analog signal is higher than a predetermined threshold value; a DA converter including a plurality of capacitors, an operational amplifier which generates the analog signal, and a plurality of transistors which connects the plurality of capacitors to a first reference voltage or a second reference voltage according to the digital signal in a first connection state and connects the plurality of capacitors between an input terminal and an output terminal of the operational amplifier in a second connection state; and a setting part which receives a clock signal and sets gate-source voltages of the plurality of transistors such that the plurality of transistors is in the first connection state in a first period of the clock signal and the plurality of transistors is in the second connection state in a second period of the clock signal. The setting part sets absolute values of gate-source voltages of at least a portion of the plurality of transistors to be lower than absolute values of the gate-source voltages of a case in which the level determiner determines that the level is higher than the threshold value when the level determiner determines that the level is lower than the threshold value.
(Configuration)
The level determiner 19 generates the control signal LVDET in response to the magnitude of a signal in the DA conversion device 100 and inputs the control signal LVDET to the DA converter 140. Specifically, the level determiner 19 switches between a high voltage and a low voltage of the control signal LVDET based on the magnitude of the signal in the DA conversion device 100. Meanwhile, although the control signal LVDET is generated based on the magnitude of an output signal of the interpolation filter 11 in
A configuration example of the DA converter 140 in the embodiment 1 is shown in
As shown in
The setting part, which includes a clock generation circuit 16, a clock buffer 17 and a clock buffer 180, receives a clock signal CLK and sets gate-source voltages of the plurality of transistors SY1, SY2, . . . , SYi such that the plurality of transistors SY1, SY2, . . . , SYi is in the first connection state in a first period (sampling phase) of the clock signal CLK. In addition, the setting part sets the gate-source voltages of the plurality of transistors SY1, SY2, . . . , SYi such that the plurality of transistors SY1, SY2, . . . , SYi is in the second connection state in a second period (transfer phase) of the clock signal CLK.
In addition, when the level determiner 19 determines that the level of the aforementioned digital signal or analog signal is lower than the predetermined threshold value Vdet, the setting part sets the absolute values of the gate-source voltages of at least a portion of the plurality of transistors SY1, SY2, . . . , SYi to be low as compared to a case in which the level determiner 19 determines that the level is higher than the predetermined threshold value Vdet.
(Operation)
An operation of the level determiner 19 to generate the control signal LVDET will be described. As described above, the level determiner 19 switches between the high voltage (e.g., “1”) and the low voltage (e.g., “0”) of the control signal LVDET based on the magnitude of the signal in the DA conversion device 100. The level determiner 19 determines whether the level of a signal having a correlation with the output signal of the DA converter 140 is higher than the predetermined threshold value Vdet.
In the embodiment 1, the level determiner 19 switches the control signal LVDET from the low voltage to the high voltage when the magnitude of the object signal in the DA conversion device 100 exceeds the predetermined threshold value (reference value) Vdet. In addition, the level determiner 19 switches the control signal LVDET from the high voltage to the low voltage according to which is later between when a first reference time Thold has elapsed from when the magnitude of the object signal in the DA conversion device 100 exceeds the predetermined threshold value Vdet and when a state in which the magnitude of the object signal is equal to or less than the predetermined threshold value Vdet continues for a second reference time Tdet. Meanwhile, as another embodiment, a configuration in which the high voltage and the low voltage of the control signal LVDET are reversed is also possible.
A specific example will be described with reference to
As shown in
In addition, when the level determiner 19 determines that the level of the aforementioned digital signal or analog signal is lower than the predetermined threshold value Vdet, the setting part sets the gate-source voltages of at least a portion of the aforementioned plurality of N-channel transistors to be lower than those when the level determiner 19 determines that the level is higher than the predetermined threshold value Vdet. Further, when the level determiner 19 determines that the level is lower than the predetermined threshold value Vdet, the setting part sets the gate-source voltages of at least a portion of the plurality of P-channel transistors to be higher than those when the level determiner 19 determines that the level is higher than the predetermined threshold value Vdet.
Furthermore, as shown in
That is, when the output signal Vout is low, the outputs of the clock buffers of the related art, that is, the same output signal as that of the DA converter 14, can be obtained. On the other hand, when the output signal Vout is high, Φ2p is the output of the clock buffer 180 having a low voltage dropped from VSS and Φ2n is the output of the clock buffer 180 having a high voltage boosted from VDD.
The above-described configuration achieves the same power consumption as that of the related art when the output signal Vout is low because the voltage dropping circuit 26 and the voltage boosting circuit 27 of
On the other hand, when the output signal Vout is high, the gate-source voltages of the transistors SY1, SY2, . . . , SYi increase because the voltage dropping circuit 26 and the voltage boosting circuit 27 cause power up (i.e., the voltage dropping circuit 26 and the voltage boosting circuit 27 are driven when Vout is high), and thus signal dependency of resistance values of the transistors SY1, SY2 . . . SYi is reduced and distortion characteristics decrease.
Embodiment 2(Configuration)
The configuration of the DA conversion device 100 in the embodiment 2 is the same as that in the embodiment 1. The embodiment 2 differs from the embodiment 1 in that configurations of a DA converter 141 and a clock buffer 181 are different from those of the DA converter 140 and the clock buffer 180 of the embodiment 1. A configuration diagram of the DA converter 141 is shown in
(Operation)
A procedure of generating the control signal LVDET is the same as that of the embodiment 1. In the configurations of
When the control signal LVDET is “1,” the power dropping circuit 26 and the power boosting circuit 27 are powered up. As shown in
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
Claims
1. A DA conversion device which converts a digital signal into an analog signal, comprising:
- a level determiner which determines whether a level of the digital signal or the analog signal is higher than a predetermined threshold value;
- a DA converter including a plurality of capacitors, an operational amplifier which generates the analog signal, and a plurality of transistors which connects each of the plurality of capacitors to a first reference voltage or a second reference voltage according to the digital signal in a first connection state and connects the plurality of capacitors between an input terminal and an output terminal of the operational amplifier in a second connection state; and
- a setting part which receives a clock signal, and sets gate-source voltages of the plurality of transistors such that the plurality of transistors is in the first connection state in a first period of the clock signal and the plurality of transistors is in the second connection state in a second period of the clock signal,
- wherein the setting part sets absolute values of the gate-source voltages of at least a portion of the plurality of transistors to be lower than absolute values of the gate-source voltages of a case in which the level determiner determines that the level is higher than the threshold value when the level determiner determines that the level is lower than the threshold value.
2. The DA conversion device according to claim 1, wherein the setting part sets the gate-source voltages of at least a portion of a plurality of N-channel transistors among the plurality of transistors to be low when the level determiner determines that the level is lower than the threshold value as compared to a case in which the level determiner determines that the level is higher than the threshold value.
3. The DA conversion device according to claim 2, wherein the setting part sets the gate-source voltages of at least a portion of a plurality of P-channel transistors among the plurality of transistors to be high when the level determiner determines that the level is lower than the threshold value as compared to a case in which the level determiner determines that the level is higher than the threshold value.
4. The DA conversion device according to claim 1, wherein the setting part sets the gate-source voltages of at least a portion of a plurality of P-channel transistors among the plurality of transistors to be high when the level determiner determines that the level is lower than the threshold value as compared to a case in which the level determiner determines that the level is higher than the threshold value.
5. The DA conversion device according to claim 1, wherein the level determiner determines whether a level of a signal having a correlation with an output signal of the DA converter is higher than the predetermined threshold value.
6. The DA conversion device according to claim 1, wherein the level determiner generates a first control signal which becomes a first logic value of the first period after the level is determined to be higher than the predetermined threshold value, and generates a second control signal which becomes a first logic value of the second period after the level is determined to be lower than the predetermined threshold value, and
- the setting part sets the absolute values of the gate-source voltages of at least the portion of the plurality of transistors to be low in a case that the second control signal is transient from the first logic value to the second logic value when the first control signal is the second logic value or in a case that the first control signal is transient from the first logic value to the second logic value when the second control signal is the second logic value, as compared to a case in which the level determiner determines that the level is higher than the predetermined threshold value.
5172019 | December 15, 1992 | Naylor et al. |
5990819 | November 23, 1999 | Fujimori |
20080297390 | December 4, 2008 | Ko |
H0613901 | April 1994 | JP |
H1155121 | February 1999 | JP |
2013198064 | September 2013 | JP |
Type: Grant
Filed: Apr 9, 2020
Date of Patent: Oct 13, 2020
Assignee: Asahi Kasei Microdevices Corporation (Tokyo)
Inventor: Naoto Tamura (Tokyo)
Primary Examiner: Joseph J Lauture
Application Number: 16/843,894
International Classification: H03M 1/66 (20060101); H03M 3/00 (20060101); H03M 1/12 (20060101); H03M 1/80 (20060101); H03M 1/00 (20060101);