Multiple circuits coupled to an interface
An integrated circuit to drive a plurality of fluid actuation devices includes an interface, a first sensor, a second sensor, and control logic. The interface is to connect to a single contact pad of a host print apparatus. The first sensor is of a first type and is coupled to the interface. The second sensor is of a second type and is coupled to the interface. The second type is different from the first type. The control logic enables the first sensor or the second sensor to provide an enabled sensor. A voltage bias or a current bias applied to the interface generates a sensed current or a sensed voltage, respectively, on the interface indicating the state of the enabled sensor.
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This application is a U.S. National Stage Application of PCT Application No. PCT/US2019/016725, filed Feb. 6, 2019, entitled “MULTIPLE CIRCUITS COUPLED TO AN INTERFACE”.
BACKGROUNDAn inkjet printing system, as one example of a fluid ejection system, may include a printhead, an ink supply which supplies liquid ink to the printhead, and an electronic controller which controls the printhead. The printhead, as one example of a fluid ejection device, ejects drops of ink through a plurality of nozzles or orifices and toward a print medium, such as a sheet of paper, so as to print onto the print medium. In some examples, the orifices are arranged in at least one column or array such that properly sequenced ejection of ink from the orifices causes characters or other images to be printed upon the print medium as the printhead and the print medium are moved relative to each other.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific examples in which the disclosure may be practiced. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is to be understood that features of the various examples described herein may be combined, in part or whole, with each other, unless specifically noted otherwise.
Fluid ejection dies, such as thermal inkjet (TIJ) dies may be narrow and long pieces of silicon. To minimize the total number of contact pads on a die, it is desirable for at least some of the contact pads to provide multiple functions. Accordingly, disclosed herein are integrated circuits (e.g., fluid ejection dies) including a multipurpose contact pad (e.g., sense pad) coupled to a memory, thermal sensors, internal test logic, a timer circuit, a crack detector, and/or other circuitry. The multipurpose contact pad receives signals from each of the circuits (e.g., one at a time), which may be read by printer logic. By using a single contact pad for multiple functions, the number of contact pads on the integrated circuit may be reduced. In addition, the printer logic coupled to the contact pad may be simplified.
As used herein a “logic high” signal is a logic “1” or “on” signal or a signal having a voltage about equal to the logic power supplied to an integrated circuit (e.g., between about 1.8 V and 15 V, such as 5.6 V). As used herein a “logic low” signal is a logic “0” or “off” signal or a signal having a voltage about equal to a logic power ground return for the logic power supplied to the integrated circuit (e.g., about 0 V).
The interface 102 is configured to connect to a single contact pad of a host print apparatus, such as fluid ejection system 700 which will be described below with reference to
In one example, the first sensor 104 includes a thermal diode and the second sensor 106 includes a crack detector. Interface 102 may include a contact pad, a pin, a bump, or a wire. In one example, control logic 108 enables or disables the first sensor 104 and enables or disables the second sensor 106 based on data passed to integrated circuit 100. In another example, control logic 108 enables or disables the first sensor 104 and enables or disables the second sensor 106 based on data stored in a configuration register (not shown) of integrated circuit 100. Control logic 108 may include transistor switches, tristate buffers, and/or other suitable logic circuitry for controlling the operation of integrated circuit 100.
The select circuit 124 selects at least one memory cell of the plurality of memory cells 1220 to 122N. The control logic 108 enables either the first sensor 104, the second sensor 106, or the selected at least one memory cell such that a voltage bias or a current bias applied to the interface 102 generates a sensed current or a sensed voltage, respectively, on the interface 102 indicating the state of the enabled sensor or the selected at least one memory cell.
In one example, each of the plurality of memory cells 1220 to 122N includes a non-volatile memory cell, such as a floating gate transistor (e.g., a floating gate metal-oxide-semiconductor field-effect transistor), a programmable fuse, etc. In one example, select circuit 124 may include an address decoder, activation logic, and/or other suitable logic circuitry for selecting at least one memory cell 1220 to 122N in response to an address signal and a data signal.
The interface 202 is configured to connect to a single contact pad of a host print apparatus, such as the fluid ejection system of
In one example, the junction device 204 includes a thermal diode and the resistive device 206 includes a crack detector. Interface 202 may include a contact pad, a pin, a bump, or a wire. In one example, control logic 208 enables or disables the junction device 204 and enables or disables the resistive device 206 based on data passed to integrated circuit 200. In another example, control logic 208 enables or disables the junction device 204 and enables or disables the resistive device 206 based on data stored in a configuration register (not shown) of integrated circuit 200. Control logic 208 may include transistor switches, tristate buffers, and/or other suitable logic circuitry for controlling the operation of integrated circuit 200.
The select circuit 306 selects at least one memory cell of the plurality of memory cells 3040 to 304N such that a voltage bias or a current bias applied to the interface 302 generates a sensed current or a sensed voltage, respectively, on the interface 302 indicating the state of the selected at least one memory cell. In one example, each memory cell 3040 to 304N includes a floating gate transistor (e.g., a floating gate metal-oxide-semiconductor field-effect transistor). In another example, each memory cell 3040 to 304N includes a programmable fuse. In one example, select circuit 306 may include an address decoder, activation logic, and/or other suitable logic circuitry for selecting at least one memory cell 3040 to 304N in response to an address signal and a data signal.
In one example, the resistive sensor 322 may include a crack detector, such as a resistor. In one example, the junction sensor 324 may include a thermal sensor, such as a thermal diode. A voltage bias or a current bias applied to the interface 302 generates a sensed current or a sensed voltage, respectively, on the interface 302 indicating the state of the resistive sensor 322, the junction sensor 324, or a selected memory cell 3040 to 304N.
While memory cell 4040 is illustrated and described herein, the other memory cells 4041 to 404N include a similar circuit as memory cell 404o. The other side of the source-drain path of floating gate transistor 430 is electrically coupled to one side of the source-drain path of transistor 432. The gate of transistor 432 is electrically coupled to memory enable signal path 405. The other side of the source-drain path of transistor 432 is electrically coupled to one side of the source-drain path of transistor 434. The gate of transistor 434 is electrically coupled to a bit enable signal path 433. The other side of the source-drain path of transistor 434 is electrically coupled to a common or ground node 412.
The gate of transistor 408 is electrically coupled to a diode north (N) enable signal path 407. The other side of the source-drain path of transistor 408 is electrically coupled to the anode of thermal diode 410. The cathode of thermal diode 410 is electrically coupled to a common or ground node 412. The gate of transistor 414 is electrically coupled to a diode middle (M) enable signal path 413. The other side of the source-drain path of transistor 414 is electrically coupled to the anode of thermal diode 416. The cathode of thermal diode 416 is electrically coupled to a common or ground node 412. The gate of transistor 418 is electrically coupled to a diode south (S) enable signal path 417. The other side of the source-drain path of transistor 418 is electrically coupled to the anode of thermal diode 420. The cathode of thermal diode 420 is electrically coupled to a common or ground node 412. The gate of transistor 422 is electrically coupled to a crack detector enable signal path 419. The other side of the source-drain path of transistor 422 is electrically coupled to one side of crack detector 424. The other side of crack detector 424 is electrically coupled to a common or ground node 412.
The memory enable signal on memory enable signal path 405 determines whether a memory cell 4040 to 404N may be accessed. In response to a logic high memory enable signal, transistors 406 and 432 are turned on (i.e., conducting) to enable access to memory cells 4040 to 404N. In response to a logic low memory enable signal, transistors 406 and 432 are turned off to disable access to memory cells 4040 to 404N. With a logic high memory enable signal, a bit enable signal may be activated to access a selected memory cell 4040 to 404N. With a logic high bit enable signal, transistor 434 is turned on to access the corresponding memory cell. With a logic low bit enable signal, transistor 434 is turned off to block access to the corresponding memory cell. With a logic high memory enable signal and a logic high bit enable signal, the floating gate transistor 430 of the corresponding memory cell may be accessed for read and write operations through sense pad 402. In one example, the memory enable signal may be based on a data bit stored in a configuration register (not shown). In another example, the memory enable signal may be based on data passed to circuit 400 from a fluid ejection system, such as fluid ejection system 700 to be described below with reference to
Thermal diode 410 may be enabled or disabled via a corresponding diode N enable signal on diode N enable signal path 407. In response to a logic high diode N enable signal, the transistor 408 is turned on to enable the thermal diode 410 by electrically connecting thermal diode 410 to sense pad 402. In response to a logic low diode N enable signal, the transistor 408 is turned off to disable the thermal diode 410 by electrically disconnecting thermal diode 410 from sense pad 402. With thermal diode 410 enabled, the thermal diode 410 may be read through sense pad 402, such as by applying a current to sense pad 402 and sensing a voltage on sense pad 402 indicative of the temperature of thermal diode 410. In one example, the diode N enable signal may be based on data stored in a configuration register (not shown). In another example, the diode N enable signal may be based on data passed to circuit 400 from a fluid ejection system. Thermal diode 410 may be arranged at the northern or upper portion of a fluid ejection die as illustrated in
Thermal diode 416 may be enabled or disabled via a corresponding diode M enable signal on diode M enable signal path 413. In response to a logic high diode M enable signal, the transistor 414 is turned on to enable the thermal diode 416 by electrically connecting thermal diode 416 to sense pad 402. In response to a logic low diode M enable signal, the transistor 414 is turned off to disable the thermal diode 416 by electrically disconnecting thermal diode 416 from sense pad 402. With thermal diode 416 enabled, the thermal diode 416 may be read through sense pad 402, such as by applying a current to sense pad 402 and sensing a voltage on sense pad 402 indicative of the temperature of thermal diode 416. In one example, the diode M enable signal may be based on data stored in a configuration register (not shown). In another example, the diode M enable signal may be based on data passed to circuit 400 from a fluid ejection system. Thermal diode 416 may be arranged in a middle or central portion of a fluid ejection die as illustrated in
Thermal diode 420 may be enabled or disabled via a corresponding diode S enable signal on diode S enable signal path 417. In response to a logic high diode S enable signal, the transistor 418 is turned on to enable the thermal diode 420 by electrically connecting thermal diode 420 to sense pad 402. In response to a logic low diode S enable signal, the transistor 418 is turned off to disable the thermal diode 420 by electrically disconnecting thermal diode 420 from sense pad 402. With thermal diode 420 enabled, the thermal diode 420 may be read through sense pad 402, such as by applying a current to sense pad 402 and sensing a voltage on sense pad 402 indicative of the temperature of thermal diode 420. In one example, the diode S enable signal may be based on data stored in a configuration register (not shown). In another example, the diode S enable signal may be based on data passed to circuit 400 from a fluid ejection system. Thermal diode 420 may be arranged in a southern or lower portion of a fluid ejection die as illustrated in
In one example, crack detector 424 includes a resistor wiring separate from and extending along at least a subset of fluid actuation devices (e.g., fluid actuation devices 608 of
In one example, each elongate substrate 510, 512, 514, and 522 includes an integrated circuit 100 of
The second column 604 of contact pads is aligned with the first column 602 of contact pads and at a distance (i.e., along the Y axis) from the first column 602 of contact pads. The column 606 of fluid actuation devices 608 is disposed longitudinally to the first column 602 of contact pads and the second column 604 of contact pads. The column 606 of fluid actuation devices 608 is also arranged between the first column 602 of contact pads and the second column 604 of contact pads. In one example, fluid actuation devices 608 are nozzles or fluidic pumps to eject fluid drops.
In one example, the first column 602 of contact pads includes six contact pads. The first column 602 of contact pads may include the following contact pads in order: a data contact pad 610, a clock contact pad 612, a logic power ground return contact pad 614, a multipurpose input/output contact (e.g., sense) pad 616, a first high voltage power supply contact pad 618, and a first high voltage power ground return contact pad 620. Therefore, the first column 602 of contact pads includes the data contact pad 610 at the top of the first column 602, the first high voltage power ground return contact pad 620 at the bottom of the first column 602, and the first high voltage power supply contact pad 618 directly above the first high voltage power ground return contact pad 620. While contact pads 610, 612, 614, 616, 618, and 620 are illustrated in a particular order, in other examples the contact pads may be arranged in a different order.
In one example, the second column 604 of contact pads includes six contact pads. The second column 604 of contact pads may include the following contact pads in order: a second high voltage power ground return contact pad 622, a second high voltage power supply contact pad 624, a logic reset contact pad 626, a logic power supply contact pad 628, a mode contact pad 630, and a fire contact pad 632. Therefore, the second column 604 of contact pads includes the second high voltage power ground return contact pad 622 at the top of the second column 604, the second high voltage power supply contact pad 624 directly below the second high voltage power ground return contact pad 622, and the fire contact pad 632 at the bottom of the second column 604. While contact pads 622, 624, 626, 628, 630, and 632 are illustrated in a particular order, in other examples the contact pads may be arranged in a different order.
Data contact pad 610 may be used to input serial data to die 600 for selecting fluid actuation devices, memory bits, thermal sensors, configuration modes (e.g. via a configuration register), etc. Data contact pad 610 may also be used to output serial data from die 600 for reading memory bits, configuration modes, status information (e.g., via a status register), etc. Clock contact pad 612 may be used to input a clock signal to die 600 to shift serial data on data contact pad 610 into the die or to shift serial data out of the die to data contact pad 610. Logic power ground return contact pad 614 provides a ground return path for logic power (e.g., about 0 V) supplied to die 600. In one example, logic power ground return contact pad 614 is electrically coupled to the semiconductor (e.g., silicon) substrate 640 of die 600. Multipurpose input/output contact pad 616 may be used for analog sensing and/or digital test modes of die 600. In one example, multipurpose input/output contact (e.g., sense) pad 616 may provide sense interface 102 of
First high voltage power supply contact pad 618 and second high voltage power supply contact pad 624 may be used to supply high voltage (e.g., about 32 V) to die 600. First high voltage power ground return contact pad 620 and second high voltage power ground return contact pad 622 may be used to provide a power ground return (e.g., about 0 V) for the high voltage power supply. The high voltage power ground return contact pads 620 and 622 are not directly electrically connected to the semiconductor substrate 640 of die 600. The specific contact pad order with the high voltage power supply contact pads 618 and 624 and the high voltage power ground return contact pads 620 and 622 as the innermost contact pads may improve power delivery to die 600. Having the high voltage power ground return contact pads 620 and 622 at the bottom of the first column 602 and at the top of the second column 604, respectively, may improve reliability for manufacturing and may improve ink shorts protection.
Logic reset contact pad 626 may be used as a logic reset input to control the operating state of die 600. Logic power supply contact pad 628 may be used to supply logic power (e.g., between about 1.8 V and 15 V, such as 5.6 V) to die 600. Mode contact pad 630 may be used as a logic input to control access to enable/disable configuration modes (i.e., functional modes) of die 600. Fire contact pad 632 may be used as a logic input to latch loaded data from data contact pad 610 and to enable fluid actuation devices or memory elements of die 600.
Die 600 includes an elongate substrate 640 having a length 642 (along the Y axis), a thickness 644 (along the Z axis), and a width 646 (along the X axis). In one example, the length 642 is at least twenty times the width 646. The width 646 may be 1 mm or less and the thickness 644 may be less than 500 microns. The fluid actuation devices 608 (e.g., fluid actuation logic) and contact pads 610-632 are provided on the elongate substrate 640 and are arranged along the length 642 of the elongate substrate. Fluid actuation devices 608 have a swath length 652 less than the length 642 of the elongate substrate 640. In one example, the swath length 652 is at least 1.2 cm. The contact pads 610-632 may be electrically coupled to the fluid actuation logic. The first column 602 of contact pads may be arranged near a first longitudinal end 648 of the elongate substrate 640. The second column 604 of contact pads may be arranged near a second longitudinal end 650 of the elongate substrate 640 opposite to the first longitudinal end 648.
Printhead assembly 702 includes at least one printhead or fluid ejection die 600 previously described and illustrated with reference to
Ink supply assembly 710 supplies ink to printhead assembly 702 and includes a reservoir 712 for storing ink. As such, in one example, ink flows from reservoir 712 to printhead assembly 702. In one example, printhead assembly 702 and ink supply assembly 710 are housed together in an inkjet or fluid-jet print cartridge or pen. In another example, ink supply assembly 710 is separate from printhead assembly 702 and supplies ink to printhead assembly 702 through an interface connection 713, such as a supply tube and/or valve.
Carriage assembly 716 positions printhead assembly 702 relative to print media transport assembly 718, and print media transport assembly 718 positions print media 724 relative to printhead assembly 702. Thus, a print zone 726 is defined adjacent to nozzles 608 in an area between printhead assembly 702 and print media 724. In one example, printhead assembly 702 is a scanning type printhead assembly such that carriage assembly 716 moves printhead assembly 702 relative to print media transport assembly 718. In another example, printhead assembly 702 is a non-scanning type printhead assembly such that carriage assembly 716 fixes printhead assembly 702 at a prescribed position relative to print media transport assembly 718.
Service station assembly 704 provides for spitting, wiping, capping, and/or priming of printhead assembly 702 to maintain the functionality of printhead assembly 702 and, more specifically, nozzles 608. For example, service station assembly 704 may include a rubber blade or wiper which is periodically passed over printhead assembly 702 to wipe and clean nozzles 608 of excess ink. In addition, service station assembly 704 may include a cap that covers printhead assembly 702 to protect nozzles 608 from drying out during periods of non-use. In addition, service station assembly 704 may include a spittoon into which printhead assembly 702 ejects ink during spits to ensure that reservoir 712 maintains an appropriate level of pressure and fluidity, and to ensure that nozzles 608 do not clog or weep. Functions of service station assembly 704 may include relative motion between service station assembly 704 and printhead assembly 702.
Electronic controller 720 communicates with printhead assembly 702 through a communication path 703, service station assembly 704 through a communication path 705, carriage assembly 716 through a communication path 717, and print media transport assembly 718 through a communication path 719. In one example, when printhead assembly 702 is mounted in carriage assembly 716, electronic controller 720 and printhead assembly 702 may communicate via carriage assembly 716 through a communication path 701. Electronic controller 720 may also communicate with ink supply assembly 710 such that, in one implementation, a new (or used) ink supply may be detected.
Electronic controller 720 receives data 728 from a host system, such as a computer, and may include memory for temporarily storing data 728. Data 728 may be sent to fluid ejection system 700 along an electronic, infrared, optical or other information transfer path. Data 728 represent, for example, a document and/or file to be printed. As such, data 728 form a print job for fluid ejection system 700 and includes at least one print job command and/or command parameter.
In one example, electronic controller 720 provides control of printhead assembly 702 including timing control for ejection of ink drops from nozzles 608. As such, electronic controller 720 defines a pattern of ejected ink drops which form characters, symbols, and/or other graphics or images on print media 724. Timing control and, therefore, the pattern of ejected ink drops, is determined by the print job commands and/or command parameters. In one example, logic and drive circuitry forming a portion of electronic controller 720 is located on printhead assembly 702. In another example, logic and drive circuitry forming a portion of electronic controller 720 is located off printhead assembly 702.
Although specific examples have been illustrated and described herein, a variety of alternate and/or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and the equivalents thereof.
Claims
1. An integrated circuit for a fluid ejection device, the integrated circuit comprising:
- an interface to connect to a single contact pad of a host print apparatus;
- a first sensor of a first type coupled to the interface;
- a second sensor of a second type coupled to the interface, the second type being different from the first type; and
- control logic to enable the first sensor or the second sensor to provide an enabled sensor,
- wherein a voltage bias or a current bias applied to the interface generates a sensed current or a sensed voltage, respectively, on the interface indicating the state of the enabled sensor.
2. The integrated circuit of claim 1, further comprising:
- a plurality of memory cells coupled to the interface; and
- a select circuit to select at least one memory cell of the plurality of memory cells,
- wherein the control logic is to enable either the first sensor, the second sensor, or the selected at least one memory cell such that a voltage bias or a current bias applied to the interface generates a sensed current or a sensed voltage, respectively, on the interface indicating the state of the enabled sensor or the selected at least one memory cell.
3. The integrated circuit of claim 2, wherein each of the plurality of memory cells comprises a floating gate transistor.
4. The integrated circuit of claim 1, wherein the first sensor comprises a thermal diode.
5. The integrated circuit of claim 1, wherein the second sensor comprises a crack detector.
6. The integrated circuit of claim 1, wherein the interface comprises a contact pad, a pin, a bump, or a wire.
7. An integrated circuit for a fluid ejection device, the integrated circuit comprising:
- an interface to connect to a single contact pad of a host print apparatus and coupled to a plurality of memory cells; and
- a select circuit to select at least one memory cell of the plurality of memory cells such that a voltage bias or a current bias applied to the interface generates a sensed current or a sensed voltage, respectively, on the interface indicating the state of the selected at least one memory cell.
8. The integrated circuit of claim 7, wherein each of the plurality of memory cells comprises a floating gate transistor.
9. The integrated circuit of claim 7, further comprising:
- a resistive sensor coupled to the interface.
10. The integrated circuit of claim 7, further comprising:
- a junction sensor coupled to the interface.
11. The integrated circuit of claim 7, further comprising:
- a thermal sensor coupled to the interface.
12. The integrated circuit of claim 11, wherein the thermal sensor comprises a thermal diode.
13. The integrated circuit of claim 7, further comprising:
- a crack detector coupled to the interface.
14. The integrated circuit of claim 13, wherein the crack detector comprises a resistor.
15. A fluid ejection device comprising:
- a carrier; and
- a plurality of elongate substrates arranged parallel to each other on the carrier, each elongate substrate having a length, a thickness, and a width, the length being at least twenty times the width, wherein on each elongate substrate there is provided: an interface; a junction device coupled to the interface; a resistive device coupled to the interface; and control logic to enable or disable the junction device and the resistive device;
- wherein the carrier comprises electrical routing coupled to the interface of each of the elongate substrates such that a voltage bias or a current bias applied to the electrical routing generates a sensed current or a sensed voltage, respectively, on the electrical routing indicating the state of an enabled junction device or an enabled resistive device.
16. The fluid ejection device of claim 15, wherein on each elongate substrate there is provided:
- a plurality of memory cells coupled to the interface; and
- a select circuit to select at least one memory cell of the plurality of memory cells.
17. The fluid ejection device of claim 16, wherein each of the plurality of memory cells comprises a floating gate metal-oxide-semiconductor field-effect transistor.
18. The fluid ejection device of claim 16, wherein each of the plurality of memory cells comprises a fuse.
19. The fluid ejection device of claim 15, wherein the junction device comprises a thermal diode.
20. The fluid ejection device of claim 19, wherein on each elongate substrate there is provided:
- a plurality of thermal diodes spaced apart along the length of the elongate substrate.
21. The fluid ejection device of claim 15, wherein the resistive device comprises a crack detector.
5477245 | December 19, 1995 | Fuse |
5646672 | July 8, 1997 | Fukushima |
5745409 | April 28, 1998 | Wong et al. |
5801980 | September 1, 1998 | Wong |
5917509 | June 29, 1999 | Becerra |
5942900 | August 24, 1999 | DeMeerleer e |
6038166 | March 14, 2000 | Wong |
6116714 | September 12, 2000 | Imanaka et al. |
6161916 | December 19, 2000 | Gibson et al. |
6398332 | June 4, 2002 | Silverbrook et al. |
6616260 | September 9, 2003 | Skene et al. |
6866359 | March 15, 2005 | Pan et al. |
7267417 | September 11, 2007 | Silverbrook et al. |
7506961 | March 24, 2009 | Silverbrook |
7510255 | March 31, 2009 | Tamura et al. |
7613661 | November 3, 2009 | Nambudiri |
7802858 | September 28, 2010 | Kasai |
7874631 | January 25, 2011 | Sheahan et al. |
7954929 | June 7, 2011 | Edelen et al. |
8064266 | November 22, 2011 | Roohparvar |
8474943 | July 2, 2013 | Ness et al. |
8561910 | October 22, 2013 | Depaula et al. |
8888226 | November 18, 2014 | Gardner |
8960848 | February 24, 2015 | Yokouchi |
8977782 | March 10, 2015 | Miyasaka |
9224480 | December 29, 2015 | Grant et al. |
9472288 | October 18, 2016 | Gardner et al. |
9493002 | November 15, 2016 | Edelen et al. |
9592664 | March 14, 2017 | Ge et al. |
20020015066 | February 7, 2002 | Siwinski et al. |
20040017437 | January 29, 2004 | Yamaguchi |
20040239712 | December 2, 2004 | Liao et al. |
20050099458 | May 12, 2005 | Edelen |
20050140703 | June 30, 2005 | Ou |
20070194371 | August 23, 2007 | Benjamin |
20080049498 | February 28, 2008 | Werner |
20090040286 | February 12, 2009 | Tan et al. |
20090244132 | October 1, 2009 | Bruce |
20090251969 | October 8, 2009 | Roohparvar |
20100277527 | November 4, 2010 | Silverbrook et al. |
20100302293 | December 2, 2010 | Torgerson et al. |
20110018951 | January 27, 2011 | Muraki |
20120057408 | March 8, 2012 | Roohparvar et al. |
20130106930 | May 2, 2013 | Lea |
20150243362 | August 27, 2015 | Nigam |
20160009079 | January 14, 2016 | Clark et al. |
20160185123 | June 30, 2016 | Anderson et al. |
20160229179 | August 11, 2016 | Anderson |
20160250849 | September 1, 2016 | Sasaki |
20170028724 | February 2, 2017 | Edelen et al. |
20170069639 | March 9, 2017 | Ge et al. |
20170120590 | May 4, 2017 | Chen |
20170355188 | December 14, 2017 | Anderson et al. |
20180001618 | January 4, 2018 | Anderson et al. |
20180086122 | March 29, 2018 | Anderson |
20180154632 | June 7, 2018 | Chen et al. |
20180215147 | August 2, 2018 | Cumbie et al. |
20180345667 | December 6, 2018 | Edelen et al. |
20190016127 | January 17, 2019 | Linn |
20190126632 | May 2, 2019 | Anderson et al. |
2021001879 | February 2022 | CL |
1292753 | April 2001 | CN |
1332412 | January 2002 | CN |
1727186 | February 2006 | CN |
1749980 | March 2006 | CN |
1960875 | May 2007 | CN |
101567362 | October 2009 | CN |
101683788 | March 2010 | CN |
101868356 | October 2010 | CN |
101983378 | March 2011 | CN |
103619601 | March 2014 | CN |
105280637 | January 2016 | CN |
105636789 | June 2016 | CN |
105873765 | August 2016 | CN |
106685425 | May 2017 | CN |
107073949 | August 2017 | CN |
107111537 | August 2017 | CN |
107206815 | September 2017 | CN |
107428167 | December 2017 | CN |
108886366 | November 2018 | CN |
109922964 | June 2019 | CN |
1170132 | January 2002 | EP |
1054772 | July 2003 | EP |
1232868 | August 2006 | EP |
61-011845 | January 1986 | JP |
08-127162 | May 1996 | JP |
11-207948 | August 1999 | JP |
2002-014870 | January 2002 | JP |
2002-519808 | July 2002 | JP |
2002-232113 | August 2002 | JP |
2004-050637 | February 2004 | JP |
2011-517006 | May 2011 | JP |
2011-230374 | November 2011 | JP |
2014-017049 | January 2014 | JP |
2017-533126 | November 2017 | JP |
20180005525 | January 2018 | KR |
2579814 | April 2016 | RU |
2635080 02 | November 2017 | RU |
200631798 | September 2006 | TW |
201637880 | November 2016 | TW |
201637881 | November 2016 | TW |
201813825 | April 2018 | TW |
97/18953 | May 1997 | WO |
WO-2009064271 | May 2009 | WO |
WO-2013048430 | April 2013 | WO |
WO-2014133534 | September 2014 | WO |
WO-2016068927 | May 2016 | WO |
WO-2017189009 | November 2017 | WO |
2018/017066 | January 2018 | WO |
2018/156617 | August 2018 | WO |
WO-2018143942 | August 2018 | WO |
WO-2018156171 | August 2018 | WO |
2018/190864 | October 2018 | WO |
WO-2019009902 | January 2019 | WO |
WO-2019009904 | January 2019 | WO |
2020/162971 | August 2020 | WO |
Type: Grant
Filed: Feb 6, 2019
Date of Patent: Mar 28, 2023
Patent Publication Number: 20210213732
Assignee: Hewlett-Packard Development Company, L.P. (Spring, TX)
Inventors: James Michael Gardner (Corvallis, OR), Scott A. Linn (Corvallis, OR), Michael W. Cumbie (Corvallis, OR)
Primary Examiner: Thinh H Nguyen
Application Number: 16/956,331
International Classification: B41J 2/045 (20060101);