Switched mode power supply with power factor control
A circuit for use in a switched mode power supply includes a dual-boost power-factor correction converter having an active rectifier stage with first and second rectifier transistors and first and second boost stages each with an inductor and transistor. An active rectifier controller circuit generates control signals for driving the rectifier transistors, respectively, on and off in accordance with an AC input voltage. A PFC controller circuit generates a pulse-width-modulated (PWM) control signal that is based on an output voltage of the boost stages and which is further based on a current sense signal representing the current passing through the active rectifier stage. A logic circuit generates a control signal for the transistor of the first boost stage and a control signal for the transistor of the second boost stage, based on the PWM control signal and at least one of the control signals for the rectifier transistors.
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The present disclosure relates to the field of switching converters, in particular to a switched-mode power supply (SMPS) with power factor correction (PFC) and suitable control circuitry.
BACKGROUNDAC/DC converters with PFC are commonly used in switched-mode power supplies. PFC entails controlling the input current to be in phase with the alternating grid voltage and with a phase offset as small as possible. Minimizing the phase offset means minimizing the reactive power the power grid is loaded with. Several suitable circuit topologies are known as such, one of which is referred to as (bridgeless) dual-boost PFC converter. However, in many applications a standard boost PFC converter is used as controlling such standard circuitry is less complex.
One example of a standard boost PFC converter is discussed in the data sheet Texas Instruments “8-Pin Continuous Conduction Mode (CCM) PFC Controller” UCC28019, April 2007. In order to be able to minimize the phase difference between input current and input voltage, a current sensing circuit is needed which is usually implemented using a single current sense resistor. The above-mentioned dual-boost PFC converter topology has some advantages (e.g. lower conduction losses and lower cooling requirements) over the standard boost PFC converter topology. However, in a dual-boost PFC converter topology the load current splits into at least two separate circuit branches, which makes sensing a precise current more difficult. As a consequence, standard controllers for standard boost PFC converters cannot be used to control dual-boost PFC converters.
The inventors have identified a need for further improvement of the control of dual-boost PFC converters.
SUMMARYA circuit for use in a switched mode power supply is described herein. In accordance with one embodiment the circuit includes a dual-boost power-factor correction (PFC) converter having an active rectifier stage with a first and a second rectifier transistor, a first boost stage with a first inductor and a first transistor, and a second boost stage with a second inductor and a second transistor. The circuit further includes an active rectifier controller circuit configured to generate a first and a second control signal for driving the first and, respectively, the second rectifier transistor on and off in accordance with an AC input voltage. Further, the circuit includes a PFC controller circuit configured to generate a pulse-width-modulated (PWM) control signal that is based on an output voltage of the first and the second boost stage and which is further based on a current sense signal representing the current passing through the active rectifier stage. A logic circuit is configured to generate a third control signal for the first transistor of the first boost stage and a fourth control signal for the second transistor of the second boost stage based on the PWM control signal and at least one of the first and the second control signals.
A further embodiment relates to a method which may be used to operate a dual-boost PFC converter having an active rectifier stage with a first and a second rectifier transistor, a first boost stage with a first inductor and a first transistor, and a second boost stage with a second inductor and a second transistor. The method includes generating a first and a second control signal for driving the first and, respectively, the second rectifier transistor on and off in accordance with an AC input voltage; sensing a current passing through the active rectifier stage and providing a respective current sense signal; generating a PWM control signal based on an output voltage of the first and the second boost stage and further based on the current sense signal; and generating a third control signal for the first transistor of the first boost stage as well as a fourth control signal for the second transistor of the second boost stage based on the PWM control signal and at least one of the first and the second control signals.
The invention can be understood better with reference to the following drawings and descriptions. The components in the figures are not necessarily to scale; instead emphasis is placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings:
A first inductor L1 is connected between the input node IN1 and circuit node N1, and a second inductor L2 is connected between the input node IN2 and circuit node N2. Diodes D1 and D2 are connected between circuit node N1 and output node OUT1 and, respectively, circuit node N2 and output node OUT1, wherein the anodes of diodes D1 and D2 are connected to circuit nodes N1 and N2, respectively. MOSFETs Q1 and Q2 are connected between circuit node N1 and output node OUT2 and, respectively, circuit node N2 and output node OUT2. An output capacitor COUT is connected between the output nodes OUT1 and OUT2. It is noted that other types of transistors may be used instead of MOSFETs in other embodiments. The first inductor L1 and the MOSFET Q1 form a first boost stage, and the second inductor L2 and the MOSFET Q2 form a second boost stage. As will be discussed later, the first boost stage is active (PFC operation) during the positive semi-wave of the AC input voltage VIN_AC and the second boost stage is active during the negative semi-wave of the AC input voltage (and inactive otherwise). The fact that the PFC converter has two boost stages is the reason for the name dual-boost PFC converter.
To allow a low complexity of the control circuit, which generates the drive signals (gate voltages) for the MOSFETs, the MOSFETs Q1 and Q2 are driven with the same pulse-width modulated (PWM) signal. In order to improve the efficiency of the circuit, an active rectification is accomplished using MOSFETs Q3 and Q4, which are connected in parallel to diodes D3 and D4. It is noted that, in some embodiments, the intrinsic body diodes of MOSFETs Q3 and Q4 may serve as diodes D3 and D4. In other embodiments, the diodes D3, D4, D5, and D6 may be formed by a full-bridge rectifier (in this case, the intrinsic body diodes of the MOSFETs Q3 and Q4 are redundant). When using the circuit topology shown in
In
Once the MOSFET Q1 is switched on, the inductor current iL1 passes from the input node IN1 through the inductor L1 and the MOS channel of MOSFET Q1 (see
Once the MOSFET Q1 is switched off, the current path via MOSFET Q1 is blocked and, therefore, the inductor current iL1 passes from the input node IN1 through the inductor L1 and the output capacitor COUT (see
As mentioned,
Experimental verification of the two separate return paths is illustrated in
The right diagram of
Common analog controllers for PFC converters need one current sense signal, wherein usually the rectified current is measured using a current sense resistor. Applying this concept to the dual-boost converter of
Due to the fact that the inductor current is split into (at least) two current paths, a current sensor circuit is needed at three different positions of the circuit in order to be able to obtain the full current information. An example (based on
At this point it should be emphasized that a standard analog PFC controller circuit (such as, e.g., the 8-pin active PFC controller UCC28019 from Texas Instruments) only provides a single PWM signal as gate signal for the boost stage. As mentioned above, in dual-boost PFC converter topologies both transistors Q1 and Q2 may be driven by the same PWM signal generated by a standard analog PFC controller circuit. One consequence thereof is the split return current paths as discussed in detail above. Using a standard analog PFC controller circuit is strongly desired in many applications with the consequence that a rather complex current sensing is needed as described above with reference to
The embodiments described herein use the transistors Q3 and Q4 for active rectification to avoid losses in the rectifier diodes D3 and D4. Controller circuits for active rectifiers are as such known and thus not further discussed here. One example is illustrated in
The active rectifier controller 20 is configured to drive the transistor Q3 into an active (conducting) state during the positive semi-wave of the AC input voltage VIN_AC and into an inactive (non-conducting) state during the negative semi-wave. Conversely, the active rectifier controller 20 is configured to drive the transistor Q4 into an active (conducting) state during the negative semi-wave of the AC input voltage VIN_AC and into an inactive (non-conducting) state during the positive semi-wave. Accordingly, the outputs of the active rectifier controller 20 labelled “GateN” and “GateL” are connected to the gate electrodes of transistors Q3 and Q4, respectively. The respective gate signals are denoted as VG3, and VG4. As mentioned above, a simple PFC controller such as the controller circuit 10 generates only a single pulse-width-modulated drive signal VG (PWM gate signal). In the present example of
The function of the circuit of
As discussed above, due to the AND-combinations of the PWM signal VG and the gate signals VG3 and VG4, the gate signal VG1 (VG AND VG3) is pulse-width modulated during the positive semi-waves and zero (i.e. blanked, which means at a low level in the present example) during the negative semi-waves, thus blocking the second return current path in the negative semi-wave. Similarly, the gate signal VG2 (VG AND VG4) is pulse-width modulated during the negative semi-waves and blanked during the positive semi-waves, thus blocking the second return current path in the positive semi-wave. Basically the gate signal VG3 and/or the gate signal VG4 are used to distinguish the positive semi-wave from the negative semi-wave of the AC input voltage VIN_AC.
The functionality required to generate the gate signals VG1, VG2, VG3, and VG4 shown in
It is noted that the logic circuit used for generating the control signals VG1 and VG2 for the boost stages (i.e. gate signals for transistors Q1 and Q2) may be implemented in various different ways. One option is shown in
Below some embodiments described above are summarized. It is noted, however, that the following is merely an exemplary summary and not an exhaustive enucleation of technical features. One embodiment relates to a circuit including a dual-boost PFC converter having an active rectifier stage with a first and a second rectifier transistor (see, e.g.,
In one embodiment, the active rectifier controller circuit may be configured to generate the first and the second control signal (cf.
In one specific embodiment the first gate circuit may be configured to generate the third control signal by combining the PWM control signal and the first control signal (e.g.
A further embodiment, which is illustrated by the flow chart of
In one embodiment generating the PWM control signal may be performed by a PFC controller circuit (see, e.g.
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, in some applications, the logic levels may be inverted and different types of logic gates and complementary transistor types may be used. In particular with regard to the various functions performed by the above described components or structures (units, assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond—unless otherwise indicated—to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention.
Claims
1. A circuit, comprising:
- a dual-boost power-factor correction (PFC) converter including an active rectifier stage with a first rectifier transistor and a second rectifier transistor, a first boost stage with a first inductor and a first transistor, and a second boost stage with a second inductor and a second transistor;
- an active rectifier controller circuit configured to generate a first control signal and a second control signal for driving the first rectifier transistor and the second rectifier transistor, respectively, on and off in accordance with an AC input voltage;
- a PFC controller circuit configured to generate a pulse-width-modulated (PWM) control signal based on an output voltage of the first and the second boost stages and further based on a current sense signal representing the current passing through the active rectifier stage; and
- a logic circuit configured to generate a third control signal for the first transistor of the first boost stage and a fourth control signal for the second transistor of the second boost stage, based on the PWM control signal and at least one of the first and the second control signals.
2. The circuit of claim 1, wherein the active rectifier controller circuit is configured to generate the first and the second control signals such that the first rectifier transistor is conducting during a positive semi-wave and the second rectifier transistor is conducting during a negative semi-wave of the AC input voltage.
3. The circuit of claim 2, wherein the logic circuit is configured to generate the third control signal and the fourth control signal from the PWM control signal such that:
- the third control signal corresponds to the PWM control signal during the positive semi-wave and is blanked during the negative semi-wave of the AC input voltage; and
- the fourth control signal corresponds to the PWM control signal during the negative semi-wave and is blanked during the positive semi-wave of the AC input voltage.
4. The circuit of claim 3, wherein at least one of the first and the second control signals are used by the logic circuit to distinguish the positive semi-wave from the negative semi-wave of the AC input voltage.
5. The circuit of claim 1, wherein the logic circuit comprises:
- a first gate circuit configured to generate the third control signal by combining the PWM control signal and the first control signal; and
- a second gate circuit configured to generate the fourth control signal by combining the PWM control signal and the second control signal.
6. The circuit of claim 5, wherein the first gate circuit is an AND gate, and wherein the second gate circuit is an AND gate.
7. A method for operating a dual-boost power-factor correction (PFC) converter, which includes an active rectifier stage with a first rectifier transistor and a second rectifier transistor, a first boost stage with a first inductor and a first transistor, and a second boost stage with a second inductor and a second transistor, the method comprising:
- generating a first control signal and a second control signal for driving the first rectifier transistor and the second rectifier transistor, respectively, on and off in accordance with an AC input voltage;
- sensing a current passing through the active rectifier stage and providing a respective current sense signal;
- generating a pulse-width-modulated (PWM) control signal based on an output voltage of the first and the second boost stages and further based on the current sense signal; and
- generating a third control signal for the first transistor of the first boost stage and a fourth control signal for the second transistor of the second boost stage, based on the PWM control signal and at least one of the first and the second control signals.
8. The method of claim 7, wherein generating the PWM control signal is performed by a PFC controller circuit.
9. The method of claim 7, wherein generating the first and the second control signals is performed by an active rectifier control circuit.
10. The method of claim 7, wherein generating the third and the fourth control signals comprises:
- directing the PWM control signal to the first transistor of the first boost stage during a positive semi-wave of the AC input voltage; and
- directing the PWM control signal to the second transistor of the second boost stage during a negative semi-wave of the AC input voltage.
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Type: Grant
Filed: Dec 1, 2021
Date of Patent: Jul 4, 2023
Patent Publication Number: 20220181966
Assignee: Infineon Technologies Austria AG (Villach)
Inventor: Alessandro Pevere (Villach)
Primary Examiner: Jue Zhang
Application Number: 17/539,787