Abstract: A voltage regulator module includes: power input and output terminals at a same side of the voltage regulator module; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor having a vertical conductor embedded in a magnetic core, the vertical conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip which electrically connects the second end of the vertical conductor to the power output terminal such that power is delivered to and from the voltage regulator module at the same side of the voltage regulator module. A method of producing the voltage regulator module and electronic assembly that includes the voltage regulator module are also described.

Abstract: An apparatus comprises a solid state device and a switch in series with the solid state device. The apparatus comprises a leak detection component connected to the solid state device. The apparatus comprises a gate driver configured to drive a gate of the solid state device. The gate driver comprises test circuitry configured to apply a test voltage to the gate of the solid state device. The test voltage is less than a threshold voltage of the solid state device. The leak detection component is configured to detect a leakage of the solid state device.

Abstract: According to one configuration, an inductor device includes a core fabricated from multiple different types of magnetically permeable material. The inductor device includes an electrically conductive path extending through the core. A magnetic permeability of the core varies in magnitude depending on a distance with respect to the electrically conductive path.

Abstract: A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

Abstract: Disclosed is a method and a control circuit. The method includes operating a buffer circuit (1) in a first operating mode or a second operating mode. Operating the buffer circuit (1) in the first operating mode includes buffering, by a capacitor parallel circuit including a first capacitor (11) and a second capacitor (12), power (Po) provided by a power source (3) and received by a load (4). Operating the buffer circuit (1) in the second operating mode includes supplying power to the load (4) by the second capacitor (12), and regulating a first voltage (Upn) across the second capacitor (12), wherein regulating the first voltage (Upn) comprises transferring charge from the first capacitor (11) to the second capacitor (12).

Abstract: A controller for a power converter includes an output terminal operative to output a modulation signal for controlling a phase current of the power converter. A modulator is operative to generate the modulation signal such that an output voltage of the power converter follows a first portion of a load-line when load current is above a first threshold, the first portion of the load-line having a first slope that determines a rate of change of the output voltage as a function of the load current. An interface is operative to receive a temperature signal. Circuitry is operative to change the first threshold in response to receipt of the temperature signal.

Abstract: A monolithically integrated bidirectional switch includes: an output terminal; a control terminal; a compound semiconductor substrate; a common drift region in the compound semiconductor substrate and in series between the input terminal and the output terminal; a first gate; and a second gate. The first gate is electrically connected to the control terminal and the second gate is electrically connected to the input terminal, or one of the first gate and the second gate is a normally-on gate and the other one of the first gate and the second gate is a normally-off gate. In either case, the monolithically integrated bidirectional switch is configured to conduct current in a single direction from the input terminal to the output terminal through the common drift region. A corresponding power electronic system that uses the monolithically integrated bidirectional switch is also described.

Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Abstract: Current sense circuitry includes: a current mirror circuit for sensing a power transistor current; a capacitor directly connected to the current mirror circuit at a first node; and a comparator circuit having a first input electrically connected to an input terminal of the current mirror circuit, a second input electrically connected to a drain or source terminal of the power transistor, and an output that is in a first state when a voltage at the first input is higher than a voltage at the second input and in a second state when the voltage at the first input is lower than the voltage at the second input. Current is sourced to the first node if the power transistor is on and the comparator output is in the second state, and sunk from the first node if the power transistor is on and the comparator output is in the first state.

Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

Abstract: A power factor correction (PFC) stage, controller, and control method are described. The PFC stage includes: a totem-pole converter having an input inductor for coupling to ac mains, first and second pairs of power switches, and an output capacitor for coupling to a bus; an auxiliary capacitor having a lower capacitance than the output capacitor; and a circuit configured to couple the auxiliary capacitor in parallel with the output capacitor in a first state and to the input inductor in a second state; and a controller. If a line drop out (LDO) condition is detected on the bus, the controller sets the circuit in the second state and operate the first pair of power switches as a DC-DC boost converter under peak current control. If no LDO condition is detected on the bus, the controller sets the circuit in the first state and operate the totem-pole converter under average current control.

Abstract: A power supply includes an assembly comprising an inductor and a transformer. The inductor and the transformer are integrated to share a core of magnetic permeable material disposed in the assembly. The power supply further includes an unregulated power converter stage and a regulated power converter stage. The unregulated power converter stage implements use of the transformer. The regulated power converter stage implements use of the inductor. A combination of the regulated power converter stage and the unregulated power converter stage operative to collectively produce an output voltage to power a load.

Abstract: A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.

Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Abstract: A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

Abstract: A driver system includes a first half-bridge that generates a first load current at a first output node, a second half-bridge that generates a second load current at a second output node, a first voltage charging device coupled to the first output node, and a second voltage charging device coupled to the second output node. A method of detecting a short circuit condition in the driver system includes detecting a first charging time at which a first charging voltage of the first voltage charging device is charged to a first threshold voltage; detecting a second charging time at which a second charging voltage of the second voltage charging device is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold.

Abstract: A DBC substrate for power semiconductor devices includes a ceramic workpiece of a non-oxide ceramic having first and second opposing main sides, the ceramic workpiece having a thickness of 10 ?m or more measured between the first and second main sides, a copper-containing layer disposed over the first main side, the copper-containing layer having a thickness of 5 ?m or more, and an intermediate layer comprising Al2O3 disposed between the ceramic workpiece and the copper-containing layer.

Abstract: An apparatus such as a power converter includes a first flying capacitor, a second flying capacitor, etc., an inductor, and a network of switches. The network of switches controls conveyance of energy from the multiple flying capacitors to the inductor. The inductor converts the received energy into an output voltage to power a load. A magnitude of the respective voltage on each of the flying capacitors is substantially the same.

Abstract: A multi-level converter comprises one or more flying capacitors configured to operate at balanced voltages. The multi-level converter comprises a plurality of switching groups comprising pairs of switches operable to transfer energy to and from an inductor and the one or more flying capacitors for inverting an input voltage to an inverted output voltage. The multi-level converter comprises the inductor configured to operate according to an inductor frequency greater than a switching frequency used to control the plurality of switching groups.

Abstract: A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.