Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

Abstract: A power supply includes a first (main) power converter and a second (auxiliary) power converter disposed in parallel with the first power converter to produce an output voltage to power a dynamic load. The second power converter includes a primary inductive path magnetically coupled to a secondary inductive path. A controller controls a flow of first current through the primary inductive path of the second power converter to control flow of second current supplied by the secondary inductive path to the dynamic load. During steady state conditions, the first power converter produces the output voltage while the second power converter is deactivated. During transient load conditions, the second power converter provides current boost capability to maintain a magnitude of the output voltage within a desired range.

Abstract: A semiconductor device includes: a semiconductor die having a metal region; a substrate having a metal region; and a soldered joint between the metal region of the semiconductor die and the metal region of the substrate. One or more intermetallic phases are present throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the semiconductor die and the metal region of the substrate. The soldered joint has the same length-to-width aspect ratio as the semiconductor die.

Abstract: In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d1, a lower p-doped Group III nitride layer having a thickness d2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped AlxGa1-xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness d2 of the lower p-doped Group III nitride layer is larger than the thickness d1 of the upper p-doped GaN layer.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: An apparatus includes a controller that measures a first voltage across a first circuit path including a series connection of a first switch and a shunt resistor. The first voltage generated based on first current supplied from a first winding of a motor including multiple windings. Based on the magnitude of the first voltage, the controller determines an ON-resistance of the first switch. The ON-resistance can be used final office action any suitable purpose. For example, the controller can be configured to use the determined ON-resistance of the first switch to controller operation of a motor including the first winding. For example, the determined ON-resistance can be used as a basis to determine an amount of current through first switch and corresponding first winding of the motor.

Abstract: A driver device, a method for monitoring a driver device, and a power supply device are disclosed. The driver device includes a controller and a driver module. The driver module includes a voltage divider loop and a plurality of drivers. The voltage divider loop includes a pull-down resistor and one or more corresponding resistors connected to each of the plurality of drivers, where the pull-down resistor and the one or more corresponding resistors are coupled to a power supply via a first node, and the first node is coupled to the controller.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer and having a first contact pad at a first surface of the semiconductor device. An outer contact pad is positioned on a lower surface of the insulating layer. A vertical redistribution structure electrically couples the first contact pad to the outer contact pad. The first contact pad has a plurality of first via sites. A first subset of the first via sites is occupied by first vias and a second subset of the first via sites remains unoccupied and forms a first via-free zone, such that the first vias are non-uniformly distributed over the first contact pad.

Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.

Abstract: A voltage converter is provided. The voltage converter comprises a switching circuit that includes a first pair of switches and a second pair of switches. The voltage converter comprises a transformer having a magnetizing inductance and a leakage inductance that are a function of a windings ratio of the transformer. The voltage converter comprises a capacitor coupled to the transformer and the switching circuit. The voltage converter comprises a switch control circuit configured to generate a frequency for controlling the first pair of switches and the second pair of switches. The frequency is set of a value to control the pairs of switches so that a peak capacitor voltage of the capacitor is a factor of an output voltage of the voltage converter and the windings ratio of the transformer.

Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

Abstract: An inductor device may include a first electrically conductive path and a second electrically conductive path. The first electrically conductive path may extend from a first terminal of the inductor device to a second terminal of the inductor device. The second electrically conductive path may extend from a third terminal of the inductor device to a fourth terminal of the inductor device. The second electrically conductive path may be magnetically coupled to the first electrically conductive path. Each of the third terminal and the fourth terminal may be offset with respect to a virtual axis extending through the first terminal and the second terminal.

Abstract: A controller of a power converter including a first power stage and a second power stage receives an indication of an output voltage of the power converter, where the indication is measured at the primary side of the power converter. Based on the indication, a control related to an intermediate voltage of the power converter is performed.

Abstract: An apparatus comprises a solid state device and a switch in series with the solid state device. The apparatus comprises a leak detection component connected to the solid state device. The apparatus comprises a gate driver configured to drive a gate of the solid state device. The gate driver comprises test circuitry configured to apply a test voltage to the gate of the solid state device. The test voltage is less than a threshold voltage of the solid state device. The leak detection component is configured to detect a leakage of the solid state device.

Abstract: A voltage regulator module includes: power input and output terminals at a same side of the voltage regulator module; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor having a vertical conductor embedded in a magnetic core, the vertical conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip which electrically connects the second end of the vertical conductor to the power output terminal such that power is delivered to and from the voltage regulator module at the same side of the voltage regulator module. A method of producing the voltage regulator module and electronic assembly that includes the voltage regulator module are also described.

Abstract: A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

Abstract: According to one configuration, an inductor device includes a core fabricated from multiple different types of magnetically permeable material. The inductor device includes an electrically conductive path extending through the core. A magnetic permeability of the core varies in magnitude depending on a distance with respect to the electrically conductive path.

Abstract: A monolithically integrated bidirectional switch includes: an output terminal; a control terminal; a compound semiconductor substrate; a common drift region in the compound semiconductor substrate and in series between the input terminal and the output terminal; a first gate; and a second gate. The first gate is electrically connected to the control terminal and the second gate is electrically connected to the input terminal, or one of the first gate and the second gate is a normally-on gate and the other one of the first gate and the second gate is a normally-off gate. In either case, the monolithically integrated bidirectional switch is configured to conduct current in a single direction from the input terminal to the output terminal through the common drift region. A corresponding power electronic system that uses the monolithically integrated bidirectional switch is also described.

Abstract: A controller for a power converter includes an output terminal operative to output a modulation signal for controlling a phase current of the power converter. A modulator is operative to generate the modulation signal such that an output voltage of the power converter follows a first portion of a load-line when load current is above a first threshold, the first portion of the load-line having a first slope that determines a rate of change of the output voltage as a function of the load current. An interface is operative to receive a temperature signal. Circuitry is operative to change the first threshold in response to receipt of the temperature signal.