Abstract: According to some embodiments, an apparatus comprises a multi-level power converter configured to convert an input voltage to an output voltage, wherein the multi-level power converter comprises one or more switching groups, wherein a switching group of the one or more switching groups comprises a pair of switches and a flying capacitor, and a controller configured to determine a duty reference for the switching group, determine a duty correction factor for the switching group based upon a flying capacitor voltage error of the flying capacitor, determine a sign correction signal based on a flying capacitor ripple voltage, and determine a duty command for activating the pair of switches based on the duty reference, the duty correction factor, and the sign correction signal.

Abstract: The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.

Abstract: An electric switch-mode power converter comprises: a parameter predictor for predicting and updating at least one regulator parameter of a regulator controlling a switching device of the converter, a performance feedback signal generator for providing a performance feedback signal indicative of a performance of the conversion operation, wherein the parameter predictor is configured to predict an update of the regulator parameter based on the performance feedback signal and during update intervals, the intervals being during the power conversion operation and being separated by pauses without update.

Abstract: Disclosed is a method and a control circuit. The method includes operating a buffer circuit in a first operating mode or a second operating mode. Operating the buffer circuit in the first operating mode includes buffering, by a first capacitor of the buffer circuit, power provided by a power source and received by a load. Operating the buffer circuit in the second operating mode includes connecting a second capacitor in series with the first capacitor to form a capacitor series circuit, supplying power to the load by the capacitor series circuit, and regulating a first voltage across the capacitor series circuit. Regulating the first voltage includes transferring charge from the first capacitor to the second capacitor.

Abstract: An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.

Abstract: This application relates to semiconductor die including: a transistor device formed in an active area of a semiconductor body and having a channel region, a gate region, and a field electrode region, the gate region arranged laterally aside the channel region and having a gate electrode for controlling a current flow in the channel region, the gate electrode formed in a gate trench extending into the semiconductor body; and an additional device formed in an additional device area of the semiconductor body. A recess extends into the semiconductor body in the additional device area, and a semiconductor material is arranged in the recess in which the additional device is formed.

Abstract: An apparatus includes a controller a current mode controller that produces an output voltage by supplying output current from at least one power supply phase of a power supply to power a load. The controller produces an error current signal based on a difference between a magnitude of the output current supplied from the power supply to a load and a phase current setpoint. Based on a magnitude of the error current signal, control a pulse width setting of a pulse width modulation signal controlling the at least one power supply phase. The controller varies a leading edge and a falling edge of a pulse width ON-time of the pulse width modulation signal over each of multiple control cycles depending on variations in the magnitude of the pulse width setting.

Abstract: A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface.

Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

Abstract: A gate driver system includes a transistor configured to be driven between switching states, the transistor including a control terminal controlled by a control voltage that has a maximum rated limit; and a gate driver coupled to the control terminal by a turn-on current path, the gate driver being configured to control the control voltage in order to drive the transistor between the switching states. The turn-on current path includes a resistor and a Zener diode connected in series, with an anode of the Zener diode connected to the control terminal and a cathode of the Zener diode connected to the resistor. The turn-on current path is configured to provide an on-current to increase the control voltage above a switching threshold. While the transistor is turned on, the Zener diode is configured to limit the control voltage to a voltage level limit that is less than the maximum rated limit.

Abstract: A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

Abstract: A semiconductor device includes type IV semiconductor base substrate, first and second device areas that are electrically isolated from one another, a first region of type III-V semiconductor material formed over the first device area, a second region of type III-V semiconductor material formed over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material, a first high-electron mobility transistor integrally formed in the first region, and a second high-electron mobility transistor integrally formed in the second region. The first and second high-electron mobility transistors are connected in series. A source terminal of the first high-electron mobility transistor is electrically connected to the first device area. The first device area is electrically isolated from a subjacent intrinsically doped region of the base substrate by a first two-way voltage blocking device.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: This disclosure includes novel ways of implementing a power supply that powers a load. A main battery source produces a main battery voltage; each of multiple auxiliary battery sources in a set produces a respective auxiliary battery voltage. A controller initially sets a battery supply voltage to the main battery voltage, the main battery voltage is supplied to a power converter. The controller then monitors a magnitude of the battery supply voltage and adjusts the battery supply voltage supplied to the power converter based on a comparison of the magnitude of the battery supply voltage with respect to a threshold level. The adjusted battery supply voltage is provided from a serial connection of the main battery source and a first auxiliary battery source in the set.

Abstract: A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.

Abstract: A method for driving a power transistor includes comparing a measurement signal that is representative of a load current to a comparator threshold that corresponds to an overcurrent threshold; generating a first fault signal when the measurement signal exceeds the comparator threshold for a first time interval; generating a second fault signal when the measurement signal exceeds the comparator threshold for a second time interval that is greater than the first time interval; regulating a control voltage provided to the control terminal of the transistor to turn off the transistor in response to the second fault signal; and in response to the first fault signal, adjusting the control voltage to an adjusted voltage level in order to limit the load current to a reduced current level that is preconfigured to be greater than the overcurrent threshold. The adjusted voltage level is sufficient to maintain the power transistor in an on-state.

Abstract: A method for operating a power converter arrangement and a corresponding controller are disclosed. The method includes operating the power converter arrangement in a surge mode, when a DC link voltage of the power converter arrangement reaches a first voltage threshold. The power converter includes a first power converter having an input and an output; a second power converter having an input and an output; and a DC link capacitor circuit coupled to the output of the first power converter and the input of the second power converter and providing the DC link voltage. Operating the power converter arrangement in the surge mode includes: deactivating the second power converter; and operating, at least temporarily, the first power converter in a reverse mode to transfer energy from the DC link capacitor circuit to the input of the first power converter.

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.

Abstract: A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.

Abstract: In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.