Abstract: A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.

Abstract: Disclosed is a method and apparatus. The method includes detecting an operating state of a current source converter that comprises a current source rectifier (1), a current source inverter (2), and an inductor circuit (3) connected between an output (p, n) of the current source rectifier (1) and an input (q, r) of the current source inverter (2); and dependent on the detected operating state, operating the current source converter in a first operating mode or a second operating mode. Operating the current source converter in the first operating mode comprises operating the current source rectifier (1) in a 2/3 mode and operating the current source inverter in a 3/3 mode, and operating the current source converter in the second operating mode comprises operating the current source inverter (2) in the 2/3 mode and operating the current source rectifier in the 3/3 mode.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A device includes: first and second electronic sides; an isolation barrier galvanically isolating the electronic sides from one another and including a signal coupler configured to enable signaling between the electronic sides over the isolation barrier via electromagnetic coupling; and transceiver circuitry included in both electronic sides and configured to implement, based on a frequency response profile of the isolation barrier, full-duplex communication between the electronic sides using the same signal coupler.

Abstract: A vehicle assembly system includes a vehicle chassis of a vehicle; at least one object sensor mounted to the vehicle chassis, where the at least one object sensor generates sensor data based on at least one detected object; a vehicle controller mounted to the vehicle chassis and configured to receive the sensor data from the at least one object sensor, where, during assembly, the vehicle controller is configured with production control software that enables the vehicle controller to generate production object data from the sensor data, monitor for a safety event based on the production object data, and generate a safety event signal in response to detecting the safety event; and a safety controller configured to receive the safety event signal from the vehicle controller and alter a movement of a surveilled machine corresponding to the safety event.

Abstract: A current mode controller includes: an error amplifier configured to generate an error signal that corresponds to the difference between a reference voltage and a voltage indicative of an output voltage of a power converter; a first current measurement circuit configured to measure current flowing in a high-side switch device of the power converter; a second current measurement circuit configured to measure current flowing in a low-side switch device of the power converter; a comparator configured to indicate when a voltage derived by the first current measurement circuit exceeds the error signal in a peak current control mode, and when a voltage derived by the second current measurement circuit drops below the error signal in a valley current control mode; and circuitry configured to configure the comparator in either the peak current control mode or the valley current control mode for each switching cycle of the power converter.

Abstract: A power module for driving a motor includes: a positive bus input voltage terminal; a phase terminal for each motor phase; an inverter including a half bridge for each motor phase, each half bridge including a high-side power switch electrically coupled between the positive bus input voltage terminal and respective phase terminal, and a low-side power switch electrically coupled between the respective phase terminal and ground; a first driver circuit for driving a gate terminal of each power switch; a protection switch electrically coupled in series between the positive bus input voltage terminal and each high-side power switch, and having a greater short-circuit withstand time and a lower short-circuit current level compared to each inverter power switch; and a second driver circuit for turning on the protection switch during normal operation and turning off the protection switch in response to a detected short circuit condition.

Abstract: A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer and a second barrier layer, wherein in a central portion of the device the second barrier layer is the only layer that is disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, wherein the first and second barrier layers are each III-V semiconductor alloys, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.

Abstract: An apparatus such as a power supply includes management hardware. The management hardware monitors operation of multiple power converter phases coupled in parallel to produce an output voltage. Based on the monitored operation, the management hardware determines a status of a series circuit path connecting windings of the multiple power converter phases. The management hardware produces status information indicating the status of the series circuit path.

Abstract: A power stage includes: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.

Abstract: A power conversion circuit includes a high-side switch and a low-side switch connected in series with one another and configured to control a load current flowing through a load, wherein at least one of the high-side switch and the low-side switch comprise a power relay circuit for switching the load current, and wherein the power relay circuit comprises a micro-electro-mechanical system switch, and a semiconductor power switch, wherein the MEMS switch and the semiconductor power switch are connected in series with the load.

Abstract: In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d1, a lower p-doped Group III nitride layer having a thickness d2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped AlxGa1-xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness d2 of the lower p-doped Group III nitride layer is larger than the thickness d1 of the upper p-doped GaN layer.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

Abstract: An apparatus includes a controller that measures a first voltage across a first circuit path including a series connection of a first switch and a shunt resistor. The first voltage generated based on first current supplied from a first winding of a motor including multiple windings. Based on the magnitude of the first voltage, the controller determines an ON-resistance of the first switch. The ON-resistance can be used final office action any suitable purpose. For example, the controller can be configured to use the determined ON-resistance of the first switch to controller operation of a motor including the first winding. For example, the determined ON-resistance can be used as a basis to determine an amount of current through first switch and corresponding first winding of the motor.

Abstract: A power supply includes a first (main) power converter and a second (auxiliary) power converter disposed in parallel with the first power converter to produce an output voltage to power a dynamic load. The second power converter includes a primary inductive path magnetically coupled to a secondary inductive path. A controller controls a flow of first current through the primary inductive path of the second power converter to control flow of second current supplied by the secondary inductive path to the dynamic load. During steady state conditions, the first power converter produces the output voltage while the second power converter is deactivated. During transient load conditions, the second power converter provides current boost capability to maintain a magnitude of the output voltage within a desired range.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: A semiconductor device includes: a semiconductor die having a metal region; a substrate having a metal region; and a soldered joint between the metal region of the semiconductor die and the metal region of the substrate. One or more intermetallic phases are present throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the semiconductor die and the metal region of the substrate. The soldered joint has the same length-to-width aspect ratio as the semiconductor die.

Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.

Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer and having a first contact pad at a first surface of the semiconductor device. An outer contact pad is positioned on a lower surface of the insulating layer. A vertical redistribution structure electrically couples the first contact pad to the outer contact pad. The first contact pad has a plurality of first via sites. A first subset of the first via sites is occupied by first vias and a second subset of the first via sites remains unoccupied and forms a first via-free zone, such that the first vias are non-uniformly distributed over the first contact pad.