Patents Assigned to Infineon Technologies Austria AG
  • Patent number: 12289044
    Abstract: A power converter includes: a solid-state transformer having a DC input and isolated DC outputs; a half bridge converter stage for each isolated DC output of the solid-state transformer, wherein an input of each half bridge converter stage is connected to the corresponding isolated DC output and an output of the half bridge converter stages are electrically connected in a cascade configuration; an output inductor shared by the half bridge converter stages and configured to deliver an output current; and a controller configured to implement phase shift control of the half bridge converter stages relative to one another, based on the number of half bridge converter stages and an output voltage of the power converter being regulated, such that each half bridge converter stage processes the full output current but only a fraction of the output voltage. Methods of controlling the power converter are also described.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: April 29, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Manuel Escudero Rodriguez, Matteo-Alessandro Kutschak, Alessandro Pevere, David Meneses Herrera
  • Patent number: 12287658
    Abstract: A signal adjustor receives a first signal such as feedback associated with generation of an output voltage. The output voltage is regulated based on a selected setpoint reference voltage. The signal adjustor maps a magnitude of the selected setpoint reference voltage to a first set of signal adjustment information amongst multiple sets of signal adjustment information. The signal adjustor then applies the first signal adjustment information to the first signal to produce a second signal.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: April 29, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Aviral Srivastava, Luca Petruzzi, Benjamim Tang
  • Patent number: 12283563
    Abstract: A semiconductor module includes a substrate, a semiconductor die arranged on the substrate, at least one first bond wire loop, wherein both ends of the at least one first bond wire loop are arranged on and coupled to a first electrode of the semiconductor die, and a molded body encapsulating the semiconductor die, wherein a top portion of the at least one first bond wire loop is exposed from a first side of the molded body.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: April 22, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Ivan Nikitin, Peter Luniewski
  • Patent number: 12283621
    Abstract: A semiconductor device includes a transistor that has: a drift region of a first conductivity type in a semiconductor substrate having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a plurality of dummy mesas, the plurality of trenches including an active trench and a plurality of dummy trenches arranged in a row; a gate electrode arranged in the active trench; and a source region of the first conductivity type in the first mesa. The first mesa is arranged adjacent to the active trench. A dummy mesa is arranged between each adjacent pair of the dummy trenches. The dummy mesas do not carry load current during an on-state of the transistor.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: April 22, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Caspar Leendertz, Markus Beninger-Bina, Matteo Dainese, Alice Pei-Shan Leendertz, Christian Philipp Sandow
  • Patent number: 12278019
    Abstract: A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: April 15, 2025
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Jens Repp
  • Patent number: 12273098
    Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: April 8, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Christian Fachmann, Matteo-Alessandro Kutschak, Otto Wiedenbauer, Winfried Kaindl, Hans Weber
  • Patent number: 12264867
    Abstract: A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a housing frame provided for pre-assembly in the cryostat. A pin insert is arranged in the housing frame. The pin insert includes a base plate and contact pins. The contact pins are arranged in an array. A housing cover has a receptacle for the substrate. The housing cover, when assembled with the housing frame, exerts a compressive force on a front side of the substrate by which a rear side of the substrate is pressed onto the contact pins.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 1, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Günther Lohmann, Ralf Otremba, Josef Höglauer, Clemens Rössler, Silke Katharina Auchter
  • Patent number: 12261547
    Abstract: A method for operating a power converter and a control circuit are disclosed. The method includes, in a power converter including an input, a converter stage, a first switch connected between the input and the converter stage, a second switch connected between input nodes of the converter stage, and an output capacitor connected between output nodes of the converter stage: detecting an operating state of the power converter; and operating the power converter in a first operating mode when the power converter is in a first operating state. Operating the power converter in the first operating mode includes regulating an input current received at the input by a switched-mode operation of the first and second electronic switches.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: March 25, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerald Deboy, Matthias J. Kasper
  • Patent number: 12261542
    Abstract: A dual active bridge circuit includes a primary side circuit including first high-side transistor and a first low-side transistor electrically coupled at a first node, and an energy transfer inductor coupled to the first node and configured to provide an inductor current based on a voltage differential across the energy transfer inductor. A secondary side circuit includes a second high-side transistor and a second low-side transistor electrically coupled at a second node. A transformer is configured to transfer energy from the primary side circuit to the secondary side circuit based on the inductor current. A controller is configured to drive each of the transistors between respective switching states with a same duty cycle to control the voltage differential across the energy transfer inductor. The same duty cycle is less than 50% such that all of the transistors are simultaneously off for a predetermined interval.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: March 25, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Yi Zhang, Cheng Zhang, Sanbao Shi
  • Patent number: 12261535
    Abstract: An isolated power converter includes: a transformer having primary winding and first and second auxiliary windings on the primary side; a converter stage configured to convert a DC input for driving the primary winding and having a resonant capacitor electrically connected to the primary winding; a controller configured to control switching of the converter stage; and a voltage supply circuit configured to select a first voltage as a supply voltage for the controller if a voltage proportional to a secondary side voltage of the transformer is at a first level or select a second voltage as the supply voltage if the voltage proportional to the secondary side voltage is at a second level greater than the first level. The first voltage corresponds to a summation of voltages across the first auxiliary winding and the resonant capacitor. The second voltage corresponds to a voltage across the second auxiliary winding.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: March 25, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Allan Saliva, Roderick Domingo
  • Patent number: 12261144
    Abstract: A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.
    Type: Grant
    Filed: October 11, 2023
    Date of Patent: March 25, 2025
    Assignee: Infineon Technologies Austria AG
    Inventor: Alexander Heinrich
  • Patent number: 12255162
    Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface and at least one transistor device structure, a source pad and a gate pad arranged on the first major surface, a drain pad and at least one further contact pad coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 18, 2025
    Assignee: Infineon Technologies Austria AG
    Inventor: Carsten von Koblinski
  • Patent number: 12243673
    Abstract: An inductor device includes a first face, a first inductive path, and magnetic permeable material. The first face couples the inductor device to a circuit board. The first inductive path extends between a first terminal on the first face to a second terminal on the first face. A portion of the first inductive path is exposed on a second face of the inductor device. The second face is disposed opposite the first face. The second face supports dissipation of heat conveyed by the first inductive path from the first face to the second face. The magnetic permeable material is disposed between the first face and the second face and carries magnetic flux associated with the first inductive path.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: March 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Danny Clavette, Wenkang Huang
  • Patent number: 12244240
    Abstract: A controller for a power converter, a corresponding power converter and a corresponding method are provided. The controller for a power converter includes a rectifier configured to receive an alternating current input signal and output rectified half waves, an output capacitor and a current control device is coupled between the rectifier and the output capacitor. After reaching a first maximum voltage, power flowing is gradually reduced, and later the current provided to the output capacitor is gradually ramped up.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: March 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Feldtkeller
  • Patent number: 12244173
    Abstract: This disclosure includes novel ways of implementing a power supply that powers a load. More specifically, a power supply includes a bidirectional power converter and a controller. The controller monitors a magnitude of an input voltage supplied from an input voltage source to a load. Based on a magnitude of the input voltage, the controller switches between a first mode of operating the bidirectional power converter to charge an energy storage resource using (a portion of power provided by) the input voltage and a second mode of producing a backup voltage from the energy storage resource to power the load as a substitute to the input voltage such as when the input voltage is below a threshold value.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: March 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Matthias J. Kasper, Luca Peluso, Gerald Deboy
  • Patent number: 12237242
    Abstract: A semiconductor device package comprises an electrically conductive carrier, a semiconductor die disposed on the carrier, an encapsulant encapsulating part of the carrier and the semiconductor die, an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure comprises a glass transition temperature in a range between ?40° C. to 150° C.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: February 25, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Mayer, Edward Fuergut, Alexander Roth, Karina Rott
  • Patent number: 12230706
    Abstract: In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: February 18, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Ingmar Neumann, Michael Hutzler, David Laforet, Roland Moennich, Thomas Ralf Siemieniec
  • Patent number: 12232302
    Abstract: A method of manufacturing an electronic module assembly includes forming the electronic module assembly, wherein the electronic module assembly comprises a plurality of internal exposed surfaces, a plurality of external exposed surfaces, at least one internal cavity, and an internal heat source configured to generate heat internally within the electronic module assembly; dipping the electronic module assembly into a thermally conductive material to coat the plurality of internal exposed surfaces and the plurality of external exposed surfaces and to at least partially fill the at least one internal cavity; and curing the thermally conductive material formed on the plurality of internal exposed surfaces and the plurality of external exposed surfaces and filled within the at least one internal cavity to form a thermally conductive layer, wherein the thermally conductive layer is formed as a one-piece integral member.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: February 18, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Chee Yang Ng, Swee Kah Lee
  • Patent number: 12230700
    Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: February 18, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Simone Lavanga, Nicholas Dellas, Gerhard Prechtl, Luca Sayadi
  • Patent number: 12231860
    Abstract: A method for designing a loudspeaker excursion estimator comprises measuring an excursion-related parameter for a loudspeaker, for each of a plurality of loudspeaker input signal levels and each of a plurality of loudspeaker input signal frequencies. The method further comprises, for each of the loudspeaker input signal frequencies and based on the measured excursion-related parameters, identifying a respective loudspeaker input signal level corresponding to a target maximum excursion-related parameter value. The method further comprises determining a filter response, based on the identified loudspeaker input signal levels and their respective loudspeaker input signal frequencies, and implementing a filter, based on the calculated filter response, for generating an excursion estimation based on loudspeaker input signal levels.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: February 18, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Holm Hansen, Pawan Garg, Jun Honda, Niels Petersen