Patents Assigned to Infineon Technologies Austria AG
  • Patent number: 11329636
    Abstract: A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Giacomo Cascio, Salvatore Angelo Della Fortuna
  • Patent number: 11329646
    Abstract: Transformer-driven power switch devices are provided for switching high currents. These devices include power switches, such as Gallium Nitride (GaN) transistors. Transformers are used to transfer both control timing and power for controlling the power switches. These transformers may be coreless, such that they may be integrated within a silicon die. Rectifiers, pulldown control circuitry, and related are preferably integrated in the same die as a power switch, e.g., in a GaN die, such that a transformer-driven switch device is entirely comprised on a silicon die and a GaN die, and does not necessarily require a (large) cored transformer, auxiliary power supplies, or level shifting circuitry.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Kennith Kin Leong, Thomas Ferianz
  • Patent number: 11329126
    Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Tilke, Hans Weber, Christian Fachmann, Roman Knoefler, Gabor Mezoesi, Manfred Pippan, Thomas Rupp, Michael Treu, Armin Willmeroth
  • Patent number: 11323099
    Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: May 3, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 11316020
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending form the base to the first major surface, and a field plate arranged in the trench and an enclosed cavity in the trench. The enclosed cavity is defined by insulating material and is laterally positioned between a side wall of the field plate and the side wall of the trench.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sylvain Leomant, Georg Ehrentraut, Maximilian Roesch
  • Patent number: 11316043
    Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
  • Patent number: 11302610
    Abstract: In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Dinkel, Petteri Palm, Eung San Cho, Josef Hoeglauer, Ralf Otremba, Fabian Schnoy
  • Patent number: 11303222
    Abstract: A multiphase inverter apparatus includes an insulating substrate, a plurality of half bridge circuits and a phase output lead for each half bridge circuit. The substrate includes a conductive redistribution structure on a first surface and having at least one low voltage bus and at least one high voltage bus. Each half-bridge circuit is electrically coupled between a low voltage bus and a high voltage bus and includes: a packaged low side switch; a packaged high side switch; and a phase output electrically coupled with the respective phase output lead. The packaged low side and high side switches are arranged on the first surface of the substrate. The phase output lead is arranged on and electrically coupled to the packaged low side and high side switches such that the low side and high side switches are arranged vertically between the phase output lead and the first surface of the substrate.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Tomasz Naeve, Elvir Kahrimanovic, Petteri Palm
  • Patent number: 11303207
    Abstract: A method of controlling a power converter includes: generating a modulation signal for controlling a phase current of a power stage of the power converter such that an output voltage of the power converter follows a load line having a slope that determines a rate of change of the output voltage as a function of load current; receiving a signal which indicates a target voltage regulation setpoint; and overriding the load line when the signal is active, such that the output voltage follows the target voltage regulation setpoint instead of the load line when the signal is present at the interface.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Jayadevan Radhakrishnan, Danny Clavette
  • Patent number: 11296213
    Abstract: According to an embodiment of a power semiconductor device, the device includes: a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. An average lateral spacing between adjacent ones of the second trenches is greater than an average lateral spacing between adjacent ones of the first trenches. Additional power semiconductor device embodiments are described herein, as are corresponding methods of production.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Christian Philipp Sandow, Wolfgang Roesner, Matteo Dainese
  • Patent number: 11296218
    Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces, an active area including active transistor cells, and an edge termination region laterally surrounding the active area. Each active transistor cell includes a mesa and a columnar trench having a field plate. The edge termination region includes inactive cells each including a columnar termination trench having a field plate, and a termination mesa including a drift region of a first conductivity type. The edge termination region includes a transition region laterally surrounding the active region and an outer termination region laterally surrounding the transition region. In the transition region, the termination mesa includes a body region of a second conductivity type arranged on the drift region. In the outer termination region, the drift region extends to the first surface. A buried doped region of the edge termination region is positioned in the transition and outer termination regions.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: April 5, 2022
    Assignees: Infineon Technologies Austria AG, Infineon Technologies Americas Corp.
    Inventors: Ralf Siemieniec, Adam Amali, Michael Hutzler, Laszlo Juhasz, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 11289436
    Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
  • Patent number: 11289595
    Abstract: A power semiconductor device includes: a semiconductor body having a front side surface and a drift region having first conductivity type dopants; and an edge termination region that includes a part of the drift region and a first semiconductor region extending along the front side surface. The first semiconductor region includes dopants of both conductivity types and forms a continuous pn-junction with the drift region. An integrated vertical dopant concentration of the second conductivity type dopants is higher than an integrated vertical dopant concentration of the first conductivity type dopants within the first semiconductor region.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: March 29, 2022
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Frank Dieter Pfirsch
  • Patent number: 11289597
    Abstract: A transistor device is enclosed. The transistor device includes: a semiconductor body; a plurality of drift regions of a first doping type; a plurality of compensation regions of a second doping type adjoining the drift regions; and a plurality of transistor cells each including a body region adjoining a respective one of the plurality of drift regions, a source region adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. The source regions of the plurality of transistor cells are connected to a source node, the body regions of the plurality of transistor cells are separated from the plurality of compensation regions in the semiconductor body, and the plurality of compensation regions are ohmically connected to the source node.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: March 29, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Björn Fischer, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 11289593
    Abstract: A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 29, 2022
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Gilberto Curatola, Martin Huber, Ingo Daumiller
  • Patent number: 11282757
    Abstract: A semiconductor device includes a semiconductor substrate and a metal structure in electrical contact with the semiconductor substrate. The metal structure has copper as a main component. An encapsulation layer includes a matrix material and a releasable copper corrosion inhibitor dispersed in the matrix material. The matrix material of the encapsulation layer at least partially covers the metal structure. A protective layer is at least partially on and in contact with a surface of the metal structure, and disposed between the metal structure and the encapsulation layer.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 22, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sabine Reither, Guenter Fafilek, Silvia Larisegger
  • Patent number: 11276680
    Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Pedone, Hans-Joachim Schulze, Rolf Gerlach, Christian Kasztelan, Anton Mauder, Hubert Rothleitner, Wolfgang Scholz, Philipp Seng, Peter Tuerkes
  • Patent number: 11276624
    Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
  • Patent number: 11270948
    Abstract: In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 8, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Patent number: 11271100
    Abstract: First and second trenches are provided in a semiconductor body. A mesa dividing structure is provided between the first and second trenches and comprises non-semiconductor material. A first semiconductor mesa is provided between the first trench and the non-semiconductor material of the mesa dividing structure. The first semiconductor mesa includes emitter, body and drift regions. The first and second trenches are formed by a masked etching technique with a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width that is less than the minimum trench separation distance.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 8, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Alim Karmous