Abstract: A semiconductor device package comprises an electrically conductive carrier, a semiconductor die disposed on the carrier, an encapsulant encapsulating part of the carrier and the semiconductor die, an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure comprises a glass transition temperature in a range between ?40° C. to 150° C.

Abstract: A method of manufacturing an electronic module assembly includes forming the electronic module assembly, wherein the electronic module assembly comprises a plurality of internal exposed surfaces, a plurality of external exposed surfaces, at least one internal cavity, and an internal heat source configured to generate heat internally within the electronic module assembly; dipping the electronic module assembly into a thermally conductive material to coat the plurality of internal exposed surfaces and the plurality of external exposed surfaces and to at least partially fill the at least one internal cavity; and curing the thermally conductive material formed on the plurality of internal exposed surfaces and the plurality of external exposed surfaces and filled within the at least one internal cavity to form a thermally conductive layer, wherein the thermally conductive layer is formed as a one-piece integral member.

Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

Abstract: In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.

Abstract: A method for designing a loudspeaker excursion estimator comprises measuring an excursion-related parameter for a loudspeaker, for each of a plurality of loudspeaker input signal levels and each of a plurality of loudspeaker input signal frequencies. The method further comprises, for each of the loudspeaker input signal frequencies and based on the measured excursion-related parameters, identifying a respective loudspeaker input signal level corresponding to a target maximum excursion-related parameter value. The method further comprises determining a filter response, based on the identified loudspeaker input signal levels and their respective loudspeaker input signal frequencies, and implementing a filter, based on the calculated filter response, for generating an excursion estimation based on loudspeaker input signal levels.

Abstract: A semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. The IGBT includes a gate trench including a gate electrode and a gate dielectric, a source region, an emitter electrode, a drift region, and a second contact groove.

Abstract: In an embodiment, a leadframe includes a first electrically conductive part and a second electrically conductive part, each having an outer surface arranged to provide substantially coplanar outer contact areas having a footprint and an inner surface opposing the outer surface, the first part being spaced apart from the second part by a gap, a first recess arranged in the inner surface of the first part, a second recess arranged in the inner surface of the second part, and a first electrically conductive insert that is arranged in, and extends between, the first recess and the second recess and bridges the gap between the first part and the second part.

Abstract: An apparatus comprises a power source connected to a buffer capacitor. The apparatus comprises a first switch connected between the buffer capacitor and a driven switch. The buffer capacitor is charged by the power source when the first switch is turned off. The apparatus comprises a comparator. The comparator monitors the charging of the buffer capacitor. In response to the buffer capacitor reaching a threshold amount of charge, the comparator turns on the first switch to initiate a charge redistribution of charge from the buffer capacitor to the driven switch.

Abstract: An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heat sink.

Abstract: An integrated circuit with galvanic isolation is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element configured to separate a first isolation domain from a second isolation domain and a first channel configured to transmit—in a first mode of operation and across the first isolation element—a logic signal from a first input in the first isolation domain to a first output in the second isolation domain. The first channel is further configured to transmit—in a second mode of operation and across the first isolation element—a serial data stream from the first input to a logic circuit in the second isolation domain, wherein the logic circuit is configured to receive—in the second mode of operation—the serial data stream and to store configuration information included in the serial data stream in a memory.

Abstract: A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

Abstract: A power supply includes a controller. The controller controls switching of a first switch and a second switch in a power supply to regulate conveyance of energy from a primary winding of a transformer to a secondary winding of the transformer to generate an output voltage. To control generation of the output voltage, the controller receives a first signal generated at a first node coupling the first switch and the second switch. As discussed herein, the controller controls activation of the first switch to an ON state depending on a magnitude of the first signal. This disclosure provides improved reliability of power supply components (such as one or more switches) because such components are no longer stressed (or overstressed) due to body diode cross conduction.

Abstract: A semiconductor package includes a first semiconductor die, a first group of leads that each comprise an interior end, and an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interior ends of the leads from the first group, wherein a gap is disposed between outer sidewalls of two immediately adjacent ones of the leads from the first group, wherein the first semiconductor die is mounted on the first group of leads such that a lower surface of the first semiconductor die faces and overlaps with each of the leads from the first group, and wherein the lower surface of the first semiconductor die extends across the gap between outer sidewalls of two immediately adjacent ones of the leads from the first group.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.

Abstract: A method of manufacturing a package includes mounting an electronic component on an electrically conductive carrier, encapsulating part of the carrier and the electronic component by an encapsulant, covering an exposed surface portion of the carrier with an electrically insulating and thermally conductive interface structure, and covering at least part of the interface structure by a protection cap.

Abstract: Digital-to-analog converter circuitry includes sequence of multiple current drive modules. The sequence may include a first current drive module and a second current drive module of a digital-to-analog converter. The first current drive module is switchable between: i) a first mode of producing a first reference current that is mirrored by a second current drive module coupled to the first current drive module; and ii) a second mode of mirroring a second reference current that is produced by the second current drive module or a third current drive module coupled to the first current drive module.

Abstract: A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: Disclosed is a method and apparatus. The method includes detecting an operating state of a current source converter that comprises a current source rectifier (1), a current source inverter (2), and an inductor circuit (3) connected between an output (p, n) of the current source rectifier (1) and an input (q, r) of the current source inverter (2); and dependent on the detected operating state, operating the current source converter in a first operating mode or a second operating mode. Operating the current source converter in the first operating mode comprises operating the current source rectifier (1) in a 2/3 mode and operating the current source inverter in a 3/3 mode, and operating the current source converter in the second operating mode comprises operating the current source inverter (2) in the 2/3 mode and operating the current source rectifier in the 3/3 mode.