Patents Assigned to Infineon Technologies Austria AG
  • Patent number: 11929679
    Abstract: An apparatus includes a controller a current mode controller that produces an output voltage by supplying output current from at least one power supply phase of a power supply to power a load. The controller produces an error current signal based on a difference between a magnitude of the output current supplied from the power supply to a load and a phase current setpoint. Based on a magnitude of the error current signal, control a pulse width setting of a pulse width modulation signal controlling the at least one power supply phase. The controller varies a leading edge and a falling edge of a pulse width ON-time of the pulse width modulation signal over each of multiple control cycles depending on variations in the magnitude of the pulse width setting.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Venkat Sreenivas, Bikiran Goswami, Benjamim Tang, Todd Bellefeuille, Kang Peng
  • Patent number: 11929395
    Abstract: A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Ingo Muri, Maximilian Treiber, Daniel Tutuc
  • Patent number: 11929430
    Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11923832
    Abstract: A gate driver system includes a transistor configured to be driven between switching states, the transistor including a control terminal controlled by a control voltage that has a maximum rated limit; and a gate driver coupled to the control terminal by a turn-on current path, the gate driver being configured to control the control voltage in order to drive the transistor between the switching states. The turn-on current path includes a resistor and a Zener diode connected in series, with an anode of the Zener diode connected to the control terminal and a cathode of the Zener diode connected to the resistor. The turn-on current path is configured to provide an on-current to increase the control voltage above a switching threshold. While the transistor is turned on, the Zener diode is configured to limit the control voltage to a voltage level limit that is less than the maximum rated limit.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: March 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Kuiwei Xu, Weiwei Cao
  • Patent number: 11923448
    Abstract: A semiconductor device includes type IV semiconductor base substrate, first and second device areas that are electrically isolated from one another, a first region of type III-V semiconductor material formed over the first device area, a second region of type III-V semiconductor material formed over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material, a first high-electron mobility transistor integrally formed in the first region, and a second high-electron mobility transistor integrally formed in the second region. The first and second high-electron mobility transistors are connected in series. A source terminal of the first high-electron mobility transistor is electrically connected to the first device area. The first device area is electrically isolated from a subjacent intrinsically doped region of the base substrate by a first two-way voltage blocking device.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Hyeongnam Kim, Jens Ulrich Heinle, Mohamed Imam, Bhargav Pandya, Ramakrishna Tadikonda, Manuel Vorwerk
  • Patent number: 11923276
    Abstract: A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: March 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Michael Treu
  • Patent number: 11923839
    Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Dirk Priefert, Matteo Albertini, Remigiusz Viktor Boguszewicz
  • Patent number: 11916428
    Abstract: This disclosure includes novel ways of implementing a power supply that powers a load. A main battery source produces a main battery voltage; each of multiple auxiliary battery sources in a set produces a respective auxiliary battery voltage. A controller initially sets a battery supply voltage to the main battery voltage, the main battery voltage is supplied to a power converter. The controller then monitors a magnitude of the battery supply voltage and adjusts the battery supply voltage supplied to the power converter based on a comparison of the magnitude of the battery supply voltage with respect to a threshold level. The adjusted battery supply voltage is provided from a serial connection of the main battery source and a first auxiliary battery source in the set.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Luca Peluso, Matthias J. Kasper
  • Patent number: 11916068
    Abstract: A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Hyeongnam Kim, Mohamed Imam
  • Patent number: 11916544
    Abstract: A method for driving a power transistor includes comparing a measurement signal that is representative of a load current to a comparator threshold that corresponds to an overcurrent threshold; generating a first fault signal when the measurement signal exceeds the comparator threshold for a first time interval; generating a second fault signal when the measurement signal exceeds the comparator threshold for a second time interval that is greater than the first time interval; regulating a control voltage provided to the control terminal of the transistor to turn off the transistor in response to the second fault signal; and in response to the first fault signal, adjusting the control voltage to an adjusted voltage level in order to limit the load current to a reduced current level that is preconfigured to be greater than the overcurrent threshold. The adjusted voltage level is sufficient to maintain the power transistor in an on-state.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Sergio Morini, Andrea Lampredi, Salviano Marino, Daniele Miatton
  • Patent number: 11916472
    Abstract: A method for operating a power converter arrangement and a corresponding controller are disclosed. The method includes operating the power converter arrangement in a surge mode, when a DC link voltage of the power converter arrangement reaches a first voltage threshold. The power converter includes a first power converter having an input and an output; a second power converter having an input and an output; and a DC link capacitor circuit coupled to the output of the first power converter and the input of the second power converter and providing the DC link voltage. Operating the power converter arrangement in the surge mode includes: deactivating the second power converter; and operating, at least temporarily, the first power converter in a reverse mode to transfer energy from the DC link capacitor circuit to the input of the first power converter.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerald Deboy
  • Patent number: 11908904
    Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Sylvain Leomant, Thomas Feil, Yulia Polak, Maximilian Roesch
  • Patent number: 11908928
    Abstract: A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies Austria AG
    Inventor: Ling Ma
  • Patent number: 11901355
    Abstract: In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 13, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Noebauer, Florian Gasser
  • Patent number: 11901888
    Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Vedant Sadashiv Chendake, Giuseppe Bernacchia, Pablo Yelamos Ruiz
  • Patent number: 11901802
    Abstract: A control circuit, a power supply including a control circuit, and a method are disclosed. The control circuit is configured to activate a second output capacitor connected in parallel with a first output capacitor of a power supply when the power supply is in a normal operating mode, and deactivate the second output capacitor when the power supply is in a standby mode.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 13, 2024
    Assignee: Infineon Technologies Austria AG
    Inventor: Sang Ho Jang
  • Publication number: 20240047096
    Abstract: A transformer includes a winding configured to carry a current. The winding includes a conductor structure through which the current flows and a graphene layer arranged in direct contact with the conductor structure.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Applicant: Infineon Technologies Austria AG
    Inventor: Wolfgang GRANIG
  • Patent number: 11894445
    Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: February 6, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Tutuc, Matthias Kuenle, Ingo Muri, Hans Weber
  • Patent number: 11894775
    Abstract: A power conversion method is disclosed. The method includes operating a PFC converter configured to receive three input voltages and provide a DC link voltage between DC link nodes in one of at least two different operating modes, and operating an SR converter coupled to the PFC converter via the DC link nodes in one of at least two different operating modes dependent on an output voltage of the SR converter. Operating the SR converter includes regulating a voltage level of the DC link voltage dependent on a DC link voltage reference, and the at least two different operating modes of the SR converter include a buck mode and a series resonant mode.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: February 6, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Johann Walter Kolar, Yunni Li, Jannik Robin Schaefer
  • Patent number: 11887961
    Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Paul Frank, Thomas Heinelt, Oliver Schilling, Sven Schmidbauer, Frank Wagner