Patents Assigned to Infineon Technologies Austria AG
  • Patent number: 10979032
    Abstract: Circuits and devices are provided for reliably maintaining a normally-off Gate Injection Transistor (GIT), or similar, in a non-conducting state when a gate of the GIT is not driven with a turn-on control signal. This is accomplished using a failsafe pulldown coupled to the GIT's gate. The failsafe pulldown includes a resistance modulation circuit, which varies the effective gate resistance of the GIT, such that a low resistance is provided for an interval immediately after a turn-on transition of the GIT, thereby facilitating a high-current pulse for charging the GIT's gate. Subsequently, a high resistance is provided, such that a much lower current is driven to maintain the GIT in its on state. The failsafe pulldown enables a GIT, or similar, to be driven with a relatively simple driver, which may be provided external to the power switch device or integrated in the same die as the power switch.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Kennith Kin Leong, Petio Natzkin
  • Patent number: 10978395
    Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Keshav Joshi, Rainer Pelzer, Axel Bürke, Sven Schmidbauer, Michael Nelhiebel
  • Patent number: 10978596
    Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Mario Barusic, Markus Bina, Matteo Dainese
  • Patent number: 10958268
    Abstract: Transformer-driven power switch devices are provided for switching high currents. These devices include power switches, such as Gallium Nitride (GaN) transistors. Transformers are used to transfer both control timing and power for controlling the power switches. These transformers may be careless, such that they may be integrated within a silicon die. Rectifiers, pulldown control circuitry, and related are preferably integrated in the same die as a power switch, e.g., in a GaN die, such that a transformer-driven switch device is entirely comprised on a silicon die and a GaN die, and does not necessarily require a (large) cored transformer, auxiliary power supplies, or level shifting circuitry.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Kennith Kin Leong, Thomas Ferianz
  • Patent number: 10957788
    Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Hölzl, Henning Kraack, Gabor Mezoesi, Hans-Joachim Schulze, Waqas Mumtaz Syed
  • Patent number: 10957771
    Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. The field electrode includes a first layer and a second layer. The second layer includes a different conductive material as the first layer. A portion of the second layer is disposed above and directly contacts a portion of the first layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventor: Thomas Feil
  • Patent number: 10958158
    Abstract: An AC/DC converter is operative to receive, via AC input terminals, an AC input signal and to transform the AC input signal into a DC output signal. The AC/DC converter comprises a first DC discharge circuit coupled to AC input terminals. The controller comprises a second DC discharge circuit having a controllable switching element for switching the second DC discharge circuit on and off. The second DC discharge circuit is operative to receive a DC discharge current from the first DC discharge circuit; logic associated with the AC/DC converter repeatedly: receives a DC sense signal from the second DC discharge circuit and determines, based on the value of the DC sense signal within a predetermined measurement time period, loss of the AC input signal. In response to determining loss of the AC input signal, the logic controls activation of the second DC discharge circuit depending on the DC sense signal.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Shih-Jeng Chen, Shi-Heng Hong, Martin Krueger
  • Patent number: 10950691
    Abstract: A power converter circuit includes an inductor and rectifier circuit having an inductor connected in series with an electronic switch, and a rectifier circuit, and a controller for generating a drive signal for driving the electronic switch. The electronic switch has drain, source and gate nodes, drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Giulio Fragiacomo, Bjoern Fischer, Rene Mente, Armin Willmeroth
  • Patent number: 10950487
    Abstract: Disclosed is a method. The method includes forming a trench structure with at least one first trench in a first section of a semiconductor body; forming a second trench that is wider than the first trench in a second section of the semiconductor body; and forming a semiconductor layer on a surface of the semiconductor body in the first section and the second section and in the at least one first trench and the second trench such that the semiconductor layer has a substantially planar surface above the first section and a residual trench remains above the second section. Forming the semiconductor layer includes forming a first epitaxial layer in a first epitaxial growth process and a second epitaxial layer on top of the first epitaxial layer in a second epitaxial growth process.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Tutuc, Hans Weber
  • Patent number: 10942838
    Abstract: An electronic device is described herein. In accordance with one embodiment, the electronic device includes an embedded controller having a debug logic, an interface circuit coupled to the debug logic, and a memory coupled to the interface circuit. The interface circuit is operative to read debug information stored in the debug logic and to transmit the read debug information to the memory. The interface circuit is further operative to receive debug information stored in the memory and write the received debug information into the debug logic.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Matthias Schneider, Arndt Pauschardt, Yuanfen Zheng
  • Patent number: 10943987
    Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm?3.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
  • Patent number: 10937720
    Abstract: A semiconductor device includes a copper structure over a semiconductor body. In a copper oxide layer on a surface of the copper structure, a content of copper is between 60 at % and 75 at % and a content of oxygen is between 25 at % and 40 at %.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Silvia Larisegger, Michael Nelhiebel, Sabine Reither
  • Patent number: 10924102
    Abstract: Disclosed is a method for driving a transistor device and an electronic circuit. The method includes: in an on-state of the transistor device (1), reducing a drive voltage (VGS) of the transistor device (1) from a maximum voltage level (VMAX) to an intermediate voltage level (VINT) that is higher than a threshold voltage level (VTH) of the transistor device (1); maintaining the intermediate voltage level (VINT) for a predefined time period (TINT); and reducing the drive voltage (VGS) to below the threshold voltage level (VTH) after the predefined time period (TINT) to switch the transistor device to an off-state.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan H. Groiss, Aliaksandr Subotski
  • Patent number: 10923432
    Abstract: A semiconductor wafer includes an alignment mark contained within in a kerf region of the semiconductor wafer. The alignment mark includes a groove vertically extending from a main surface of the semiconductor wafer to a bottom surface of the groove, and at least one tin protruding from the bottom surface of the groove. The groove has a rectangular shape with four sidewalls and four inside corners, with each of the four inside corners facing the at least one fin. A minimum distance between the at least one fin and a nearest one of the four inside corners is at least 25 ?m.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Moser, Hans Weber, Johannes Baumgartl, Gabor Mezoesi, Michael Treu
  • Patent number: 10924108
    Abstract: A circuit arrangement is enclosed. The circuit arrangement includes a first electronic circuit; a second electronic circuit; and a coupling circuit connected between the first electronic circuit and the second electronic circuit. The first electronic circuit is at least partially integrated in a first region of a semiconductor layer, the second electronic circuit is at least partially integrated in a second region of the semiconductor layer, and the second region adjoins a first insulating layer formed on a first surface of the semiconductor layer and is electrically insulated from the first region by a second insulating layer. Further, the coupling circuit is arranged in a third insulating layer formed on a second surface of the semiconductor layer and comprises at least two capacitors connected in series.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Muellauer, Thomas Ferianz, Hermann Gruber
  • Patent number: 10923578
    Abstract: A semiconductor device includes a transistor. The transistor includes a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and the first main surface, and a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a dummy mesa. The plurality of trenches includes at least one active trench. The first mesa is arranged at a first side of the active trench, and the dummy mesa is arranged at a second side of the active trench. A gate electrode is arranged in the active trench, and a source region of the first conductivity type is in the first mesa. A one-sided channel of the transistor is configured to be formed in the first mesa.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Caspar Leendertz, Markus Bina, Matteo Dainese, Alice Pei-Shan Hsieh, Christian Philipp Sandow
  • Patent number: 10917011
    Abstract: A power supply includes a power converter, a reference voltage generator, and a controller. During operation, the power converter produces an output voltage to power a load. The reference voltage generator (such as a voltage mode amplifier circuit) generates a floor reference voltage, a magnitude of which varies as a function of the output voltage. The controller compares an output voltage feedback signal (derived from the output voltage) to the floor reference voltage to produce control output to control timing of activating switches in the power converter to maintain the output voltage within a desired voltage range.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Anthony B. Candage, Keng Chen, Paul Sisson
  • Patent number: 10910318
    Abstract: A semiconductor wafer has a semiconductor body, an insulation layer on the semiconductor body, an active region with a power semiconductor die, the active region forming a part of the semiconductor body, a scribeline region arranged adjacent to the active region, and a passivation structure arranged above the insulation layer and exposing a section of the insulation layer. The exposed section of the insulation layer is terminated by a termination edge of the passivation structure. The semiconductor wafer also has an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage. The optically detectable reference feature is included in the active region, spatially displaced from the termination edge, and exposed by the passivation structure.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Patent number: 10910284
    Abstract: A semiconductor device includes a first semiconductor component having a semiconductor substrate, and a barrier layer disposed at least on or at a portion of the first semiconductor component. The barrier layer includes a polymer material and an organic metal complexing agent covalently bound to the polymer material. In an embodiment, the organic metal complexing agent includes a crown ether and/or cryptand. In an embodiment, the polymer material includes a homopolymer or copolymer resulting from the polymerization of monomers selected from the group consisting of: imides, epoxies, silicones, monomers having functional side chains, methacrylates, and any combinations thereof.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: February 2, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Schwab, Herbert Hutter
  • Patent number: 10901449
    Abstract: An electronic circuit includes a first input pin configured to receive a first input signal that includes an enable information and at least one operation parameter information, a second input pin configured to receive a second input signal, an output pin, a control circuit configured to generate a drive signal based on the first input signal and the second input signal, an output circuit configured to generate an output signal at the output pin, the enable information includes an enabled state and a disabled state, the control circuit is configured to generate the drive signal in the enabled state and to turn to the electronic circuit off in the disabled state, the at least one operation parameter information includes information about an operational parameter of the output signal, and the output circuit is configured to use the at least one operation parameter information to change the operational parameter of the output signal.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Tobias Gerber, Thomas Ferianz