Throttle control circuits for throttling activity in processing segment circuits in an integrated circuit (IC) chip and related methods
A throttle control circuit receives a throttle control signal for controlling power consumption in a plurality of processing segment circuits. The throttle control signal has a throttle control value based on throttle requests from monitoring circuits that have detected power-related events or conditions and correspond to a requested change in activity in the plurality of processing segment circuits. The throttle control circuit receives the throttle control signal in a plurality of throttle administration circuits that each generates a throttle select signal to select an activity control signal for a corresponding processing segment circuit. In each of a first number (N) of consecutive cycles of a clock signal, the activity control signal disables state changes in the corresponding processing segment circuit for a second number (M) of cycles among the first number (N) of consecutive cycles to reduce power consumption in the processing segment circuits.
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The field of the disclosure relates to processor-based systems (e.g., central processing unit (CPU)-based systems, graphic processing unit (GPU)-based systems), or neural network processing unit (NPU)-based systems, and more particularly, to power distribution management of circuits in the processor-based systems.
II. BackgroundMicroprocessors, also known as processing units (PUs), perform computational tasks in a wide variety of applications. One type of conventional microprocessor or PU is a central processing unit (CPU). Another type of microprocessor or PU is a dedicated processing unit known as a graphics processing unit (GPU). A GPU is designed with specialized hardware to accelerate the rendering of graphics and video data for display. A GPU may be implemented as an integrated element of a general-purpose CPU or as a discrete hardware element that is separate from the CPU. Other examples of PUs may include neural network processing units or neural processing units (NPUs). CPUs are configured to execute software instructions that cause a processor to fetch data from a location in a memory and to perform one or more processor operations using the fetched data.
PUs are included in a computer system that includes other supporting processing devices (circuits) involved with or accessed as part of performing computing operations in the computer system. Examples of these other supporting processing devices include memory, input/output (I/O) devices, secondary storage, modems, video processors, and related interface circuits. The PUs and supporting processing devices in a computer system are referred to collectively as processing devices. Processing devices of a processor-based system can be provided in separate integrated circuits (ICs) in separate IC chips or may be aggregated in a larger IC, like a system-on-a-chip (SoC) IC, wherein some or all of these processing devices are integrated into the same IC chip. For example, an SoC IC chip may include a PU that includes a plurality of processor cores and supporting processing devices, such as a memory system that includes cache memory and memory controllers for controlling access to external memory, I/O interfaces, power management systems, etc. An SoC may be particularly advantageous for applications in which a limited area is available for the computer system (e.g., a mobile computing device such as a cellular device). To manage power distributed to the processing devices, the SoC may also include a power management system that includes one or more power rails in the SoC that supply power to its components. A separate power management integrated circuit (PMIC) that can be off-chip or on-chip with the SoC can independently control power supplied to the power rails. The SoC may be designed with a plurality of different power rails that are distributed within the SoC to provide power to various clusters of the processing devices for their operation. For example, all the processor cores in the SoC may be coupled to a common power rail for power, whereas supporting processing devices may be powered from separate power rails in the SoC, depending on the design of the SoC.
SUMMARY OF THE DISCLOSUREAspects disclosed herein include throttle control circuits for throttling activity of processing segment circuits in an integrated circuit (IC) chip. Related methods of throttle control in an IC chip are also disclosed. The IC chip includes a processor as well as integrated supporting processing devices (e.g., network nodes, memory controllers, internal memory, input/output (I/O) interface circuits, etc.) for the processor. For example, the processor may be a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU), wherein the processor includes multiple processing units (PUs) and/or processor cores. The processor-based system may be provided as a system-on-a-chip (SoC) that includes a processor and the integrated supporting processing devices for the PU. As examples, the SoC may be employed in smaller mobile devices (e.g., a cellular phone, a laptop computer), as well as enterprise systems such as server chips in computer servers. The IC chip may also include a hierarchical power management system that is configured to control power consumption by the processor-based system at both local and centralized levels to achieve a desired performance within an overall power budget for the IC chip. The hierarchical power management system can be configured to control power consumption by controlling the power level (e.g., by controlling the voltage level) distributed at one or more power rails in the IC chip that provide power to the PUs and the integrated supporting processing devices. For example, the hierarchical power management system can be configured to provide additional power to certain power rails to supply power to higher current-demanding devices to achieve higher performance while providing less power to other power rails to keep the overall power within power and/or thermal limits for the IC chip. The hierarchical power management system can also be configured to control power consumption by throttling performance (e.g., frequency) of the processing devices in the processor-based system, which in turn throttles (i.e., reduces, maintains, or increases) their current demand and thus their power consumption. Note, as used herein, throttle can mean to take an action that will decrease or increase a parameter that affects power and thus results in a respective decrease or increase in power consumption.
The hierarchical power management system is configured to throttle performance of the processing devices in the processor-based system because the level of processing activity in the processing devices in a SoC can vary based on workload conditions. Some power rails in the SoC may experience heightened current demand. It is desired that this current demand does not exceed the maximum current limitations of its respective power rail. Even if a higher current demand on a power rail is within its maximum current limits, a heightened activity of a processing device in the SoC can generate a sudden increase in current demand from its power rail, referred to as a “di/dt” event. This di/dt event can cause a voltage droop in the power rail, thus negatively affecting performance of processing devices powered by such power rail. Also, even if a higher current demand on a power rail is within its maximum current limits, a higher current demand can increase the overall power consumption of the SoC. Processing devices may have a maximum power rating to operate properly and/or to not impact performance in an undesired manner. Higher current demand from processing devices can also generate excess heat. Thus, the maximum power rating of the SoC may be based in part on the ability of the SoC to dissipate heat generated by the processing devices during their operation.
In exemplary aspects, the hierarchical power management system may include local area management (LAM) circuits distributed in the IC chip that are each associated with and provided to monitor one or more processing circuits (also referred to as “processing devices”) in the IC chip. The LAM circuits may be configured to generate power events associated with monitored processing circuits in the IC chip that represent power consumption associated with the monitored processing devices in the IC chip. The power events can be reported from local areas in the IC chip, where power estimations for particular monitored processing devices are performed, to a centralized power estimation and limit (PEL) circuit in the hierarchical power management system. The PEL circuit may be configured to estimate and control (i.e., throttle) power in the processor-based system in the IC chip to achieve a desired performance within an overall power budget for the IC chip. The PEL circuit may determine how to throttle power based on the received power events. For example, the power events may be associated with estimations of power consumption that can be thought of as power throttle recommendations to throttle power in the IC chip if the estimated power consumption exceeds the power limits of the IC chip or negatively affects performance.
The activity of the processing devices in the IC chip may affect its steady state current demand (I) and current transients (di/dt), and thus its power consumption. Because the IC chip may be larger in terms of die area due to the integration of the PUs and integrated supporting processing devices, there can be a significant delay between when the PEL circuit receives a power event regarding power consumption of a monitored processing device and the PEL circuit throttling power in the IC chip to throttle power consumption in response. This delay can, for example, cause devices in the IC chip to temporarily continue to consume excess power that can cause thermal and/or power issues (e.g., di/dt issues, voltage droop, heat generation) or permanent damage before the power management circuit has time to react. Thus, in response to the power events, current demand and transients, and other monitoring and control circuits associated with each LAM circuit, localized control may also be asserted on the processing circuits to improve response time and avoid performance issues.
In this regard, the processor-based system includes, additionally or alternatively, a throttle control circuit that may be associated with a LAM circuit and receive a throttle control signal for controlling power consumption in a plurality of processing segment circuits which may be associated with the LAM circuit. The throttle control signal has a throttle control value that may be based on throttle requests provided from monitoring circuits that have detected power-related events or conditions associated with the LAM circuit and correspond to a requested change in activity in the plurality of processing segment circuits. In an exemplary aspect, the throttle control circuit receives the throttle control signal in a plurality of throttle administration circuits. Each throttle administration circuit generates a throttle select signal to select an activity control signal for a corresponding processing segment circuit. A throttle sequence selection circuit receives the respective throttle select signals and provides, to the plurality of processing segment circuits, a selected activity control signal to reduce state changes in the processing segment circuit according to the throttle control value. In this regard, in each of a first number (N) of consecutive cycles of a clock signal, the activity control signal disables state changes in the corresponding processing segment circuit for a second number (M) of cycles among the first number (N) of consecutive cycles to reduce power consumption in the processing segment circuits.
In this regard, in one exemplary aspect, an integrated circuit (IC) chip comprising a processor-based system. The processor-based system comprises a plurality of processing segment circuits, each configured to operate in response to a clock signal; and a throttle control circuit. The throttle control circuit comprises a plurality of throttle administration circuits, each configured to receive a throttle control signal and generate a throttle select signal based on the throttle control signal, corresponding one of the first plurality of processing segment circuits; and a throttle sequence selection circuit configured to provide, to each of the first plurality of processing segment circuits, an activity control signal configured to throttle activity in the processing segment circuit in a first number (M) of cycles among a second number (N) of consecutive cycles of the clock signal based on a corresponding throttle select signal.
In another exemplary aspect, a method of controlling activity in an integrated circuit (IC) chip comprising a processor-based system is disclosed. The method comprises operating each of a plurality of processing segment circuits in response to a clock signal; receiving, in each of a plurality of throttle administration circuits, a throttle control signal; and generating a throttle select signal corresponding one of the first plurality of processing segment circuits. The method further comprises providing an activity control signal, based on the corresponding throttle select signal, to each of the first plurality of processing segment circuits in each cycle of a first number (N) of consecutive cycles of the clock signal, the activity control signal configured to disable operation in the processing segment circuit in a second number (M) of cycles among the first number (N) of consecutive cycles.
In another exemplary aspect, a throttle control circuit is disclosed. The throttle control circuit comprises a plurality of throttle administration circuits, each configured to receive a throttle control signal and generate a throttle select signal based on the throttle control signal, corresponding one of a first plurality of processing segment circuits. The throttle control circuit also comprises a throttle sequence selection circuit configured to provide, to each of the first plurality of processing segment circuits in each cycle of a first number (N) of consecutive cycles of the clock signal, an activity control signal configured to disable state changes in the processing segment circuit in a second number (M) of cycles among the first number of consecutive cycles based on the corresponding throttle select signal.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed herein may optionally include a hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip. Related power management and power throttling methods are also disclosed. The IC chip includes a processor as well as integrated supporting processing devices (e.g., network nodes, memory controllers, internal memory, input/output (I/O) interface circuits, etc.) for the processor. For example, the processor may be a central processing unit (CPU), graphics processing unit (GPU), or neural network processing unit (NPU), wherein the processor includes multiple processing units (PUs) and/or processor cores. The processor-based system may be provided as a system-on-a-chip (SoC) that includes a processor and the integrated supporting processing devices for the PU. As examples, the SoC may be employed in smaller mobile devices (e.g., a cellular phone, a laptop computer), as well as enterprise systems such as server chips in computer servers. The IC chip may also include a hierarchical power management system that is configured to control power consumption by the processor-based system at both local and centralized levels to achieve a desired performance within an overall power budget for the IC chip. The hierarchical power management system can be configured to control power consumption by controlling the power level (e.g., voltage level) distributed at one or more power rails in the IC chip that provide power to the PUs and the integrated supporting processing devices. For example, the hierarchical power management system can be configured to provide additional power to certain power rails supplying power to higher current-demanding devices to achieve higher performance while providing less power to other power rails to keep the overall power within power and/or thermal limits for the IC chip. The hierarchical power management system can also be configured to control power consumption by throttling performance (e.g., frequency) of the processing devices in the processor-based system, which in turn throttles (i.e., reduces, maintains, or increases) their current demand and thus their power consumption. Note, as used herein, throttle can mean to take an action that will decrease or increase a parameter that affects power and thus results in a respective decrease or increase in power consumption.
In exemplary aspects, the hierarchical power management system may include local area management (LAM) circuits distributed in the IC chip that are each associated with one or more processing devices in the IC chip. The LAM circuits may be configured to generate power events associated with its monitored processing devices in the IC chip that represent power consumption associated with the monitored processing devices in the IC chip. The power events can be reported from local areas in the IC chip, where power estimations for particular monitored processing devices are performed, to a centralized power estimation and limit (PEL) circuit in the hierarchical power management system. The PEL circuit is configured to estimate and control (i.e., throttle) power in the processor-based system in the IC chip to achieve a desired performance within an overall power budget for the IC chip. The PEL circuit may determine how to throttle power based on the received power events. For example, the power events may be associated with estimations of power consumption that can be thought of as power throttle recommendations to throttle power in the IC chip if the estimated power consumption exceeds the power limits of the IC chip or negatively affects performance.
The activity of the processing devices in the IC chip may affect its steady state current demand and transient current demands (e.g., changes in current flow rate referred to as “di/dt”) and thus affect power consumption. Because the IC chip may be larger in terms of die area due to the integration of the processing units and integrated supporting processing devices, there can be a significant delay between when PEL circuit receives a power event regarding the consumption of a monitored processing device and the PEL circuit throttling power in the IC chip to throttle power consumption in response. This delay can, for example, cause devices in the IC chip to temporarily continue to consume excess power that can cause performance issues (e.g., di/dt issues, voltage droop, heat generation) before the power management circuit has time to react.
In this regard, the processor-based system includes, additionally or alternatively, a throttle control circuit that may be associated with a LAM circuit and receive a throttle control signal for controlling power consumption in a plurality of processing segment circuits which may be associated with the LAM circuit. The throttle control signal has a throttle control value that may be based on throttle requests provided from monitoring circuits that have detected power-related events or conditions associated with the LAM circuit and correspond to a requested change in activity in the plurality of processing segment circuits. In an exemplary aspect, the throttle control circuit receives the throttle control signal in a plurality of throttle administration circuits. Each throttle administration circuit generates a throttle select signal to select an activity control signal for a corresponding processing segment circuit. A throttle sequence selection circuit receives the respective throttle select signals and provides, to the plurality of processing segment circuits, a selected activity control signal to reduce state changes in the processing segment circuit according to the throttle control value. In this regard, in each of a first number (N) of consecutive cycles of a clock signal CLK, the activity control signal disables state changes in the corresponding processing segment circuit for a second number (M) of cycles among the first number (N) of consecutive cycles to reduce power consumption in the processing segment circuits.
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Also, as discussed in more detail below, a hierarchical power management system 124 can also be configured to control power consumption in the processor-based system 100 by throttling performance, which may include controlling clock frequency and/or supply voltage on the power rails provided to the processing devices 110 in the processor-based system 100. Throttling performance may also include controlling activity that causes the consumption of power. These methods, in turn, throttle (i.e., reduce, maintain, or increase) the current demand of such processing devices 110 and, thus, their power consumption in the IC chip 104. Throttling may generally refer to any measure (for example, modifying activity, a clock frequency, and/or a supply voltage) to effect (i.e., reduce, maintain, or increase) power consumption. Performance of clocked circuits in the processing devices 110 in the processor-based system 100 in terms of frequency (f) is related to power (P) according to the power equation P=c f V2, where ‘c’ is capacitance and ‘V’ is voltage. Thus, reducing the frequency of a clocked circuit in a processing device 110 in the processor-based system 100 also reduces its power consumption.
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The power consumption of the processing devices 110 in the processor-based system 100 may contribute to the power consumption in the IC chip 104. Thus, it may be desired to also have a way for the PEL circuit 126 in the hierarchical power management system 124 to receive a direct indication of power consumption for the processing devices 110. The PEL circuit 126 can then use this information to estimate power consumption in the IC chip 104 and use such information to appropriately throttle the power consumption in the IC chip 104. In this regard, as shown in
In either case, in this manner, the activity power events 138 can be reported from local areas in the IC chip 104, where power estimations for particular monitored processing devices 110 are performed, to the centralized PEL circuit 126. The PEL circuit 126 can then be configured to use the received activity power events 138 and/or the other power events 130 to estimate and control (i.e., throttle) power in the processor-based system 100 in the IC chip 104 to achieve a desired performance within an overall power budget for the IC chip 104. For example, the activity power events 138 that are associated with estimations of power consumption of processing devices 110 that can be thought of in essence as power throttle recommendations to the PEL circuit 126 for the PEL circuit 126 to throttle power in the IC chip 104 if the estimated power consumption exceeds the power limits of the IC chip 104 or negatively affects performance in an undesired manner.
The PEL circuit 126 being configured to receive activity power events 138 relating to activity for individual processing devices 110 in the processor-based system 100 allows the PEL circuit 126 to throttle power consumption to certain local processing devices 110 that are responsible for increased power consumption. This allows the PEL circuit 126 to throttle power with discrimination as opposed to throttling power to the power rails or, in other ways, in the IC chip 104 that affects the power delivered to a larger set of processing devices 110 as a whole. For example, as discussed in more detail below, the PEL circuit 126 can be configured to use the received activity power events 138 to perform performance throttling of processing devices 110 in the processor-based system 100 to throttle its power consumption. The PEL circuit 126 can be configured to generate power limiting management responses 140 to be communicated to certain LAM circuits 136 in the processor-based system 100 to cause such LAM circuits 136 to limit the performance of its monitored processing device 110.
Performance throttling of a processing device 110 in the processor-based system 100 to throttle its power consumption can be accomplished in different manners. For example, as discussed in more detail below, performance throttling can be achieved by the PEL circuit 126 by generating a throughput throttling power limiting management response 140, which is destined for the LAM circuit 136(3) associated with the internal communication network 114. The LAM circuit 136(3) can be configured to throttle the throughput of communication traffic in the internal communication network 114, such as at a particular network node in the internal communication network 114, to throttle current demand in the internal communication network 114 and thus its power consumption. Throughput throttling can be isolated to only certain areas or network nodes in the internal communication network 114. In another example, as discussed in more detail below, performance throttling in the processor-based system 100 can be achieved by the PEL circuit 126 by generating a clock throttling power limiting management response 140 to cause a clock circuit (which may be clocking one or more of the processing devices 110) to throttle the speed (i.e., clock frequency) of certain clocked processing devices 110. Clock throttling of a processing device 110 throttles its current demand, which throttles its power consumption. In another example, as discussed in more detail below, performance throttling in the processor-based system 100 can be achieved by throttling or changing the power states of a monitored processing device 110 to throttle its performance and thus its power consumption.
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In this example, any of the RAM circuits 502, 502(2)-502(4) discussed above can also include circuitry to behave functionally as a LAM circuit for an assigned processing device 110. In this regard, any of the RAM circuits 502, 502(2)-502(4) can also be configured to sample the processing activity of its respective assigned processing device 110 to generate a plurality of activity samples for such processing device 110. Such RAM circuits 502, 502(2)-502(4) can be configured to estimate the power consumption of its assigned processing device 110 based on the activity samples regarding its assigned processing device 110 to generate an aggregated activity power event based on the such estimated power consumption of the respective processing device 110 and the other received activity power events 138 from its coupled LAM circuits 136(1)(0)-(1)(N), 136(2)-136(5), 136(6)(0)-136(6)(X).
Note that in any of the above-referenced examples, the RAM circuits 502 are optional for any of the monitored processing devices 110, and their respective LAM circuits 136(1)-136(6) can be configured to communicate activity power events 138 directly to the PEL circuit 126.
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For example, if the target circuit 620(1)-620(Q) is assigned to a target device 200 of a power rail 300(1)-300(5), the target circuit 620(1)-620(Q) can be configured to determine how to throttle the voltage to the associated power rail 300(1)-300(5) to control power consumption of processing devices 110 powered by such power rail 300(1)-300(5). The respective power limiting command generation circuit 625(1)-625(Q) can be configured to generate a performance throttling power limiting management response 140(1)-140(Q) to cause the voltage provided to the associated power rail 300(1)-300(5) to be throttled to control power consumption of processing devices 110 powered by such associated power rail 300(1)-300(5).
In another example, if the target circuit 620(1)-620(Q) is assigned to a target device 200, such as the internal communication network 114, the target circuit 620(1)-620(Q) can be configured to determine how to throttle performance of the internal communication network 114 to control power consumption of the internal communication network 114. For example, to throttle the throughput performance of the internal communication network 114, the target device 200 may be the clock circuit 506 (
In another example, if the target circuit 620(1)-620(Q) is assigned to a target device 200 as a PU cluster 108(0)-108(N) or any other processing device 110, the target circuit 620(1)-620(Q) can be configured to determine how to throttle performance of the internal communication network 114 to control power consumption of the internal communication network 114. For example, to throttle performance of the PU cluster 108(0)-108(N) or other processing device 110, the target device 200 may be the clock circuit 506 (
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Note that in the sequence of operations and communications described above with regard to the LAM circuits 136 communicating activity power events 606 to the RAM circuits 502, and the RAM circuits 502 communicating aggregated activity power events 138 to the PEL circuit 126, communication delays are incurred. There is a delay between generating the activity samples 600 of sampling of power consumptions in a processing device 110 in a LAM circuit 136 and the reporting and receipt of an associated aggregated activity power event 138 in the PEL circuit 126. This delay can be particularly large for an IC chip 104 that has a larger area, such as one that includes a number of PU clusters 108(0)-108(N) and other processing devices 110 as in the processor-based system 100. By the time the PEL circuit 126 receives the associated aggregated activity power event 138 and processes such to a generation of an associated power limiting management response 140(1)-140(Q), the power consumed by the monitored processing device 110 may have already exceeded desired power limits in an undesired manner and/or for an undesired amount of time, possibly causing the power consumption in the IC chip 104 to exceed designed power limits. Further, instantaneous current demand by a monitored processing device 110 can cause di/dt events or voltage droop events that can cause performance issues and/or failures that may not be able to be timely addressed by the PEL circuit 126.
To mitigate the delay in the PEL circuit 126 receiving aggregated activity power events 138 associated with monitored processing devices 110 in the processor-based system 100 that may affect throttling of power consumption within the processor-based system 100, each of the LAM circuits 136, 136R can also be configured to directly throttle performance of an associated monitored processing device 110 to throttle its current demand and thus throttle its power consumption. This gives the PEL circuit 126 more reaction time to receive and process aggregated activity power events 138 to determine how power consumption in the processor-based system 100 should be throttled to achieve a desired overall performance while also maintaining power consumption within desired limits. In this manner, the LAM circuits 136, 136R may be able to more timely mitigate a power issue by locally throttling power consumption of its specific monitored processing device 110 on a device granularity (without having to throttle performance in other processing devices 110). The LAM circuits 136, 136R can be configured to continuously monitor and throttle power consumption locally in its monitored processing device 110, co-existent with the PEL circuit 126 generating power limiting management responses 140 to limit power consumption by target devices 200 in the processor-based system 100.
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In this manner, the LAM circuit 136 may be configured to continually monitor the ongoing current flow rate of its monitored processing device 110 to be able to locally throttle the power consumption of the monitored processing device 110. In this manner, the LAM circuit 136 may be configured to respond more quickly to power consumption issues caused by the current demand of the monitored processing device 110, such as di/dt events and voltage droops, before the PEL circuit 126 may be able to respond.
As an example, if the monitored processing device 110 by the LAM circuit 136 is a network node 500 of the internal communication network 114, the local throttle signals 634 generated by the LAM circuit 136 may be a throughput throttle to selectively enable and disable communication flow in the network node 500 to throttle its throughput thus throttling its power consumption. As another example, if the monitored processing device 110 by the LAM circuit 136 is a PU cluster 108(0)-108(N) or other processing device 110, the local throttle signals 634 generated by the LAM circuit 136 may be a performance throttle to selectively throttle performance or workload of the monitored PU cluster 108(0)-108(N) or other processing device 110 to throttle its performance thus throttling its power consumption.
Note that sampling of processing activity discussed herein may be accomplished by determining or sampling a quantity that is associated with an instantaneous activity of the monitored processing device 110. For example, the workload performed by a monitored processing device 100 may be determined or discoverable as an indirect method to determine instantaneous activity that can be correlated to an estimated current or power consumption. As another example, activity of a monitored processing device 110 may be determined by sensing a temperature at a temperature sensor associated with the processing device 110. As another example, a voltage droop may be sensed at the processing device 110 to determine an activity sample. Also, other quantities may be used to sample activity. As an example, an incoming interrupt at the processing device, a status register, a state of an interrupt queue, or a signal indicating whether the processing device is busy or idle may be used for sampling of processing activity.
Note that the components to perform local throttling by the LAM circuit 136 can also be provided in the LAM circuit 136R in the RAM circuit 502 so that the LAM circuit 136R may also be configured to locally throttle a monitored processing device 110.
Note that the hierarchical power management system 124 provided in the IC chip 104 for the processor-based system 100 in
Also, as discussed herein, it is stated that the PEL circuit 126 receives activity power events 606 from a LAM circuit 136, this receipt of activity power events 606 can be directly from the LAM circuit 136 to the PEL circuit 126 or indirectly from one or more intermediate circuits, including the RAM circuits 502. For example, as discussed above, the activity power events 606 generated by the LAM circuits 136 can be indirectly reported to the PEL circuit 126 the as part of being included in aggregated activity power events 138 generated and reported by a RAM circuit 502 to the PEL circuit 126 as part of received activity power events 606.
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The selected next current flow rate 642 is provided by the di/dt circuit 636 to the comparator circuit 906 in the throttle FSM circuit 644. The throttle FSM circuit 644 may be configured to generate the local throttle signals 634 to throttle power consumption of the monitored processing device 110 based on whether the selected next current flow rate 642 (from selection of change in current flow rate di_dt_1, di_dt_2, di_dt_3) exceeds a threshold current flow rate (which can include a threshold change in current flow rate) for the monitored processing device 110. The threshold current flow rate for the monitored processing device 110 can be obtained from a current flow rate register 908. The current flow rate register 908 can be programmed with a threshold current flow rate for the monitored processing device 110. For example, the current flow rate register 908 can be programmed with different threshold current flow rates (e.g., lowest, level 1, level 2, highest) so that the comparator circuit 906 can generate local throttle signals 634 for different levels of power consumption throttling based on the comparison of selected next current flow rate 642 (from selection of change in current flow rate di_dt_1, di_dt_2, di_dt_3) with the selected threshold current flow rate obtained from the current flow rate register 908.
Note that when current flow rate is discussed herein, such also means current flow and represents current (I) (e.g., charge (q) over time (t) (q/t)) or a change in the current flow rate (e.g., a change in current over time (di/dt)). A determined change in the current flow rate (di/dt) is determined from a determined current flow rate (t/T).
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The energy tracker circuits 1000(1)-1000(E) may each include respective data aggregator circuits 1016(1)-1016(E) that are configured to aggregate the received energy power events 1002 into respective aggregated energy power events 1018(1)-1018(E). The activity tracker circuits 612(1)-612(T) may also each include respective data aggregator circuits 1020(1)-1020(T) that are configured to aggregate received energy power events into respective aggregated energy power events 1022(1)-1022(T). The MAP tracker circuits 1004(1)-1004(B) may also each include respective data aggregator circuits 1024(1)-1024(T) that are configured to aggregate received energy power events into respective aggregated MAP power events 1027(1)-1027(B). The energy tracker circuits 1000(1)-1000(E), the activity tracker circuits 612(1)-612(T), and the MAP tracker circuits 1004(1)-1004(B) in this example, each include a respective energy power limit management policy circuits 1006, activity power limit management policy circuits 1008, and MAP power limit management policy circuits 1010 that are configured to generate respective energy power throttle recommendations 1012, activity power throttle recommendations 614, and MAP power throttle recommendations 1014. These generated respective energy power throttle recommendations 1012, activity power throttle recommendations 614, and MAP power throttle recommendations 1014 may be based on the respective received aggregated energy power events 1018(1)-1018(E), aggregated activity power events, 1022(1)-1022(T), aggregated MAP power events 1027(1)-1027(B) for the PEL circuit 1026 to process to determine how to throttle power consumption in the IC chip 104.
With continuing reference to
With continuing reference to
The target devices 200 can include the interface circuits 127(1)-127(Z) that can be throttled by power limiting management responses 140(1) communicated to a RAM circuit 502(6) and/or LAM circuit 136(6) configured to throttle power consumption in such interface circuits 127(1)-127(Z). The target devices 200 can include the PU clusters 108(0)-108(N) that can be throttled by power limiting management responses 140(2) communicated to a RAM circuit 502(1) and/or LAM circuit 136(1) configured to throttle power consumption in such PU clusters 108(0)-108(N). The target devices 200 can include the internal communication network 114 that can be throttled by power limiting management responses 140(3) communicated to a RAM circuit 502(3) and/or LAM circuit 136(3) configured to throttle power consumption in such internal communication network 114. The target devices 200 can include the memory controllers 118(0)-118(M) that can be throttled by power limiting management responses 140(4) communicated to a RAM circuit 502(2) and/or LAM circuit 136(2) configured to throttle power consumption in such memory controllers 118(0)-118(M). The target devices 200 can include the I/O interface circuits 120(0)-120(X) that can be throttled by power limiting management responses 140(5) communicated to a RAM circuit 502(4) and/or LAM circuit 136(4) configured to throttle power consumption in such I/O interface circuits 120(0)-120(X). The target devices 200 can include the S2S interface circuits 122(0)-122(Y) that can be throttled by power limiting management responses 140(6) communicated to a RAM circuit 502(5) and/or LAM circuit 136(5) configured to throttle power consumption in such S2S interface circuits 122(0)-122(Y).
The merge circuit 616 in the PEL circuit 1026 can be programmed to map (e.g., through firmware, electronic fuses, etc.) merged power throttle recommendations 618(1)-618(6) to a particular target device 200, and thus a target circuit 620(1)-620(6), that may not directly correlate to each other. In this manner, the merged power throttle recommendations 618(1)-618(6) related to power issues and power consumption in the IC chip 104 can be mapped in the PEL circuit 1026 to correlate to different target devices 200 for throttling power consumption. The merge circuit 616 can be programmed in a “many-to-many mapping” to correlate to different power-limiting management responses within the IC chip 104 in the desired manner for more flexibility in managing power consumption in the IC chip 104 while still achieving the desired performance. In this manner, the power throttling management behavior of the PEL circuit 1026 can be configured and changed even after the IC chip 104 is deployed in an application.
With continuing reference to
The components of a power management system, such as hierarchical power management systems 124, 624, 724 in
The throttle control circuit 1100 may be included in the LAM circuit 1110, which may be any of the LAM circuits 136 in
Each processing segment circuit 1104(1)-1104(X) includes at least one transistor circuit configured to change an output voltage state in response to the clock signal CLK. The processing segment circuits 1104(1)-1104(X) associated with the LAM circuit 1110 may each be located adjacent to another one of the processing segment circuits 1104(1)-1104(X) and may each be coupled to a same power rail to receive a power supply voltage.
The purpose of the throttle control circuit 1100 in this example is to provide local control or throttling of activity in the processing segment circuits 1104(1)-1104(X) associated with the LAM circuit 1110. Activity in the processing segment circuits 1104(1)-1104(X) refers to state changes or changes in a voltage state on the outputs of sequential circuits that occur in response to the clock signal CLK. For example, the voltage level on outputs of storage circuits, including memory circuits, latch circuits, and/or flip-flop circuits among the processing segment circuits 1104(1)-1104(X), may change state (e.g., switch) in response to a voltage or a change in voltage (e.g., a level, transition or edge) of the clock signal CLK. Such state changes cause a surge in current in the power rail(s), providing a power supply voltage to the processing segment circuits 1104(1)-1104(X). The number of circuits that switch in response to the clock signal CLK at a given moment varies depending on circumstances, such as a type of instructions being executed, a frequency of executing instructions, the data being processed, and other factors. As a result, the current and power requirements vary. Circuits can be provided to monitor current and power in an area local to the LAM circuit 1110 by detecting electrical characteristics such as current level, rate of change of current (di/dt), power level, rate of change of power consumption, or temperature. Current and power can also be measured indirectly by monitoring processing activity, such as by firmware. When these monitoring circuits determine, based on the particular aspect of current or power states or events that they measure, that the amount of activity in the processing segment circuits 1104(1)-1104(X) should be reduced, they can generate one of the threshold requests 1114(1)-1114(R), which are the throttle requests 1114(1)-1114(R) from
Stopping all activity in the processing segment circuits 1104(1)-1104(X) would be an extreme and unnecessary response to a minor di/dt event, for example. For a more appropriate response, the throttle requests 1114(1)-1114(R) each provide one of several values in a range to indicate, based on the severity of the problem detected (e.g., event or condition), an appropriate request for a reduction in activity. Consequently, the throttle control signal 1102 is a value based on the respective throttle requests. A reduction of activity in the processing segment circuits 1104(1)-1104(X) can be achieved by reducing the number of cycles within a window of consecutive cycles (clock window) of the clock signal CLK, in which switching or state changes are allowed (enabled) to occur. Maximum power is consumed when switching is enabled in all (100 percent) of the cycles of the clock signal CLK. In a clock window including a number (N) of consecutive cycles of the clock signal CLK, activity can be reduced in the processing segment circuits 1104(1)-1104(X) incrementally by reducing the number of cycles in which activity is enabled from N to 1. Thus, the number of possible values of the throttle control signal 1102 may equal to the number N of consecutive cycles in a clock cycle window of the clock cycle.
However, not all of the processing segment circuits 1104(1)-1104(X) may be identical in power consumption characteristics, as individual ones may perform different functions and therefore consume different amounts of power or may cause different rates of increase and/or decrease in current drawn on the power rail(s). In this regard, equally reducing the number of cycles of activity in all of the processing segment circuits 1104(1)-1104(X) may not be necessary or desirable to achieve the desired change in the power distribution. In addition, performance can be optimized for each incremental level of requested throttle reduction by varying the extent to which activity is reduced among the processing segment circuits 1104(1)-1104(X) in a configurable manner. Such configuration may be based on testing and programming of the IC chip 1106.
Implementation of an optimized incremental approach to activity reduction in the processing segment circuits 1104(1)-1104(X) includes storing individualized configuration information 1212 for each of the processing segment circuits 1104(1)-1104(X) in the configuration register 1214 for each incremental change in the throttle control value 1209 designated by the throttle control signal 1204. Receiving both the throttle control value 1209 and the configuration information 1212, the throttle administration circuits 1202(1)-1202(X) generate selections of appropriate levels of activity for each one of the processing segment circuits 1104(1)-1104(X). The throttle administration circuit 1202(1)-1202(X) is configured to, for a given throttle control value 1209, determine the number of cycles, among the first number (N) of cycles, that activity in a corresponding one of the processing segment circuits 1104(1)-1104(X) is disabled based on the configuration information 1212.
In a further aspect, while some of the throttle requests 1114(1)-1114(R) are based on measures (e.g., of events or conditions) that change slowly, others may be based on measures that can change significantly from cycle to cycle. In addition, one of the benefits of locally applied throttle control is the ability to respond to detected problems quickly. Therefore, the throttle control circuit 1200 is configured to respond in a next cycle of the clock signal CLK to request a significant reduction in activity in the processing segment circuits 1104(1)-1104(X). On the other hand, sudden increases in activity in the processing segment circuits 1104(1)-1104(X) can cause sudden increases in current that may result in a voltage droop, for example. Consequently, even if the throttle control signal 1204 indicates that a significant increase in activity is allowed, the throttle administration circuits 1202(1)-1202(X) may not allow a significant increase to occur during one or a few cycles. Rather, to avoid sudden increases in current and power, the throttle administration circuits 1202(1)-1202(X) may be implemented as finite state machines, referred to collectively as FSMs 1202. The FMSs 1202 can gradually increase activity in the corresponding processing segment circuits 1104(1)-1104(X) at a configurable rate. In view of the above considerations, the throttle administration circuits 1202(1)-1202(X) generate the throttle select signals 1208(1)-1208(X) that are each directed to one of the processing segment circuits 1104(1)-1104(X). The throttle select values 1207(1)-1207(N) of the throttle select signals 1208(1)-1208(X) are based on the most recent throttle control value 1209, the configuration information 1212 indicating the appropriate activity level for the corresponding one of the processing segment circuits 1104(1)-1104(X) at that throttle control value 1209, and a transition limitation imposed by the FSM limiting the number of states by which the FSM 1202 can change in one direction. The throttle select signals 1208(1)-1208(X) are provided to a throttle sequence selection circuit shown in
In an example in which the clock window is eight (8) consecutive cycles (i.e., N=8), the value of M ranges from zero (0) to seven (7). In such an example, the throttle sequence generator 1302(1) may generate a sequence in which the sequence signal 1304(1) is in a first state (e.g., “0” or “1”) for M=1 cycle and a second state (e.g., “1” or “0”) for N−M or 8−1=7 cycles. Here, the first state is provided to enable (allow) activity in the processing segment circuits 1104(1)-1104(X), and the second state is provided to disable activity. In additional examples, the throttle sequence generator 1302(3) may generate a sequence signal 1304(3) that is in a first state for 3 cycles and a second state for 5 cycles, and the throttle sequence generator 1302(8) may generate a sequence signal 1304(8) that is in the first state for 8 cycles and the second state for 0 cycles. As should be apparent, the sequence signal 1304(8) is provided to any of the processing segment circuits 1104(1)-1104(X) in which no throttling or reduction in activity is requested, and the sequence signal 1304(1) is provided for the most restrictive throttling response, allowing only one active cycle per cycle window.
The throttle sequence selection circuit 1300 includes multiplexors 1306(1)-1306(X), each corresponding to one of the processing segment circuits 1104(1)-1104(X). Each of the sequence signals 1304(1)-1304(N) is provided to each of the multiplexors 1306(1)-1306(N). The throttle select signals 1208(1)-1208(X) generated in the throttle administration circuits 1202(1)-1202(X) in
It can easily be recognized that the number N of throttle sequence generators 1302(1)-1302(N) in this example is determined by the number of different sequences that can be provided, which, in this case, corresponds to the number N of cycles in the clock window in the examples above. In another non-limiting example, rather than providing sequence signals 1304(1)-1304(N) having each increment from 1 to N active cycles, throttle sequence generator 1302(1)-1302(N/2) generating sequence signals 1304(1)-1304(N/2) having only even numbers of active cycles (e.g., 2, 4, 6, and 8) may be employed. In such a case, for a cycle window having 8 cycles, only four (4) throttle sequence generators may be needed. Other cases, including odd numbers of active cycles or any combination of active and inactive signals are also possible.
The number X of throttle administration circuits 1202(1)-1202(X) in
The sequence signals 1304(1)-1304(N) are labeled in
In the cycle window W0, in response to the enable signal EN being activated in cycle 1 of the clock signal CLK, the sequence signals indicated by 1/8 through 7/8 change from an enable state to a disable state (indicated by a transition from “0” to “1”) to disable activity in the processing segment circuits 1104(1)-1104(X) while the sequence signal 0/8 remains in the enable state. In each subsequent cycle, one of the sequence signals 1/8 through 7/8 transitions back to the enable state before the cycle window W0 ends. Since the enable signal EN continues to be active in cycle window W1, the sequence signals 0/8 through 7/8 are repeated until the enable signal EN is deactivated in cycle window W2.
Any of the throttle administration circuits 1202(1)-1202(X) being in the states 1502(0) to 1502(7) cause the corresponding sequence signals 0/8 to 7/8, respectively, to be selected by the multiplexors 1306(1)-1306(X). Generally, increases in the control value 1209 will result in upward transitions to more restrictive throttling of the processing segment circuits 1104(1)-1104(X). In this example, an upward transition refers to transitioning to a higher-numbered state, where state 1502(7) is the highest-numbered state and state 1502(0) is the lowest. Since it is preferable to respond quickly to increases in throttling to avoid or reduce power-related problems, upward transitions may occur from any one of the states 1502(1)-1502(6) to any higher numbered state (e.g., states 1502(2)-1502(7). For example,
The FSM 1202 may remain in the least restrictive state 1502(0), for any number of cycles until the throttle control signal 1204 increases, causing a transition to one of the more restrictive states 1502(1)-1502(7). Since the throttling function is implemented by the sequence signals 0/8 to 7/8, the FSM 1202 remains in any of the states 1502(1)-1502(7) for at least a full clock window (e.g., 8 cycles corresponding to clock windows W0 and W1 in
The state diagram 1500 also includes downward transitions 1506(2)-1506(7) and downward transitions 1508(1)-1508(7), which are examples of transitions that may occur in response to decreases in the throttle control value 1209. Downward transitions 1506(2)-1506(7) and downward transitions 1508(1)-1508(7) are transitions to lower states in the FSM 1202, which correspond to less restriction on activity in the processing segment circuits 1104(1)-1104(X), and thus higher power consumption. For this reason, sudden significant increases in activity are avoided. In this regard, at the end of a clock window, if the throttle control signal 1204 has decreased (and assuming the configuration information 1212 is not conflicting with a reduction in throttling), the FSM 1202 will transition to a lower state where more activity is allowed in the processing segment circuits 1104(1)-1104(X). However, to avoid sudden surges in current due to the increased activity, the FSM 1202 may limit the downward transition to a state that is, for example, only one state or two states lower than a current state.
Referring back to
The FSM 1202 may be configured to implement either downward transitions 1506(2)-1506(7) or downward transitions 1508(1)-1508(7) but is not limited to only these options. The FSMs 1202 may be able to select a transition limit indicating that the FSM 1202 can transition in the downward direction by a limited number of states in one transition. The transition limit may be regarded as a maximum number of states changed in a transition from one cycle to a next cycle or a maximum decrease in a corresponding one of the throttle select values 1207(1)-1207(X) from one cycle to a next cycle. The transition limit may be a configurable value stored in the configuration register 1214. For example, the FSM 1202 may be configured to transition three (3) states downward (e.g., from state 1502(7) to 1502(4)) if the throttle control signal 1204 decreases by three levels or more (e.g., from a 7/8 value to a 4/8 value or lower). As noted above, the FSM 1202 stays in each state for at least 8 cycles as the throttle control value 1209 decreases (during which the corresponding processing segment circuit 1104(1)-1104(X) receives the sequence signal, but may increase to a higher state in any cycle in response to an increase in the throttle control value 1209.
With further regard to the transition limit in the FSMs 1202, a transition from a state 1502(0)-1502(6) having a lower number to one of the states 1502(2)-1502(7) having a higher number is referred to herein as an upward transition and corresponds to an increase in the throttle control values 1209 generated by each of the FSMs 1202. Whereas a transition from a state 1502(1)-1502(7) having a higher number to one of the states 1502(0)-1502(6) having a lower number is referred to herein as a downward transition and corresponds to a decrease in the throttle control value 1209 generated by each of the FSMs 1202. In this regard, each of the plurality of FSMs 1202 is configured to increase, from one cycle to a next cycle, a first corresponding one of the throttle select values 1207(1)-1207(X) of the throttle select signal 1208(1)-1208(X) to any second corresponding second throttle select value 1207(1)-1207(X) in response to a corresponding increase in the throttle control value 1209. Each of the FSMs 1202 is configured to decrease, from one cycle to a next cycle, the throttle select signal 1204 from a first corresponding one of the throttle select values 1207(1)-1207(X) to a second corresponding one of the throttle select values 1207(1)-1207(X) by no more than the transition limit. In response to the throttle control value 1209 staying the same or decreasing, the FSMs 1202 are configured to provide a same throttle select value for the first number N of consecutive clock cycles in the clock window.
A throttle control circuit configured to receive a throttle control signal and provide, to a plurality of processing segment circuits, selected activity control signals to control activity in a clock window of N consecutive clock cycles, including throttling activity in a number M of the N consecutive cycles based on the throttle control signal and components thereof illustrated in
In this example, the processor-based system 1700 may be formed in an IC chip 1702 and as a system-on-a-chip (SoC) 1704. The processor-based system 1700 includes a central processing unit (CPU)(s) 1706 that includes one or more processors 1708, which may also be referred to as CPU cores or processor cores. The CPU 1706 may have cache memory 1710 coupled to the CPU 1706 for rapid access to temporarily stored data. The CPU 1706 is coupled to a system bus 1712 and can intercouple master and slave devices included in the processor-based system 1700. As is well known, the CPU 1706 communicates with these other devices by exchanging address, control, and data information over the system bus 1712. For example, the CPU 1706 can communicate bus transaction requests to a memory controller 1714, as an example of a slave device. Although not illustrated in
Other master and slave devices can be connected to the system bus 1712. As illustrated in
The CPU 1706 may also be configured to access the display controller(s) 1726 over the system bus 1712 to control information sent to one or more displays 1730. The display controller(s) 1726 sends information to the display(s) 1730 to be displayed via one or more video processor(s) 1732, which processes the information to be displayed into a format suitable for the display(s) 1730. The display(s) 1730 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
The IC chip 1702 also includes a throttle control circuit in a processor-based system on an IC chip configured to receive a throttle control signal and provide, to a plurality of processing segment circuits, selected activity control signals to control activity in a clock window of N consecutive clock cycles, including disabling activity in a number M of the N consecutive cycles based on the throttle control signal, including but not limited to the throttle control circuit and components thereof illustrated in
As shown in
The components of the RF transceiver 1804 and/or data processor 1806 can be split among multiple different die 1803(1), 1803(2). The data processor 1806 may include a memory to store data and program codes. The RF transceiver 1804 includes a transmitter 1808 and a receiver 1810 that support bi-directional communications. In general, the wireless communications device 1800 may include any number of transmitters 1808 and/or receivers 1810 for any number of communication systems and frequency bands. All or a portion of the RF transceiver 1804 may be implemented on one or more analog ICs, RF ICs, mixed-signal ICs, etc.
The transmitter 1808 or the receiver 1810 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage for the receiver 1810. In the direct-conversion architecture, a signal is frequency-converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communications device 1800 in
In the transmit path, the data processor 1806 processes data to be transmitted and provides I and Q analog output signals to the transmitter 1808. In the exemplary wireless communications device 1800, the data processor 1806 includes digital-to-analog converters (DACs) 1812(1), 1812(2) for converting digital signals generated by the data processor 1806 into the I and Q analog output signals, e.g., I and Q output currents, for further processing.
Within the transmitter 1808, lowpass filters 1814(1), 1814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion. Amplifiers (AMPs) 1816(1), 1816(2) amplify the signals from the lowpass filters 1814(1), 1814(2), respectively, and provide I and Q baseband signals. An upconverter 1818 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers 1820(1), 1820(2) from a TX LO signal generator 1822 to provide an upconverted signal 1824. A filter 1826 filters the upconverted signal 1824 to remove undesired signals caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) 1828 amplifies the upconverted signal 1824 from the filter 1826 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1830 and transmitted via an antenna 1832.
In the receive path, the antenna 1832 receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch 1830 and provided to a low noise amplifier (LNA) 1834. The duplexer or switch 1830 is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA 1834 and filtered by a filter 1836 to obtain a desired RF input signal. Downconversion mixers 1838(1), 1838(2) mix the output of the filter 1836 with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator 1840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1842(1), 1842(2) and further filtered by lowpass filters 1844(1), 1844(2) to obtain I and Q analog input signals, which are provided to the data processor 1806. In this example, the data processor 1806 includes analog-to-digital converters (ADCs) 1846(1), 1846(2) for converting the analog input signals into digital signals to be further processed by the data processor 1806.
In the wireless communications device 1800 of
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium wherein any such instructions are executed by a processor or other processing device, or combinations of both. As examples, the devices and components described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Implementation examples are described in the following numbered clauses:
1. An integrated circuit (IC) chip comprising a processor-based system, the processor-based system comprising:
-
- a plurality of processing segment circuits, each configured to operate in response to a clock signal; and
- a throttle control circuit comprising:
- a plurality of throttle administration circuits, each configured to receive a throttle control signal and generate a throttle select signal based on the throttle control signal, corresponding one of the first plurality of processing segment circuits; and
- a throttle sequence selection circuit configured to provide, to each of the first plurality of processing segment circuits, an activity control signal configured to throttle activity in the processing segment circuit in a first number (M) of cycles among a second number (N) of consecutive cycles of the clock signal based on a corresponding throttle select signal.
2. The IC chip of clause 1, each of the first plurality of processing segment circuits comprising at least one transistor circuit configured to change an output voltage state in response to the clock signal.
3. The IC chip of clause 1 or 2, each of the first plurality of processing segment circuits coupled to a same power rail to receive a power supply voltage.
4. The IC chip of any of clauses 1-3, each of the first plurality of processing segment circuits located adjacent to another one of the first plurality of processing segment circuits.
5. The IC chip of any of clauses 1-4, wherein:
- the throttle control signal indicates one of a third number (L) of throttle control values; and
- the third number (L) of throttle control values is equal to the first number (N) of consecutive clock cycles of the clock signal.
6. The IC chip of any of clauses 1-5, wherein the throttle select signal corresponding to one of the plurality of processing segment circuits is generated in one of the plurality of throttle administration circuits based on the throttle control signal and on configuration information corresponding to the processing segment circuit.
7. The IC chip of any of clauses 1-6, further comprising a configuration register configured to store, for each one of the plurality of processing segment circuits, configuration information corresponding to each of the throttle control values, wherein the throttle administration circuit is configured to, for a given throttle control value, determine the number M of cycles among the first number N of cycles, that activity in a corresponding one of the processing segment circuits is disabled based on the configuration information.
8. The IC chip of any of clauses 1-7, wherein each of the plurality of throttle administration circuits comprises a finite state machine having a fourth number (K) of states equal to the first number (N) of consecutive cycles of the clock signal.
9. The IC chip of clause 8, wherein: - each of the plurality of throttle administration circuits is configured to generate the throttle select signal having a throttle select value for each of the fourth number (K) of states; and
- an increase of the throttle select value corresponds to an increase of the second number (M) of cycles in which activity in the processing segment circuit is disabled among the first number (N) of consecutive cycles.
10. The IC chip of clause 9, wherein each of the plurality of throttle administration circuits is configured to increase, from one cycle to a next cycle, the throttle select value of the throttle select signal from a first throttle select value to any second throttle select value higher than the first throttle select value in response to a corresponding increase in the throttle control value.
11. The IC chip of clause 9 or 10, wherein each of the plurality of throttle administration circuits is configured to decrease, from one cycle to a next cycle, the throttle select signal from a first throttle select value to a second throttle select value that is lower than the first throttle select value by no more than a transition limit.
12. The IC chip of any of clauses 9-11 wherein, in response to the throttle control value staying the same or decreasing, each of the plurality of throttle administration circuits is configured to provide the second throttle select value for the first number (N) of consecutive cycles of the clock signal.
13. The IC chip of clause 11 or 12, wherein the transition limit is a configurable value stored in a configuration register.
14. The IC chip of any of clauses 1-13, further comprising a plurality of throttle sequence generators configured to generate sequence signals that are selected by the throttle select signals to be provided as the activity control signal, wherein plurality of throttle sequence generators are configured to generate the select signals to disable every number, from 0 to N−1, of the cycles of the number N of consecutive cycles.
15. The IC chip of any of clauses 1-14, wherein in response to the throttle control signal having a highest throttle control value, the throttle sequence selection circuit is configured to provide the activity control signal to disable activity in all but one cycle of the first number (N) of consecutive cycles.
16. The IC chip of any of clauses 1-15, wherein in response to the throttle control signal having a lowest throttle select value, the throttle sequence selection circuit is configured to provide the activity control signal to disable activity in none of the first number (N) of consecutive cycles.
17. The IC chip of any of clauses 1-16, the throttle sequence selection circuit comprising a plurality of multiplexors, each controlled by one of the throttle select signals generated by the plurality of throttle administration circuits, wherein each of the plurality of multiplexors comprises an output coupled to one of the plurality of processing segment circuits.
18. The IC chip of any of clauses 1-17, each of the plurality of processing segment circuits comprising an activity control circuit configured to receive the activity control signal and disable activity in a plurality of transistor circuits in the processing segment circuit, wherein disabling activity comprises gating the clock signal.
19. The IC chip of any of clauses 1-18, further comprising: - at least a second plurality of processing segment circuits; and
- at least a second throttle control circuit configured to control state changes in the at least a second plurality of processing segment circuits to manage power in response to detected power events.
20. The IC chip of any of clauses 1-19 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
21. A method of controlling activity in an integrated circuit (IC) chip comprising a processor-based system, the method comprising: - operating each of a plurality of processing segment circuits in response to a clock signal;
- receiving, in each of a plurality of throttle administration circuits, a throttle control signal;
- generating a throttle select signal corresponding one of the first plurality of processing segment circuits; and
- providing an activity control signal, based on the corresponding throttle select signal, to each of the first plurality of processing segment circuits in each cycle of a first number (N) of consecutive cycles of the clock signal, the activity control signal configured to disable operation in the processing segment circuit in a second number (M) of cycles among the first number (N) of consecutive cycles.
22. The method of clause 21, further comprising generating the throttle select signals in each one of the plurality of throttle administration circuits based on the throttle control signal and on a configuration setting corresponding to the processing segment circuit.
23. The method of clause 21 or 22, further comprising disabling, based on configuration settings in a configuration register, a different second number (M) of state changes among the first number (N) of consecutive cycles in a first one of the plurality of processing segment circuits than in the first number (N) of consecutive cycles in a second one of the plurality of processing segment circuits.
24. The method of any of clauses 21-23, wherein an increase of the throttle select value corresponds to an increase of the second number M of cycles in which state changes in the processing segment circuit are disabled among the first number N of consecutive cycles.
25. The method of any of clauses 21-24, further comprising increasing, from a first cycle to a second cycle, the throttle select value of the throttle select signal from a first throttle select value to a second throttle select value that is higher than the first throttle control value in response to a corresponding increase in the throttle control value.
26. The method of any of clauses 21-25, further comprising reducing, from a first cycle to a second cycle, the throttle select value of the throttle select signal from a first throttle select value to a second throttle select value that is less than the first throttle select value by no more than a transition limit in response to a corresponding decrease in the throttle control value.
27. The method of clause 26, further comprising, in response to the throttle control value staying the same or decreasing, providing, in each of the plurality of throttle administration circuits, the second throttle select value for the first number (N) of consecutive cycles of the clock signal before further reducing the throttle select signal to a third throttle select value that is less than the second throttle select value by not more than the transition limit.
28. A throttle control circuit comprising: - a plurality of throttle administration circuits, each configured to receive a throttle control signal and generate a throttle select signal based on the throttle control signal, corresponding one of a first plurality of processing segment circuits; and
- a throttle sequence selection circuit configured to provide, to each of the first plurality of processing segment circuits in each cycle of a first number (N) of consecutive cycles of the clock signal, an activity control signal configured to disable state changes in the processing segment circuit in a second number (M) of cycles among the first number of consecutive cycles based on the corresponding throttle select signal.
Claims
1. An integrated circuit (IC) chip comprising a processor-based system, the processor-based system comprising:
- a first plurality of processing segment circuits, each configured to operate in response to a clock signal; and
- a throttle control circuit comprising: a plurality of throttle administration circuits, each configured to receive a throttle control signal and generate a throttle select signal, based on the throttle control signal, to a corresponding one of the first plurality of processing segment circuits; and a throttle sequence selection circuit configured to provide, to each of the first plurality of processing segment circuits, an activity control signal configured to throttle activity in the processing segment circuit in a first number (M) of cycles among a second number (N) of consecutive cycles of the clock signal based on a corresponding throttle select signal.
2. The IC chip of claim 1, each of the first plurality of processing segment circuits comprising at least one transistor circuit configured to change an output voltage state in response to the clock signal.
3. The IC chip of claim 1, each of the first plurality of processing segment circuits coupled to a same power rail to receive a power supply voltage.
4. The IC chip of claim 1, each of the first plurality of processing segment circuits located adjacent to another one of the first plurality of processing segment circuits.
5. The IC chip of claim 1, wherein:
- the throttle control signal indicates one of a third number (L) of throttle control values; and
- the third number (L) of throttle control values is equal to the first second number (N) of consecutive clock cycles of the clock signal.
6. The IC chip of claim 1, wherein the throttle select signal corresponding to one of the first plurality of processing segment circuits is generated in one of the plurality of throttle administration circuits based on the throttle control signal and on configuration information corresponding to the processing segment circuit.
7. The IC chip of claim 5, further comprising a configuration register configured to store, for each one of the first plurality of processing segment circuits, configuration information corresponding to each of the third number (L) of throttle control values, wherein each throttle administration circuit of the plurality of throttle administration circuits is configured to, for a given throttle control value of the third number (L) of throttle control values, determine the first number (M) of cycles, among the second number (N) of consecutive cycles, in which activity in a corresponding one of the processing segment circuits is disabled based on the configuration information.
8. The IC chip of claim 5, wherein each of the plurality of throttle administration circuits comprises a finite state machine having a fourth number (K) of states equal to the second number (N) of consecutive cycles of the clock signal.
9. The IC chip of claim 8, wherein:
- each of the plurality of throttle administration circuits is configured to generate the throttle select signal having a throttle select value for each of the fourth number (K) of states; and
- an increase of the throttle select value corresponds to an increase of the first number (M) of cycles in which activity in the processing segment circuit is disabled among the second number (N) of consecutive cycles.
10. The IC chip of claim 9, wherein each of the plurality of throttle administration circuits is configured to increase, from one cycle to a next cycle, the throttle select value of the throttle select signal from a first throttle select value to a second throttle select value higher than the first throttle select value in response to a corresponding increase in the one throttle control value.
11. The IC chip of claim 9, wherein each of the plurality of throttle administration circuits is configured to decrease, from one cycle to a next cycle, the throttle select signal from a first throttle select value to a second throttle select value that is lower than the first throttle select value by no more than a transition limit.
12. The IC chip of claim 10 wherein, in response to the one throttle control value staying the same or decreasing, each of the plurality of throttle administration circuits is configured to provide the second throttle select value for the first second number (N) of consecutive cycles of the clock signal.
13. The IC chip of claim 11, wherein the transition limit is a configurable value stored in a configuration register.
14. The IC chip of claim 1, further comprising a plurality of throttle sequence generators configured to generate sequence signals that are selected by the throttle select signals to be provided as the activity control signal, wherein the plurality of throttle sequence generators is configured to generate the sequence signals having a first state for the first number (M) of cycles and having a second state for N−M cycles and the every number M ranges from 0 to N−1 among the sequence signals.
15. The IC chip of claim 5, wherein in response to the throttle control signal having a highest throttle control value of the third number (L) of throttle control values, the throttle sequence selection circuit is configured to provide the activity control signal to disable activity in all but one cycle of the second number (N) of consecutive cycles.
16. The IC chip of claim 9, wherein in response to the throttle control signal having a lowest throttle select value, the throttle sequence selection circuit is configured to provide the activity control signal to disable activity in none of the second number (N) of consecutive cycles.
17. The IC chip of claim 1, the throttle sequence selection circuit comprising a plurality of multiplexors, each controlled by one of the throttle select signals generated by the plurality of throttle administration circuits, wherein each of the plurality of multiplexors comprises an output coupled to one of the first plurality of processing segment circuits.
18. The IC chip of claim 1, each of the first plurality of processing segment circuits comprising an activity control circuit configured to receive the activity control signal and disable activity in a plurality of transistor circuits in the processing segment circuit, wherein disabling activity comprises gating the clock signal.
19. The IC chip of claim 1, further comprising:
- at least a second plurality of processing segment circuits; and
- at least a second throttle control circuit configured to control state changes in the at least a second plurality of processing segment circuits to manage power in response to detected power events.
20. The IC chip of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
21. A method of controlling activity in an integrated circuit (IC) chip comprising a processor-based system, the method comprising:
- operating each of a first plurality of processing segment circuits in response to a clock signal;
- receiving, in each of a plurality of throttle administration circuits, a throttle control signal;
- generating a throttle select signal to a corresponding one of the first plurality of processing segment circuits; and
- providing an activity control signal, based on the corresponding throttle select signal, to each of the first plurality of processing segment circuits in each cycle of a first second number (N) of consecutive cycles of the clock signal, the activity control signal configured to disable operation in the processing segment circuit in a first number (M) of cycles among the second number (N) of consecutive cycles.
22. The method of claim 21, further comprising generating the throttle select signals in each one of the plurality of throttle administration circuits based on the throttle control signal and on a configuration setting corresponding to the processing segment circuit.
23. The method of claim 21, further comprising disabling, based on configuration settings in a configuration register, a different first number (M) of state changes among the second number (N) of consecutive cycles in a first one of the first plurality of processing segment circuits than in a second one of the first plurality of processing segment circuits.
24. The method of claim 21, wherein an increase of a throttle select value of the throttle select signal corresponds to an increase of the first number (M) of cycles in which state changes in the processing segment circuit are disabled among the second number (N) of consecutive cycles.
25. The method of claim 24, further comprising increasing, from a first cycle to a second cycle, the throttle select value of the throttle select signal from a first throttle select value to a second throttle select value that is higher than the first throttle select value in response to a corresponding increase in a throttle control value of the throttle control signal.
26. The method of claim 24, further comprising reducing, from a first cycle to a second cycle, the throttle select value of the throttle select signal from a first throttle select value to a second throttle select value that is less than the first throttle select value by no more than a transition limit in response to a corresponding decrease in a throttle control value of the throttle control signal.
27. The method of claim 26, further comprising, in response to the throttle control value of the throttle control signal staying the same or decreasing, providing, in each of the plurality of throttle administration circuits, the second throttle select value for the first number (N) of consecutive cycles of the clock signal before further reducing the throttle select signal to a third throttle select value that is less than the second throttle select value by not more than the transition limit.
28. A throttle control circuit comprising:
- a plurality of throttle administration circuits, each configured to receive a throttle control signal and generate a throttle select signal, based on the throttle control signal, to a corresponding one of a first plurality of processing segment circuits; and
- a throttle sequence selection circuit configured to provide, to each of the first plurality of processing segment circuits in each cycle of a second number (N) of consecutive cycles of the clock signal, an activity control signal configured to disable state changes in the processing segment circuit in a first number (M) of cycles among the second number (N) of consecutive cycles based on the corresponding throttle select signal.
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Type: Grant
Filed: Jun 22, 2023
Date of Patent: Sep 9, 2025
Patent Publication Number: 20240427368
Assignee: QUALCOMM Incorporated (San Diego, CA)
Inventors: Sagar Koorapati (Austin, TX), Alon Naveh (Corte Madera, CA)
Primary Examiner: Brian T Misiura
Application Number: 18/339,478
International Classification: G06F 1/08 (20060101); G06F 1/3228 (20190101); G06F 1/324 (20190101);
