Patents by Inventor Alon Naveh

Alon Naveh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12287688
    Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.
    Type: Grant
    Filed: April 1, 2024
    Date of Patent: April 29, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Sagar Koorapati, Vinod Chamarty, Gaurav Sanjeev Kirtane, Pushkin Raj Pari, Nitin Makhija, Alon Naveh
  • Patent number: 12228988
    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: February 18, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Sagar Koorapati, Alon Naveh
  • Publication number: 20240427411
    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.
    Type: Application
    Filed: April 4, 2024
    Publication date: December 26, 2024
    Inventors: Vinod Chamarty, Sagar Koorapati, Alon Naveh
  • Publication number: 20240427396
    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Sagar Koorapati, Alon Naveh
  • Publication number: 20240427392
    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Vinod Chamarty, Sagar Koorapati, Sreeram Jayadev, Alon Naveh
  • Publication number: 20240427400
    Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.
    Type: Application
    Filed: April 1, 2024
    Publication date: December 26, 2024
    Inventors: Sagar Koorapati, Vinod Chamarty, Gaurav Sanjeev Kirtane, Pushkin Raj Pari, Nitin Makhija, Alon Naveh
  • Publication number: 20240427410
    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Vinod Chamarty, Sagar Koorapati, Alon Naveh
  • Publication number: 20240427393
    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.
    Type: Application
    Filed: April 4, 2024
    Publication date: December 26, 2024
    Inventors: Vinod Chamarty, Sagar Koorapati, Sreeram Jayadev, Alon Naveh
  • Publication number: 20240427397
    Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Sagar Koorapati, Vinod Chamarty, Gaurav Sanjeev Kirtane, Pushkin Raj Pari, Nitin Makhija, Alon Naveh
  • Publication number: 20240428024
    Abstract: Broadcasting power limiting management responses in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that includes a power estimation and limiting (PEL) circuit, a Limit Management Throughput Throttle (LMTT) source circuit, a plurality of activity management (AM) circuits, and an LMTT bus communicatively coupling the LMTT source circuit with each AM circuit of the plurality of AM circuits. The LMTT source circuit receives a power limiting management response from a PEL circuit via a communications network of the processor-based system, and generates an LMTT command based on the power limiting management response. The LMTT source circuit broadcasts the LMTT command to each AM circuit of the plurality of AM circuits via the LMTT bus.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Sagar Koorapati, Vinod Chamarty, Alon Naveh
  • Publication number: 20240427682
    Abstract: Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that that is configured to receive an input telemetry value from an input source circuit. The processor-based system converts the input telemetry value into a common format telemetry value, wherein a first unit value represented by a least significant bit of the common format telemetry value is greater than one (1) and is based on a quotient of a power of two (2) and a corresponding power of 10. The processor-based system then processes common format telemetry value.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Sagar Koorapati, Pradeep Kanapathipillai, Alon Naveh
  • Publication number: 20240427368
    Abstract: A throttle control circuit receives a throttle control signal for controlling power consumption in a plurality of processing segment circuits. The throttle control signal has a throttle control value based on throttle requests from monitoring circuits that have detected power-related events or conditions and correspond to a requested change in activity in the plurality of processing segment circuits. The throttle control circuit receives the throttle control signal in a plurality of throttle administration circuits that each generates a throttle select signal to select an activity control signal for a corresponding processing segment circuit. In each of a first number (N) of consecutive cycles of a clock signal, the activity control signal disables state changes in the corresponding processing segment circuit for a second number (M) of cycles among the first number (N) of consecutive cycles to reduce power consumption in the processing segment circuits.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Sagar Koorapati, Alon Naveh
  • Patent number: 11733757
    Abstract: An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: August 22, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Alon Naveh, Anubhav Mishra, Manu Gulati
  • Patent number: 11687139
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Publication number: 20220413581
    Abstract: This application is directed to power management at a processor system having a plurality of domains. Power samples are collected from the domains and combined to generate a system temperature profile including a temporal sequence of system temperature values. When the system temperature profile satisfies a first criterion, it is determined in real time whether a respective system temperature value of the system temperature profile satisfies a second criterion or a third criterion. In accordance with a determination that the respective system temperature value satisfies the second criterion, a power management engine determines power budgets of the domains on a firmware level and enables operations of the domains according to the power budgets. In accordance with a determination that the respective system temperature value satisfies the third criterion, a subset of domains are selected to apply a respective power throttling action directly on a hardware level.
    Type: Application
    Filed: March 22, 2022
    Publication date: December 29, 2022
    Inventors: Alon NAVEH, Anubhav MISHRA, Manu GULATI
  • Publication number: 20220413582
    Abstract: An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.
    Type: Application
    Filed: March 22, 2022
    Publication date: December 29, 2022
    Inventors: Alon NAVEH, Anubhav MISHRA, Manu GULATI
  • Patent number: 11467740
    Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 11, 2022
    Assignee: Intel Corporation
    Inventors: Inder M. Sodhi, Alon Naveh, Doron Rajwan, Ryan D. Wells, Eric C. Samson
  • Publication number: 20220214738
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Applicant: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Patent number: 11307628
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 19, 2022
    Assignee: INTEL CORPORATION
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Patent number: 11287871
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Oren Lamdan, Alon Naveh