Voltage regulator circuit built in a semiconductor memory device

Abstract

A voltage regulator circuit is disclosed which generates an output voltage obtained by adjusting a high voltage and has serially connected regulators of a two-stage structure. A regulator of a previous regulator adjusts the high voltage to a sufficiently constant voltage. A regulator of a next stage has a depletion-type NMOS transistor, and adjusts the high voltage to a voltage of a required level using a voltage adjusted by the regulator of the previous stage. According to this structure, an output voltage of the prevent voltage regulator circuit is clamped exactly at a voltage, which is identical to a sum of an absolute value of a threshold voltage of the depletion-type transistor and a voltage adjusted by the regulator of the previous stage, without overshooting over a required voltage level.

Description

[0001] This application relies from priority upon Korean Patent Application No. 2000-05360, filed on Feb. 3, 2000, the contents of which are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

[0002] The present invention relates to a nonvolatile storage device and, more particularly, to a voltage regulator for nonvolatile storage devices of the electrically erasable and programmable semiconductor type.

BACKGROUND OF THE INVENTION

[0003] As is well known, a nonvolatile storage device such as a flash memory device comprises an array of memory cells, each formed of a MOS transistor whose gate electrode, located over its channel region, is a so-called floating gate. This electrode has high DC impedance toward all the other terminals of the same cell and the circuit in which the cell is connected. The cell further comprises a second electrode, called the control gate electrode, which is driven by means of appropriate control voltages. The other electrodes of the transistor are known as its drain, source and bulk (or body) terminals.

[0004] By the application of appropriate voltage values to the cell terminals, the amount of charges present on the floating gate can be changed, e.g., utilizing phenomena known as Fowler-Nordheim's Tunneling and/or Channel Hot Electron Injection. This results in the transistor being placed in either of two logic states: a first state (referred to as “an OFF state”) of “high” threshold voltage (existing in a threshold voltage distribution of 6V to 7V), and a second state (referred to as “an ON state) of “low” threshold voltage (existing in a threshold voltage distribution of 1V to 3V).

[0005] Since the floating gate has high impedance toward any other terminals of the cell, the stored charge can persist therein for an indefinite length of time, even after the power supply voltage to the circuit, which contains it, has been cut off. The cell has, therefore, the characteristics of a nonvolatile memory.

[0006] Whether the memory cell has either one of the OFF and ON states, is judged by a read operation. During the read operation of each cell, a specified voltage (e.g., 4.5V) is applied to its control gate and a ground voltage is applied to its source. If the memory cell has the OFF state, no current flows from its drain to its source. This makes a voltage of a bit line increased, so that the memory cell is judged as the OFF state by a well-known sense amplifier (not shown). If the memory cell has the ON state, current flows from its drain to its source. This makes the voltage of the bit line lowered, and thereby the memory cell is judged as the ON state by the sense amplifier.

[0007] Referring to FIG. 1, there is illustrated a block diagram which shows a rough construction of a NOR-type flash memory device with a conventional voltage regulator. The memory device of FIG. 1 comprises an array 10 of memory cells arranged into a matrix of rows, called the word lines WL0 to WLi, and columns, called the bit lines BL0 to BLj. A voltage VPPi from a word line voltage generating circuit 30 is supplied to a word line WLi through a decoder 20 as a word line voltage (or a read voltage). The word line voltage generating circuit 30 consists of a high voltage generator 32 and a voltage regulator 34. The high voltage generator 32, which includes a booster circuit well known in the art, generates a higher voltage VPP than a power supply voltage in response to a boost enable signal EN as a control signal. The voltage regulator 34 adjusts the high voltage VPP so as to have a word line voltage VPPi of a required level. Herein, the high voltage VPP is maintained at the power supply voltage level when the boost enable signal EN is inactivated. A circuit diagram showing the voltage regulator 34 in FIG. 1 is illustrated in FIG. 2.

[0008] As illustrated in FIG. 2, a conventional voltage regulator 34 consists of a comparator COMP, a PMOS transistor MP1 used as a driver, and two resistors R1 and R2 used as a divider, which are connected as illustrated in the figure. The comparator COMP judges whether an output voltage Vdiv of the divider (R1 and R2) is lower than a reference voltage Vref, and the PMOS transistor MP1 operates according to a judgment result of the comparator COMP. For example, if, as a judgment result of the voltage regulator 34, the voltage VPPi is lower than a required voltage level (Vref>Vdiv), the PMOS transistor MP1 supplies current from the voltage VPP to an output terminal VPPi so that the output voltage VPPi is increased up to the required voltage level. On the other hand, if the voltage VPPi is higher than the required level (Vref<Vdiv), the current supply through the PMOS transistor MP1 is blocked so that the voltage VPPi is lowered up to the required voltage level.

[0009] As described above, the output voltage VPP of the high voltage generator 32 is maintained at the power supply voltage level when the boost enable signal EN is at an inactivation state. On the other hand, when the boost enable signal EN is at an activation state (t1, refer to FIG. 3), the high voltage generator 32 generates the high voltage VPP which is boosted fast from the power supply voltage in short time (e.g., several nanoseconds). The voltage regulator 34 adjusts the high voltage VPP thus generated so as to have the output VPPi of the required voltage level, that is, a word line voltage VWL. However, as illustrated in FIG. 2, the conventional voltage regulator 34 having a feedback scheme has a following problem.

[0010] Since the voltage VPPi adjusted by the voltage regulator 34 is always sensed, DC current path occurs between the high voltage VPP and the ground voltage. This causes the capacity of the high voltage to be reduced. Generally, as the resistors R1 and R2 forming the divider are designed so as to have relatively large values, the DC current between the high voltage VPP and the ground voltage is reduced. On the other hand, a response speed of the voltage regulator 34 is lowered according to an increase of a resistor value. Main cause of the response speed drop is RC delay owing to both a capacitance value of the PMOS transistor MP1 having large driving capacity and a resistance value of the divider.

[0011] For this, as illustrated in FIG. 3, the voltage VPPi adjusted by the voltage regulator 34 is not clamped exactly at a required voltage level. That is, the voltage VPPi is increased over the required voltage level between points of time t2 and t3, as illustrated in FIG. 3 (the overshot voltage level is determined according to RC delay time). The overshot voltage VPPi is applied to a selected word line WLi through the decoder 20 as a word line voltage VWL. As a result, since the word line voltage VWL is higher than a required voltage level, read fail (more particularly, read fail toward a memory cell of an OFF state) occurs. This is because the word line voltage VWL exists in a threshold voltage distribution of the OFF state or because sensing margin for the memory cell of the OFF state is reduced. Therefore, it is preferred to exactly clamp the voltage VPPi at a required voltage level without the overshooting of the voltage VPPi (in FIG. 3, a portion marked by a dotted line A).

SUMMARY OF THE INVENTION

[0012] It is therefore an object of the invention to provide a semiconductor memory device that has a voltage regulator circuit for supplying a voltage exactly clamped at a required voltage level.

[0013] It is another object of the invention to provide a voltage regulator circuit of a semiconductor memory device, which is capable of reducing DC current consumption.

[0014] In order to attain the above objects, according to an aspect of the present invention, there is provided a flash memory device that comprises a circuit for generating a word line voltage higher than a power supply voltage. The word line voltage generating circuit comprises a voltage regulator circuit, which is connected to a high voltage generator for generating a high voltage higher than the power supply voltage and has an output terminal for outputting an adjusted output voltage. The voltage regulator circuit consists of a first regulator for adjusting the high voltage to output a constant voltage lower than the adjusted output voltage, and a second regulator for adjusting the high voltage according to the constant voltage to output the adjusted output voltage. The second regulator consists of a depletion-type NMOS transistor having a drain connected to the high voltage, a source connected to the output terminal and a gate connected to receive the constant voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more complete appreciation of the present invention, and many of the attendant advantages thereof, will become readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:

[0016] FIG. 1 is a block diagram showing a rough construction of a flash memory device having a conventional voltage regulator;

[0017] FIG. 2 is a preferred embodiment showing a voltage regulator illustrated in FIG. 1;

[0018] FIG. 3 is a diagram showing a variation of an output voltage of a voltage regulator illustrated in FIG. 2;

[0019] FIG. 4 is a block diagram showing a flash memory device with a voltage regulator circuit according to the present invention;

[0020] FIG. 5 is a preferred embodiment of a voltage regulator illustrated in FIG. 4;

[0021] FIG. 6 is a diagram showing a variation of an output voltage of a voltage regulator illustrated in FIG. 5; and

[0022] FIGS. 7A and 7B are other embodiments of a voltage regulator illustrated in FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0023] The preferred embodiment of the invention will be more fully described with reference to the attached drawings.

[0024] According to a novel memory device of the present invention, a voltage regulator circuit is provided which is used in a word line voltage generating circuit. The regulator circuit generates an output voltage obtained by adjusting a high voltage, and includes serially connected regulators of a two-stage structure. A regulator of a previous stage adjusts the high voltage with a sufficiently constant voltage, wherein the sufficiently constant voltage is lower than the adjusted output voltage. And then, the regulator of a next stage adjusts the high voltage with a predetermined voltage level using a voltage adjusted by the regulator of the previous stage. In this embodiment, the regulator of the next stage consists of a depletion-type transistor having a negative threshold voltage. According to this construction, an output voltage of the voltage regulator circuit is clamped exactly at a voltage, which is identical to a sum of an absolute value of a threshold voltage of the depletion-type transistor and a voltage adjusted by the regulator of the previous stage, without the overshooting of the output voltage of the voltage regulator circuit.

[0025] A block diagram showing a rough configuration of a flash memory device having a voltage regulator circuit according to the present invention is illustrated in FIG. 4. The memory device in FIG. 4 comprises an array 100 of memory cells arranged in a matrix of rows (word lines WL0 to WLi) and columns (bit lines BL0 to BLj). A voltage VPPi from a word line voltage generating circuit 130 is supplied to a selected word line WLi through a decoder 120 as a word line voltage. The word line voltage generating circuit 130 consists of a high voltage generator 132 and a voltage regulator circuit 134. The high voltage generator 132, for example, consists of a well-known booster circuit, and generates a higher voltage than a power supply voltage in response to a boost enable signal EN. The voltage regulator circuit 134 adjusts the high voltage from the high voltage generator 132 to a predetermined word line voltage VPPi. Herein, the high voltage VPP is maintained at the power supply voltage when the boost enable signal EN is at an inactivation state.

[0026] The voltage regulator circuit 134 has a two-stage regulator structure. That is, the voltage regulator circuit 134 according to the present invention has a first voltage regulator 136 and a second voltage regulator that are connected in series. The first regulator 136 adjusts the high voltage VPP from the high voltage generator 132 so as to have a constant voltage V1, which is lower than a word line voltage VWL. The second regulator 138 clamps the high voltage VPP by use of the constant voltage V1 from the first regulator 136, and thus the clamped high voltage VPP is identical to a predetermined word line. A preferred embodiment of the voltage regulator circuit 134 is illustrated in FIG. 5.

[0027] Referring to FIG. 5, the voltage regulator circuit 134 comprises a first regulator 136, which consists of a depletion-type NMOS transistor DMN1, a load L1 and an NMOS transistor MN1, and a second regulator 138, which consists of a depletion-type NMOS transistor DMN2. The depletion-type NMOS transistor DMN1, whose gate is connected to a reference voltage Vref, has its drain (or, referred to as a first current electrode) connected to an output voltage, that is, a high voltage VPP of the high voltage generator 132. The source (or, referred to as a second current electrode) of the transistor DMN1 is grounded through the load L1 and the NMOS transistor MN1. The gate electrode (or, referred to as a control gate electrode) of the depletion-type NMOS transistor DMN2 is connected to the source of the depletion-type NMOS transistor DMN1 (or, one terminal of the load opposite to the ground voltage). The drain of the transistor DMN2 is connected to the high voltage VPP, and the source thereof is connected to an output terminal 139 for the voltage VPPi. The NMOS transistor MN1 of the first regulator 136 is turned on/off according to a boost enable signal EN. That is, the NMOS transistor MN1 is turned on when the high voltage generator 132 operates, and is turned off when the high voltage generator 132 does not operate. Therefore, while the high voltage generator 132 does not operate, the NMOS transistor MN1 blocks DC current path between the high voltage VPP and the ground voltage.

[0028] As illustrated in FIG. 5, the load L1 of the first regulator 136 can consist of a plurality of serially connected NMOS transistors. However, it is obvious to ones skilled in the art that the load L1 can be realized using other integrated circuit elements operating as a resistor.

[0029] As well known in the art, each of the depletion-type NMOS transistors DMN1 and DMN2 has a negative threshold voltage (−Vthd), and operates at a saturation region when a drain-to-source voltage Vds is identical to or more than a voltage (Vg−(−Vthd)). That is, the depletion-type NMOS transistors DMN1 and DMN2 are blocked (or become a shutoff state) at such a condition as Vds≧(Vg−(−Vthd)). According to this transistor characteristics, the voltage VPPi adjusted by the voltage regulator circuit 130 is exactly clamped (or adjusted) at the voltage (Vds≧Vg−(−Vthd)), which will be described more fully with reference to FIG. 6.

[0030] As illustrated in FIG. 6, when the high voltage generator 132 does not operate (the boost enable signal EN is maintained at a logic low level as an inactivation state), that is, during a period of time t0-t1, an output voltage VPP of the high voltage generator 132 is maintained at the power supply voltage Vcc. When the boost enable signal EN goes high as an activation state (t1), the output voltage VPP of the high voltage generator 132 is increased gradually and rapidly from the power supply voltage Vcc in short time (e.g., several nanoseconds). As the high voltage VPP is increased, the gate voltage of the depletion-type NMOS transistor DMN2 (or the source voltage of the transistor DMN1) is also increased.

[0031] After this, the drain-to-source voltage Vds of the depletion-type NMOS transistor DMN1 reaches a voltage Vref−(−Vthd1) (herein, −Vthd1 is a threshold voltage of the depletion-type NMOS transistor DMN1), the depletion-type NMOS transistor DMN1 is shut off. Therefore, the gate voltage V1 of the depletion-type NMOS transistor DMN2 becomes a voltage Vref+Vthd1. That is, the depletion-type NMOS transistor DMN1 adjusts (or clamps) the high voltage VPP so as to have the voltage Vref+Vthd1 at a point of time t2′. Herein, the voltage Vref+Vthd1 is higher than the power supply voltage Vcc and is lower than a predetermined word line voltage VWL.

[0032] The load L1 and the NMOS transistor MN1 of the first regulator 136 are used to prevent the source of the depletion-type NMOS transistor DMN1 from being floated. In the case that the load L1 and the NMOS transistor MN1 do not exist, the gate voltage V1 of the depletion-type NMOS transistor DMN2 is boosted when the source voltage of the depletion-type NMOS transistor DMN1 goes to a voltage Vref+Vthd1 (or, the transistor DMN1 is shut off). This makes the voltage VPPi set more highly than the required voltage level.

[0033] And then, when the output voltage VPP of the high voltage generator 132 reaches a word line voltage VWL at a point of time t2, the depletion-type NMOS transistor DMN2 is shut off. Thus, the voltage VPPi is clamped exactly at the word line voltage VWL of the required level. More particularly, as the high voltage VPP is increased over the constant voltage V1, the source voltage of the depletion-type NMOS transistor DMN2 is also increased. At this time, the depletion-type NMOS transistor DMN1 becomes shut off, and thus the source voltage V1 thereof is fixed to a voltage Vref+Vthd1. After this, the drain-to-source voltage Vds of the depletion-type NMOS transistor DMN1 reaches a voltage V1−(−Vthd2) (herein, −Vthd2 is a threshold voltage of the transistor DMN2) at a point of time t2′, the depletion-type NMOS transistor DMN2 becomes shut off. Therefore, the voltage VPPi, which is adjusted by the voltage regulator 134, is clamped to a voltage V1+Vthd2 by the depletion-type NMOS transistor DMN2. It is obvious to ones skilled in the art that adjusting the reference voltage Vref and the threshold voltages −Vthd1 and −Vthd2 varies the voltage VPPi.

[0034] According to the voltage regulator circuit 134 of the present invention having a two-stage regulator structure, the depletion-type NMOS transistor DMN2 is shut off when the high voltage VPP reaches a word line voltage VWL of a required voltage level. The voltage VPPi adjusted by the voltage regulator circuit 134 is exactly clamped without overshooting over a required level in a point of time t2′. Therefore, there are prevented problems (read fail and sense margin reduction owing to an increase of the word line voltage) owing to an overshoot of the voltage VPPi. Furthermore, there is blocked DC current path between the high voltage VPP and the ground voltage that occurs the conventional voltage regulator circuit illustrated in FIG. 2.

[0035] Other embodiments of the first regulator illustrated in FIG. 4 are shown in FIGS. 7A and 7B. Referring to FIG. 7A, the first regulator 136 consists of two PMOS transistors MP2 and MP3, two NMOS transistors MN2 and MN3 and a resistor R3, which are connected as illustrated in FIG. 7A. The first regulator 136 clamps the high voltage VPP at the constant voltage V1 when the boost enable signal EN is at a logic high level. The voltage V1 is higher than the power supply voltage Vcc and is lower than a word line voltage VWL of a required level. Similar to FIG. 5, since the second regulator 138 consists of a depletion-type NMOS transistor DMN2, the voltage VPPi is clamped exactly at a voltage V1+Vthd2 without overshooting. An operation associated with the second regulator is identical to that in FIG. 5, and description thereof is thus omitted. The first regulator in FIG. 7B is identical to that in FIG. 7A except that the resistor R3 is replaced with a diode-connected NMOS transistor MN5, and description thereof is thus omitted.

[0036] The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A voltage regulator circuit connected to a voltage booster for generating a high voltage VPP and having an output terminal for delivering a regulated output voltage VPPi, the voltage regulator comprising:

first means for receiving the high voltage VPP to produce a sufficiently constant voltage V1; and

second means including a driver, which is coupled between the high voltage and the output terminal, wherein the second means clamps the high voltage into the regulated output voltage which is such a voltage (V1+Vth) that the sufficiently constant voltage V1 is summed with a threshold voltage Vth of the driver.

2. The voltage regulator circuit according to

claim 1, wherein the driver comprises a depletion-type MOS transistor which has a first current electrode coupled to the high voltage, a second current electrode coupled to the output terminal and a control electrode coupled to receive the sufficiently constant voltage; and wherein the depletion-type MOS transistor is shut off when the adjusted output voltage reaches the voltage (V1+Vth).

3. The voltage regulator circuit according to

claim 2, wherein the first means comprises:

a second depletion-type MOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to the control electrode of the first depletion-type MOS transistor, and a control electrode coupled to receive a reference voltage; and

a switch coupled between the second current electrode of the second depletion-type MOS transistor and a ground voltage, the switch being switched according to a boost enable signal.

4. The voltage regulator circuit according to

claim 3, wherein the first means further comprises a load coupled between the second depletion-type MOS transistor and the switch.

5. The voltage regulator circuit according to

claim 1, wherein the first means comprises:

a first PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to a ground voltage via a first NMOS transistor which is switched according to a reference voltage, and a control electrode coupled to the second current electrode of the first PMOS transistor;

a second PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to the control electrode of the depletion-type MOS transistor, and a control electrode coupled to the control electrode of the first PMOS transistor; and

a second NMOS transistor having a first current electrode and a control electrode coupled to the control electrode of the depletion-type MOS transistor, and a second current electrode coupled to the ground voltage,

wherein the sufficiently constant voltage V1 is out from the second current electrode of the second PMOS transistor.

6. The voltage regulator circuit according to

claim 1, wherein the first means comprises:

a first PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to a ground voltage via a first NMOS transistor which is switched according to a reference voltage, and a control electrode coupled to the second current electrode of the first PMOS transistor;

a second PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to the control electrode of the depletion-type MOS transistor, and a control electrode coupled to the control electrode of the first PMOS transistor; and

a resistor coupled between the second current electrode of the second PMOS transistor and the ground voltage,

wherein the sufficiently constant voltage V1 is out from the second current electrode of the second PMOS transistor.

7. A semiconductor memory device comprising:

an array of memory cells arranged in rows and columns;

a row decoder for selecting one of the rows; and

a word line voltage generating circuit for generating a word line voltage to be supplied to the selected row,

wherein the word line voltage generating circuit includes a voltage booster for generating a high voltage; means for receiving the high voltage to produce a sufficiently constant voltage; and a depletion-type MOS transistor coupled between the high voltage and the row decoder.

8. The voltage regulator circuit according to

claim 8, wherein the depletion-type MOS transistor is shut off when the word line voltage reaches such a required voltage value that a value of the sufficiently constant voltage is summed with an absolute value of a threshold voltage of the depletion-type MOS transistor.

9. A voltage regulator circuit connected to a voltage booster for generating a high voltage VPP over a power supply voltage and having an output terminal for delivering a regulated output voltage VPPi, the voltage regulator comprising:

a first regulator for adjusting the high voltage VPP to output a sufficiently constant voltage V1 lower than the adjusted output voltage VPPi; and

a second regulator for adjusting the high voltage VPP according to the sufficiently constant voltage V1 to output the adjusted output voltage.

10. The voltage regulator circuit according to

claim 9, wherein the second regulator comprises a depletion-type NMOS transistor, the depletion-type NMOS transistor having a drain connected to the high voltage, a source connected to the output terminal and a gate connected to receive the sufficiently constant voltage.