Including Reference Or Bias Voltage Generator Patents (Class 365/189.09)
  • Patent number: 10416220
    Abstract: Even when parts having individual differences among identical parts or differences in deterioration speed between parts, or a part that does not have a non-volatile memory such as an EEPROM in a chip of the part itself, are mixed, there is no deterioration diagnosis device that can appropriately diagnose a state of deterioration due to temporal change or the like, because of which a mechanism (correction methodology) for evaluating and correcting deterioration in the precision or performance of an electronic part that has low precision or considerable temporal deterioration, and does not have a correction function, is incorporated in a deterioration diagnosis device, and a deterioration state is diagnosed using incorporated deterioration determination means when using a product after shipping.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masanori Kurimoto, Yuki Iwagami, Yoshitake Nishiuma, Takayuki Yanai
  • Patent number: 10416886
    Abstract: The data storage device includes scale-out storage devices and a controller configured to assign commands to the scale-out storage devices and re-assign the commands assigned to the scale-out storage devices based on state information output from a first scale-out storage device among the scale-out storage devices. Each of the scale-out storage devices includes a volatile memory device, a non-volatile memory device, and a scale-out controller configured to control the volatile memory device and the non-volatile memory device.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Ju Yi, Seok Won Ahn, Jun Ho Choi, Chan Ho Yoon
  • Patent number: 10409346
    Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
  • Patent number: 10403349
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 10403359
    Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
  • Patent number: 10396856
    Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip The first semiconductor chip includes a transmission circuit input unit, a transmission circuit unit, and a transmission unit. The second semiconductor chip includes a reception unit, a reception circuit unit, and a reception circuit output unit. The transmission unit and the reception unit can communicate with each other in a non-contact manner. A transmission circuit unit input signal having a predetermined transmission-side potential is input into the transmission circuit unit. A reception circuit unit input signal is input into the reception circuit unit via the non-contact communication between the transmission unit and the reception unit. The reception circuit unit outputs a reception circuit unit output signal having a predetermined reception-side potential. The ratio of the reception-side potential to the transmission-side potential can be changed.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 27, 2019
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10388387
    Abstract: A memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages suitable for storing data; and a controller suitable for receiving a plurality of commands from a host, performing a plurality of command executions on the plurality of memory blocks in response to the plurality of commands, checking parameters of the plurality of memory blocks according to the plurality of command executions performed on the plurality of memory blocks, selecting first memory blocks among the plurality of memory blocks according to the parameters, and copying data stored in the first memory blocks to second memory blocks among the plurality of memory blocks.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Byeong-Gyu Park
  • Patent number: 10381101
    Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
  • Patent number: 10374595
    Abstract: An RF switch includes two or more coupled RF switch cells, each RF switch cell including a transistor having a first source/drain node, a second source/drain node, and a gate node, a first varactor is coupled between the first source/drain node and the gate node, and a second varactor is coupled between the second source/drain node and the gate node.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 6, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Winfried Bakalski
  • Patent number: 10366771
    Abstract: Aspects of the present disclosure include a memory system monitors at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among a plurality of logical blocks. The memory system disassembles the first logical block among the plurality of logical blocks when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range, and the second physical block having an erasing time length or a programming time length falling outside the first range.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazutaka Takizawa, Masaaki Niijima
  • Patent number: 10354718
    Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja
  • Patent number: 10338817
    Abstract: Storage divisions are selected for garbage collection by use of a first selection criterion that is based on an amount of storage capacity freed by reclaiming the respective storage divisions. The first selection criterion may be overridden by a second, different selection criterion in response to determining that a wear variance of the storage divisions exceeds a threshold. The second selection criterion may select a storage division to reclaim based on a wear-level of the storage division. Overrides of the first selection criterion may be limited to a particular override frequency and/or period. The first selection criterion may comprise a logarithmic comparison of the amount of invalid data within the storage divisions. The amount of invalid data in a storage division may be calculated in terms of recovery blocks, having a size that exceeds the size of the physical storage locations within the storage divisions.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Jim Peterson, Michael Callahan
  • Patent number: 10340008
    Abstract: In one embodiment, an electronic device includes a power supply circuit that has a first switch circuit between a power supply line and a ground potential. The first switch circuit connects the power supply line to the ground potential upon receipt of a control signal that is supplied when a supply of power on the power supply line is cut off. A capacitor is connected between the power supply line and the ground potential. A second switch circuit is between the capacitor and the power supply line. The second switch circuit is configured to disconnect the capacitor from the power supply line upon receipt of the first control signal. A controller circuit is configured to supply the first control signal when the supply of power on the power supply line is cut off.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuma Kawamura, Naoki Kimura
  • Patent number: 10339995
    Abstract: Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-geun Do, Jong-ho Lee, Chan-yong Lee, Min-soo Jang
  • Patent number: 10320288
    Abstract: A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Christopher P Miller
  • Patent number: 10319417
    Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojiang Guo, Qiang Tang
  • Patent number: 10319865
    Abstract: A pressure detecting includes a plurality of sensing cells arranged a plurality of rows and columns, each of the plurality of sensing cells including a pressure sensing element and a selection transistor. First driving signal lines are disposed in the rows, and the first driving signal lines are connected to the selection transistors of a first portion of the plurality of sensing cells in a respective row. Second driving signal lines are disposed in a portion of the plurality of rows, and the second driving signal lines are connected to the selection transistors of a second portion of the plurality of sensing cells in a respective row. First and second driving circuits are respectively connected to the first driving signal lines the second driving signal lines.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 11, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Katsuyoshi Hiraki, Osamu Sato, Kazuki Watanabe
  • Patent number: 10311946
    Abstract: The semiconductor memory device includes: a memory cell; a sensing circuit connected to the memory cell via a first bit line and a second bit line different from the first bit line, the sensing circuit configured to sense data stored in the memory cell; and a bit line voltage control circuit connected to the memory cell via the first bit line and the second bit line, the bit line voltage control circuit configured to precharge the first bit line to a first voltage that is lower than a supply voltage and to precharge the second bit line to a second voltage that is lower than the supply voltage and is different from the first voltage.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 4, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Han-Wool Jeong, Woo-Jin Rim, Tae-Joong Song, Seong-Ook Jung, Gyu-Hong Kim
  • Patent number: 10311819
    Abstract: The invention provides a CMOS GOA circuit, comprising a signal processing module having a first and a second TFTs, the first TFT having a gate connected to a first control signal, a source connected to an output node and a drain connected to a third node; the second TFT having a gate and a source connected to a second control signal, and a drain connected to the third node; the first and second control signals having opposite phases, the first and second control signals controlling the first and second TFTs to turn on alternatingly inputting a voltage signal of the output node or a second control signal to the third node. Compared to the known technique using NAND circuit, the invention reduces the number of TFTs required by latch module without affecting operation of the circuit, and facilitates the implementation of the ultra-narrow border or borderless display products.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: June 4, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shijuan Yi
  • Patent number: 10282289
    Abstract: A package module may be provided. The package module may include a first chip and a second chip. The first chip may be configured to receive first pattern data to generate first transmission data in a first write mode. The second chip may be configured to receive the first transmission data to generate and output first sense data in a first read mode.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Hak Song Kim, Min Su Park
  • Patent number: 10275017
    Abstract: A power circuit and a memory device using the same are provided. The power circuit is used for providing an operating voltage to a memory array, and includes a voltage regulator circuit and a voltage feedback circuit. The voltage regulator circuit receives a system voltage to provide the operating voltage. The voltage feedback circuit is coupled to the voltage regulator circuit to receive the operating voltage, and receives a data locking voltage, wherein the voltage feedback circuit has a non-volatile memory element which is set or reset in response to the data locking voltage. The voltage feedback circuit is set or reset based on the non-volatile memory element to provide a feedback voltage to the voltage regulator circuit, so as to set an output level of the operating voltage.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: April 30, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Cheng-Chih Wang, Hsi-Jung Tsai
  • Patent number: 10276219
    Abstract: In one embodiment, an apparatus comprises a first connector to couple to a connector of a memory card, the memory card comprising a first sense node to sense a supply voltage at a first location of the memory card, the first connector comprising a voltage supply pin; a ground pin; and a sense pin to couple to the first sense node; a first sense line to couple to the first sense node through the sense pin; and a voltage regulator coupled to the first sense line, the voltage regulator to provide the supply voltage based on feedback received from the first sense node of the memory card via the first sense line.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: George Vergis, Dat Le
  • Patent number: 10255972
    Abstract: A memory system includes a non-volatile memory and a controller configured to perform a read re-try in response to a failed normal read. The read re-try includes a first read of data at a first read voltage, a second read of data at a second read voltage obtained by shifting the first read voltage by a first shift amount, which is determined according to a bit count value obtained by counting a number of predetermined bit values in the first read, a third read of data carried out a plurality of times at a plurality of third read voltages, wherein each of the plurality of third read voltages are shifted from each other by a second shift amount, and a final read of data at a read voltage that is set closer to the second read voltage than the first read voltage.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Nobuaki Sato
  • Patent number: 10250132
    Abstract: A voltage system and a method of operating a voltage system are provided. The voltage system includes an oscillator and a pump device. The oscillator is configured to provide an oscillation signal exhibiting a first frequency when a voltage level of a supply voltage is greater than a reference voltage level, and to provide the oscillation signal exhibiting a second frequency greater than the first frequency when the voltage level of the supply voltage is less than the reference voltage level. The pump device is configured to provide the supply voltage, based on a frequency of the oscillation signal provided by the oscillator, by performing a charging operation.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 2, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chuan-Jen Chang, Ting-Shuo Hsu
  • Patent number: 10242724
    Abstract: Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Satoshi Yamanaka
  • Patent number: 10241909
    Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Masahiro Arai, Kazuhisa Fujimoto
  • Patent number: 10222996
    Abstract: The subject technology provides reduced overhead in Low Density Parity Check decoding operations. A method includes receiving a hard decode fail indication that decoding first raw data read from non-volatile memory in response to a first read command using a first set of voltages failed. The first read command comprises a first set of read operations. The method includes issuing to the non-volatile memory a second read command for the data using a second set of voltages. The second read command comprises a second set of read operations. The method includes issuing to the decoder, for processing in parallel with the second read command, at least one soft decoding request using soft information based on the first raw data. The method includes receiving from the decoder a success indication of successful decoding.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 5, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niang-Chu Chen, Jun Tao
  • Patent number: 10210933
    Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: February 19, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francois Tailliet, Marc Battista
  • Patent number: 10204906
    Abstract: An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Weimin Zhang, Yanzhong Xu
  • Patent number: 10192594
    Abstract: A semiconductor device includes a voltage hold circuit that raises a second boosted voltage with rise of an output voltage of a booster circuit that generates a first boosted voltage and then maintains the second boosted voltage at a point when the output voltage reaches a hold voltage level after that, and a first switch that short-circuits a first output terminal through which the first boosted voltage is output and a second output terminal through which the second boosted voltage is output until the output voltage reaches the hold voltage level.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masao Yamashiro, Tatsuya Bando, Kunitoshi Kamada, Hiroshi Sato
  • Patent number: 10191681
    Abstract: Example implementations relate to placing loads in a self-refresh mode using a shared backup power supply. For example, a shared backup power supply system can include a node coupled to a shared backup power supply. The node can include a plurality of loads that include volatile memory and a processing resource to place the plurality of loads in a self-refresh mode in response to a failure of a primary power supply. A shared backup power supply system can also include the shared backup power supply to provide backup power to the plurality of loads in the self-refresh mode in response to the failure of the primary power supply.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 29, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Hai Ngoc Nguyen, Han Wang, Patrick A. Raymond, Raghavan V. Venugopal
  • Patent number: 10192621
    Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Ken Matsubara, Takashi Iwase, Satoru Nakanishi
  • Patent number: 10175906
    Abstract: In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: January 8, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Naveen Muralimanohar, Erik Ordentlich, Cong Xu
  • Patent number: 10153032
    Abstract: The present disclosure provides a pump system of a DRAM and a method for operating the same. The pump system includes a pump device and a spare pump assembly. The pump device provides a current sufficient to allow a bank of the DRAM to operate at a normal refresh rate without other spare pump devices in response to a normal instruction which indicates that the bank is instructed to operate at the normal refresh rate. The spare pump assembly includes a first spare pump device configured to provide, in combination with the pump device, a current sufficient to allow the bank to operate at a first refresh rate greater than the normal refresh rate in response to a first instruction which indicates that the bank is instructed to operate at the first refresh rate.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: December 11, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 10147492
    Abstract: A non-differential sense amplifier circuit for reading out information in Non-Volatile Memories (NVMs) is disclosed. The circuit comprises a half latch, a PMOSFET device, a switch device and a reset transistor. The PMOSFET device has a source electrode connected to a digital voltage rail, a drain electrode connected to an output node of the half latch and a gate electrode connected to a bitline path coupled with a selected NVM cell. After the bitline path is pre-charged and the reset transistor is turned off, applying a read voltage to a word line related to the selected NVM cell causes a voltage at the gate electrode of the PMOSFET device to drop differently according to an electrical conductance state of the selected NVM cell. The disclosed circuitries can achieve extra low power consumption and high sensing speed compared to those in the conventional sensing scheme.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 4, 2018
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Patent number: 10140047
    Abstract: The data storage system includes a memory, a hard disk, and a processing unit. A first logical address and a second logical address in a first logical block of the memory correspond to a piece of duplicated data, and the duplicated data is stored in two physical pages in the hard disk. When executing a de-duplication command, the processing unit transfers the duplicated data to a physical page mapped to a third logical address in a second logical block of the memory; the physical page has a third physical address, and the processing unit updates a first mapping relationship to make it provide a mapping relationship between the first logical address and the third logical address and a mapping relationship between the second logical address and the third logical address, and stores the mapping relationship between the third logical address and the third physical address in the memory.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: November 27, 2018
    Assignee: ACCELSTOR, INC.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Patent number: 10110121
    Abstract: A charge pump includes a first unidirectional conducting device, a flying capacitor, a second unidirectional conducting device, an output capacitor, a first switch, and a second switch. The first unidirectional conducting device unidirectionally couples a supply voltage to an internal node. The flying capacitor is coupled between the internal node and a clock signal. The second unidirectional conducting device unidirectionally couples the internal node to an output node. The output capacitor is coupled between the output node and a ground. The first switch couples a discharge node to the ground according to a discharge signal. The second switch couples the output node to the discharge node according to the voltage of the internal node.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: October 23, 2018
    Assignee: FORTEMEDIA, INC.
    Inventors: Ion Opris, Abu Hena M Kamal, Lee Tay Chew, Shomo Chen
  • Patent number: 10084311
    Abstract: A voltage generator includes a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven, and a control signal generation unit suitable for activating the first voltage generation unit until the second power supply voltage reaches a specific level and activating the second voltage generation unit after the second power supply voltage reaches the specific level. The first voltage generation unit has less driving ability than the second voltage generation unit.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 25, 2018
    Assignee: SK Hynix Inc.
    Inventor: Young-Sub Yuk
  • Patent number: 10073623
    Abstract: A memory system, may include: a memory device including a plurality of memory blocks each including a plurality of stacked word lines; and a controller suitable for dividing the plurality of word lines into two or more word line groups according to heights thereof, programming data of a relatively high access frequency into a word line group having word lines of relatively low physical heights and data of a relatively low access frequency into a word line group having word lines of relatively high physical heights among the word line groups included in each of the memory blocks.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Byoung-Sung You
  • Patent number: 10056121
    Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: August 21, 2018
    Assignees: ARM Limited, The Regents of the University of Michigan
    Inventors: Mahmood Khayatzadeh, Massimo Bruno Alioto, David Theodore Blaauw, Dennis Michael Chen Sylvester, Fakhruddin Ali Bohra
  • Patent number: 10050044
    Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 14, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Ping Huang, Chun-Hsien Huang, Yu-Tse Kuo, Ching-Cheng Lung
  • Patent number: 10037802
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish
  • Patent number: 10026489
    Abstract: The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device having improved reliability includes an address decoder applying a program voltage to a selected word line coupled to selected memory cells, among the plurality of memory cells, and a read and write circuit applying a program permission voltage or a program inhibition voltage to bit lines coupled to the selected memory cells, and a control logic controlling the read and write circuit to sequentially apply the program permission voltage and the program inhibition voltage to the bit lines coupled to the selected memory cells when the program voltage is applied.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 17, 2018
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Hye Eun Heo
  • Patent number: 10018680
    Abstract: A semiconductor device, a battery monitoring system, and a method for activating the semiconductor device that may reduce current consumption in standby state. An integrated circuit (IC) of the semiconductor device includes an activation circuit that uses a ground of the IC as ground and a power source voltage of the IC as its power source, and a driving circuit that uses the power source voltage as ground and a boosted voltage output from a boosting circuit as its power source. In the IC, only the activation circuit enters an operation state in a standby state, and when recovered from the standby state, causes the activation circuit to make inner circuits of the IC enter the operation state based on an activation signal. When all the inner circuits enter the operation state, the driving circuit outputs the activation signal to the activation circuit of an upper IC.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: July 10, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hidekazu Kikuchi
  • Patent number: 10008259
    Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses are described. A memory includes an array of cells for storing data and a sense amplifier for controlling access to the array. The cells receive word line inputs for data access driven by a first voltage supply. The sense amplifier includes first precharge logic, which receives a first precharge input driven by the first power supply used by the array. Therefore, the first precharge input has similar timing characteristics as the word line input used in the array. The sense amplifier includes second precharge logic, which receives a second precharge input driven by a second power supply not used by the array and provides precharged values on bit lines driven by the second power supply.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: June 26, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ryan Thomas Freese
  • Patent number: 10002657
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory cell configured to operate in multiple retention states including a static retention state and a dynamic retention state. The integrated circuit may include a controller configured to selectively apply different voltage levels to the memory cell based on the retention state of the memory cell.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 19, 2018
    Assignee: The Regents of the University of Michigan
    Inventors: Byoungchan Oh, Sandunmalee Abeyratne, Ronald G. Dreslinski, Jr., Trevor Mudge
  • Patent number: 9993175
    Abstract: A pulsed ultra-wideband sensor comprises a control unit designed for forming a time delay of a synchronizing pulse, a probing signal forming path, a transmitting antenna, a receiving antenna, a path of a probing signal transmitter, with an output of said path being connected to the transmitting antenna, a path of a return signal receiver, with an input of the path being connected to the receiving antenna, and a first electronic switch. The input of the first electronic switch is connected to the output of the path for forming a probing signal, and its outputs—to the input of the path of the probing signal transmitter and to the path of a return signal receiver. The outputs of the channels for processing a return signal, which are parts of the path of the return signal receiver, are connected to the path for calculating a respiratory rate and a heart rate.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 12, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Teh Ho Tao, Igor Yakovlevich Immoreev, Maksim Vladimirovich Fesenko
  • Patent number: 9997228
    Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: June 12, 2018
    Assignee: SK hynix Inc.
    Inventors: Jae Seung Lee, Chang Hyun Kim, Yo Sep Lee
  • Patent number: 9978441
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 22, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Keiji Ikeda, Toshinori Numata, Tsutomu Tezuka
  • Patent number: 9977480
    Abstract: Selective coupling of power rails to memory domain(s) in processor-based system, such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional intentional decoupling capacitance in logic domain to mitigate voltage droops on logic power rail, power rail selection circuit is provided. The power rail selection circuit is configured to couple memory domain to a logic power rail when the logic power rail can satisfy a minimum operating voltage of memory arrays. The additional intrinsic decoupling capacitance of the memory arrays is coupled to the logic power rail. However, if the operating voltage of the logic power rail is scaled down below the minimum operating voltage of the memory arrays when the logic domain does not need higher operation functionality, the power rail selection circuit is configured to couple the memory domain to separate memory power rail.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yeshwant Nagaraj Kolla, Neel Shashank Natekar