Including Reference Or Bias Voltage Generator Patents (Class 365/189.09)
  • Patent number: 11183245
    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 11176887
    Abstract: The present disclosure relates to a display apparatus enhancing a display quality and a method of driving the display apparatus. The display apparatus comprises a display panel and a power voltage generator. The display panel comprises a plurality of pixels. The power voltage generator is configured to output a first initialization voltage, a second initialization voltage, a first power voltage, and a second power voltage less than the first power voltage to the plurality of pixels. The power voltage generator is configured to output the second initialization voltage substantially equal to the second power voltage in response to an emergency shutdown signal.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 16, 2021
    Inventors: Jung Deok Seo, Seung-Kyu Lee, Min Seong Son
  • Patent number: 11170828
    Abstract: A voltage generating circuit, a semiconductor storage device, and a bit line charging method thereof are provided. The voltage generating circuit includes: an INTVDD generating circuit for generating an internal power supply voltage INTVDD from an external power supply voltage EXVDD; a VDD_V1 generating circuit for generating an internal power supply voltage VDD_V1 from the external power supply voltage EXVDD; and a V1_driving circuit generating a charging voltage for charging the bit line at an output node by using the internal power supply voltage VDD_V1. The V1_driving circuit may generate voltages V1 having different driving capability. The V1_driving circuit charges the bit line with the voltage V1 having a weak driving capability during a first charging period of the bit line and charges the bit line with the voltage V1 having a strong driving capability during a second charging period.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 9, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Sho Okabe
  • Patent number: 11156505
    Abstract: A reconfigurable all-digital temperature sensor includes a NAND gate and several delay units, the NAND gate comprises two input terminals and an output terminal, one input terminal is used for external starting control signal; a plurality delay units are connected in series, the input end of the first delay unit is connected to the output terminal of the NAND gate, and the output end of the last delay unit is connected to another input terminal of the NAND gate, thereby forming a ring oscillator structure; each delay unit includes a leakage-based inverter and a Schmitt trigger, and the output end of the leakage-based inverter is connected to the input end of the Schmitt trigger. The reconfigurable all-digital temperature sensor can realize the conversion of temperature-leakage-frequency based on the ring oscillator structure in the temperature range of ?40˜125° C., thereby reducing the design complexity and achieving high accuracy.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: October 26, 2021
    Assignee: Semitronix Corporation
    Inventors: Zhong Tang, Yun Fang, Xiaopeng Yu, Zheng Shi
  • Patent number: 11158390
    Abstract: A method and apparatus for performing automatic power control in a memory device are provided. The method includes: during an initialization phase of the memory device, performing signal level detection on a reference clock request signal to determine whether the reference clock request signal is at a first predetermined voltage level or a second predetermined voltage level, for performing the automatic power control for the memory device, wherein the reference clock request signal is received through an IO pad; and according to a logic value carried by an input signal of a selective regulation circuit (SRC), performing selective power control to generate a secondary power voltage according to a main power voltage, wherein the selective power control makes the secondary power voltage be either equal to the main power voltage or a regulated voltage of the main power voltage in response to the logic value carried by the input signal.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 26, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Yu-Wei Chyan, Ping-Yen Tsai, Jiyun-Wei Lin
  • Patent number: 11126211
    Abstract: A chip package assembly and a chip function execution method thereof are provided. The chip package assembly includes a plurality of pins, and one of the plurality of pins is configured to receive a voltage signal. A processing circuit is configured to receive the voltage signal, where the processing circuit determines whether a voltage level of the voltage signal is a first level or a second level, to generate a first control signal according to the first level, and generate a second control signal according to the second level. A first functional circuit of a plurality of functional circuits executes a first function according to the first control signal, and a second functional circuit of the plurality of functional circuits executes a second function according to the second control signal.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: September 21, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Tsung-Peng Chuang
  • Patent number: 11119657
    Abstract: A storage controller coupled to a storage array comprising one or more storage devices receive a request to write data to one of the storage devices. The storage controller determines a first data block on the storage device comprising a list of deallocated data blocks on the storage device, the list comprising a block number of each deallocated data block and an access operation count value at which each deallocated data block was deallocated. The storage controller identifies a second data block from the list of deallocated data blocks on the storage device based on a corresponding access operation count value from the list and writes the data to the second data block.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 14, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: Nidhi Pankaj Doshi, Eric D. Seppanen, Neil Buda Vachharajani
  • Patent number: 11114154
    Abstract: Various implementations described herein are directed to a device having voltage generator circuitry that provides a temperature-compensated voltage. The device may include amplifier circuitry that receives the temperature-compensated voltage from the voltage generator circuitry and provides an output voltage based on the temperature-compensated voltage. The device may include voltage retention circuitry that receives the output voltage from the amplifier circuitry and provides a retention voltage to memory based on the output voltage.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 7, 2021
    Assignee: Arm Limited
    Inventors: Amit Chhabra, Shanuj Garg
  • Patent number: 11112455
    Abstract: Built-in self-test (BIST) circuits and related methods are disclosed. An example BIST circuit includes a state machine to generate a control signal to reduce a gate voltage associated with a transistor from a first voltage to a second voltage when an enable signal is asserted, the transistor to be enabled at the first voltage and the second voltage, and assert an alert signal when a gate-to-source voltage associated with the transistor satisfies a threshold when the gate voltage is reduced to the second voltage.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 7, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jacco van Oevelen
  • Patent number: 11114135
    Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses are also provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 7, 2021
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Gerald Barkley, Nicholas Hendrickson
  • Patent number: 11100973
    Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Donald M. Morgan
  • Patent number: 11094592
    Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars. The sacrificial structures comprise an isolated sacrificial structure in a slit region and connected sacrificial structures in a pillar region. Tiers are formed over the sacrificial structures and support pillars, and a portion of the tiers are removed to form tier pillars and tier openings, exposing the connected sacrificial structures and support pillars. The connected sacrificial structures are removed to form a cavity, a portion of the cavity extending below the isolated sacrificial structure. A cell film is formed over the tier pillars and over sidewalls of the cavity. A fill material is formed in the tier openings and over the cell film. A portion of the tiers in the slit region is removed, exposing the isolated sacrificial structure, which is removed to form a source opening. The source opening is connected to the cavity and a conductive material is formed in the source opening and in the cavity.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Matthew J. King, Indra V. Chary, Darwin A. Clampitt
  • Patent number: 11081148
    Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
  • Patent number: 11079787
    Abstract: A semiconductor apparatus includes a voltage divider, a plurality of reference voltage controllers, and a plurality of receivers. The voltage divider outputs a plurality of division voltages. Each of the plurality of reference voltage controllers is configured to receive in common the plurality of division voltages. Each of the plurality of receivers is configured to receive data by utilizing at least one reference voltage. The plurality of reference voltage controllers are coupled to the plurality of receivers in a one-to-one manner, and each of the plurality of reference voltage controllers is configured to select at least one division voltage among the plurality of division voltages and provide the one division voltage as the at least one reference voltage to a corresponding receiver among the plurality of receivers.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyu Bong Kong, Jae Hyeok Yang, Gang Sik Lee
  • Patent number: 11069690
    Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 20, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Shih-Kuei Yen, Li-Wei Liu, Le-Tien Jung, Hung-Lin Shih, Hsuan-Tung Chu, Ming-Che Li, Guan-Yi Liou, Huai-Jin Hsing
  • Patent number: 11062189
    Abstract: A flag holding circuit includes: a flag setting part connected to a voltage supply line and charging a capacitor according to an input signal; a flag determination part outputting an output signal based on a charging voltage of the capacitor; and a discharging part discharging the capacitor. The flag setting part includes: a switch having a first terminal connected to a connection line between the flag determination part and the discharging part and a second terminal connected to the voltage supply line or a grounding line according to a signal level of the input signal, and connecting or disconnecting the voltage supply line or the grounding line with the connection line according to a leakage control signal; and a switch control part, generating the leakage control signal whose signal level changes to be greater than a power supply voltage according to a clock signal and supplying it to the switch.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: July 13, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Tetsuaki Yotsuji
  • Patent number: 11062779
    Abstract: A data processing system includes a memory device, a predetermined voltage generating circuit and a reference voltage generating circuit. The memory device stores system data and operates based on a system high voltage. The predetermined voltage generating circuit is coupled to the memory device and generates a predetermined voltage having a target voltage level according to a reference voltage. The target voltage level is the voltage level required for performing a write operation or an erase operation of the memory device. The reference voltage generating circuit generates the reference voltage. A voltage generator of the reference voltage generating circuit is enabled or disabled in response to a write protection signal, so as to selectively output the reference voltage. When the voltage generator is disabled, the reference voltage will not be output and the predetermined voltage having a target voltage level will accordingly not be generated.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 13, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Cheng-Chih Wang
  • Patent number: 11042313
    Abstract: Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gerald Barkley, Poorna Kale
  • Patent number: 11029355
    Abstract: A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: June 8, 2021
    Assignee: THE BOEING COMPANY
    Inventors: Mark Yao, Manuel F. Cabanas-Holmen, Ethan H. Cannon
  • Patent number: 11029861
    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Patent number: 10997322
    Abstract: An apparatus is provided to enable power supply input to be isolated from power supply output. Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply. The first charge store can be charged from the power input whilst isolated from the power output. The second charge store can be discharged to the power output, while isolated from the power input.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: May 4, 2021
    Assignee: Arm Limited
    Inventors: Adeline-Fleur Fleming, Carl Wayne Vineyard, George Mcneil Lattimore, Christopher Neal Hinds, Robert John Harrison, Mikael Rien, Abdellah Bakhali, Robert Christiaan Schouten, Jean-Charles Bolinhas
  • Patent number: 10990465
    Abstract: A method of writing data into a memory device discloses utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank. The method further comprises searching for a data word that is awaiting write verification in the error buffer, wherein the verify operation occurs in a same row as the write operation. The method also comprises determining if an address of the data word is proximal to an address for the write operation and responsive to a positive determination, delaying a start of the verify operation so that a rising edge of the verify operation occurs a predetermined delay after a rising edge of the write operation.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 27, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Benjamin Louie, Neal Berger, Lester Crudele
  • Patent number: 10984876
    Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
  • Patent number: 10984854
    Abstract: Signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. Pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 20, 2021
    Inventor: Atul Katoch
  • Patent number: 10964383
    Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: March 30, 2021
    Assignees: Jiangsu Advanced Memory Technology Co., Ltd., ALTO MEMORY TECHNOLOGY CORPORATION
    Inventors: Jui-Jen Wu, Fan-Yi Jien
  • Patent number: 10949100
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 16, 2021
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Patent number: 10950298
    Abstract: A static random access memory (SRAM) device includes a first memory array including a plurality of memory cells, each memory cell including a first pass gate transistor with a first threshold voltage connected to a bit line. The SRAM device further includes a second memory array including a plurality of memory cells, each memory cell including a second pass gate transistor with a second threshold voltage connected to the bit line. The SRAM device further includes a peripheral input-output circuit connected to the bit line. The SRAM device still further includes a column of write current tracking cells, each tracking cell disposed within a row of the first memory array and the second memory array, wherein the first memory array is between the peripheral input-output circuit and the second memory array.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 16, 2021
    Inventors: Wei-Chang Zhao, Hidehiro Fujiwara, Chih-Yu Lin
  • Patent number: 10942655
    Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 9, 2021
    Assignee: Seagate Technology LLC
    Inventors: Ludovic Danjean, Abdelhakim Alhussien, Sundararajan Sankaranarayanan, Erich Franz Haratsch
  • Patent number: 10930322
    Abstract: A regulator having improved voltage control capability may include a comparator, an output voltage generator, a voltage divider, and an output voltage controller. The comparator generates a comparison voltage by comparing a reference voltage with a feedback voltage. The output voltage generator generates an output voltage by using a power supply voltage, based on the comparison voltage. The voltage divider may include a first resistor and a second resistor, which generate the feedback voltage by dividing the output voltage. The output voltage controller adjusts a resistance value of at least one of the first resistor and the second resistor, based on a result of comparing the output voltage with a target voltage.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Bon Kwang Koo, Chi Hyun Kim, Kyu Tae Park, Tei Cho
  • Patent number: 10923064
    Abstract: A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 16, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yohei Takeuchi, Takuya Watanabe, Yasuaki Iwase, Akira Tagawa
  • Patent number: 10916286
    Abstract: A method of writing to a magnetic random access memory cell includes applying an alternating current signal to the magnetic random access memory cell having a first magnetic orientation, and applying a direct current pulse to the magnetic random access memory cell to change the magnetic orientation of the magnetic random access memory cell from the first magnetic orientation to a second magnetic orientation. The first magnetic orientation and the second magnetic orientation are different.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Duen-Huei Hou
  • Patent number: 10910071
    Abstract: There are provided a method of operating a voltage generator. The method includes providing a reference voltage, sensing a magnitude of a charge current for increasing voltages of a plurality of word lines based on the reference voltage, determining whether the sensed magnitude of the charge current is greater than a peak current value, increasing the reference voltage in accordance with a first slope when the sensed magnitude of the charge current is less than or equal to the peak current value, and increasing the reference voltage in accordance with a second slope less than the first slope when the detected magnitude of the charge current is greater than the peak current value.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-heon Baek, Ki-chang Jang, Dae-seok Byeon
  • Patent number: 10902935
    Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10902899
    Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, inc.
    Inventor: Christopher Kawamura
  • Patent number: 10896737
    Abstract: An object of the present invention is to increase a writing speed to a flash memory while suppressing an increase in noise. In the high-speed write mode, the memory controller simultaneously performs a first write operation with a second write current having a current value smaller than the first write current with respect to a second number of memory cells having a larger number than the first write current. At the completion of the first write operation, the memory controller simultaneously performs the second write operation by the third write current having a larger current value than the second write current with respect to the memory cell determined by the sense amplifier to have not completed the write operation in the determination process.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takanori Moriyasu, Kazuo Yoshihara, Akihiko Kanda, Yoshihiko Asai, Tomoya Ogawa
  • Patent number: 10885954
    Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 5, 2021
    Inventors: Sang-Yeop Baeck, Inhak Lee, SangShin Han, Tae-Hyung Kim, JaeSeung Choi, Sunghyun Park, Hyunsu Choi
  • Patent number: 10880103
    Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chen Lin, Shih-Lien Linus Lu, Wei Min Chan
  • Patent number: 10871919
    Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventors: Do-Sun Hong, Dong-Gun Kim, Yong-Ju Kim
  • Patent number: 10847508
    Abstract: An apparatus includes: a first substrate comprising a first current channel that includes a first plurality of doped regions on the first substrate; a second substrate comprising a second current channel that includes a second plurality of doped regions in the second substrate, wherein: the doped regions of the second substrate are physically separate from those of the first substrate, and the second current channel is aligned colinearly with the first current channel; and a conductive structure extending across the first substrate and the second substrate and electrically connecting matching doped regions of the first current channel and the second current channel.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Takashi Ishihara
  • Patent number: 10839879
    Abstract: The present application relates to a memory device. The memory device includes a magnetic tunnel junction (MTJ) current path, a reference current path in parallel with the MTJ current path, and a bias current path in parallel with the MTJ current path and the reference current path. The MTJ current path includes a MTJ memory cell configured to switch between a first data state and a second data state. The reference current path includes a reference memory cell. The bias current path is configured to bias the MTJ current path and the reference current path during read operations so the MTJ current path and the reference current path each carry a current level when the first state is read from the MTJ memory cell and each carry the current level when the second state is read from the MTJ memory cell.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, Chung-Te Lin, Katherine Chiang
  • Patent number: 10833664
    Abstract: An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 10, 2020
    Assignee: Apple Inc.
    Inventors: Greg M. Hess, Hemangi U. Gajjewar, Sachmanik Cheema
  • Patent number: 10825488
    Abstract: In accordance with the present disclosure, a data sensing circuit of a semiconductor apparatus includes a sensing portion configured to sense and amplify an input signal provided through an activated data line between a first data line and a second data line. The data sensing circuit also includes an offset sampling portion configured to generate a second offset voltage by sampling a first offset voltage of one to be activated between the first data line and the second data line and configured to store the second offset voltage into a parasitic capacitor of the other one between the first data line and the second data line.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Min Ho Yun
  • Patent number: 10811079
    Abstract: A semiconductor memory apparatus includes a memory cell unit and an internal voltage stabilization apparatus. The memory cell unit includes a row decoder, a column decoder, and a memory cell array. The internal voltage stabilization apparatus includes an operation termination determination unit configured to determine whether an operation of the semiconductor memory apparatus is terminated on the basis of an external input voltage and output an operation termination command, a termination voltage generation unit configured to generate a termination voltage having a preset voltage value on the basis of a determination result of operation termination by the operation termination determination unit, and a switch unit. The switch unit includes a plurality of switches that are turned in response to the operation termination command, and supplies the termination voltage, input from the termination voltage generation unit, to a plurality of internal nodes of the memory cell array.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Min Park, Dae Sun Kim, In Cheol Nam, Chang Soo Lee, Jin Seok Jeong
  • Patent number: 10811963
    Abstract: A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Xiaoqun Liu, Madan Mohan Reddy Vemula
  • Patent number: 10803962
    Abstract: A semiconductor package includes an external power supply node, a current monitoring node, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies includes a first circuit and a second circuit. The first circuit is configured to supply a first operating current to that semiconductor die from the external power supply node. The second circuit is configured to mirror the first operating current on a reduced scale and output the mirrored first operating current to the current monitoring node. The mirrored first operating current from each semiconductor die of the plurality of semiconductor dies is summed on the current monitoring node.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tomoharu Tanaka
  • Patent number: 10803932
    Abstract: According to one embodiment, a storage device includes: a memory cell including a storage component to which a plurality of data values are allowed to set in response to a plurality of resistance values of the storage component and a selector connected in series to the storage component; a word line configured to provide a signal to select the memory cell; a bit line configured to receive a data signal from the memory cell; a first conversion circuit configured to nonlinearly convert a first current, generated in response to the data signal input to the bit line, into a first voltage; and a comparison circuit configured to compare the first voltage, converted by the first conversion circuit, with a plurality of reference voltages.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Takahiko Iizuka
  • Patent number: 10796773
    Abstract: A memory device includes a memory array, a plurality of voltage generation systems, and a controller. The memory array includes a plurality of planes. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technolgy, Inc.
    Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
  • Patent number: 10789162
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks and a controller. The controller manages a garbage collection count for each of blocks containing data written by a host, the garbage collection count indicating the number of times the data in said each of the blocks has been copied by a garbage collection operation of the nonvolatile memory. The controller selects, as garbage collection target blocks, first blocks associated with a same garbage collection count. The controller copies valid data in the first blocks to a copy destination free block. The controller sets, as a garbage collection count of the copy destination free block, a value obtained by adding one to a garbage collection count of the first blocks.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10782728
    Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 22, 2020
    Assignee: Ambiq Micro, Inc.
    Inventor: Scott Hanson
  • Patent number: 10768857
    Abstract: A storage system, includes a controller and a solid state disk. The controller creates multiple segments in advance, selects a first die from the multiple dies, selects a first segment from the multiple segments, determines an available offset of the first segment, generates a write request, where the write request includes a write address, target data, and a data length of the target data, and the write address includes an identifier of a channel coupled to the first die, an identifier of the first die, an identifier of the first segment, and the available offset, and sends the write request to the solid state disk. The solid state disk receives the write request, and stores the target data according to the write address and the data length.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 8, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Meng Zhou, Kun Tang, Jui-Yao Yang, Jea Woong Hyun