Including Reference Or Bias Voltage Generator Patents (Class 365/189.09)
  • Patent number: 10839879
    Abstract: The present application relates to a memory device. The memory device includes a magnetic tunnel junction (MTJ) current path, a reference current path in parallel with the MTJ current path, and a bias current path in parallel with the MTJ current path and the reference current path. The MTJ current path includes a MTJ memory cell configured to switch between a first data state and a second data state. The reference current path includes a reference memory cell. The bias current path is configured to bias the MTJ current path and the reference current path during read operations so the MTJ current path and the reference current path each carry a current level when the first state is read from the MTJ memory cell and each carry the current level when the second state is read from the MTJ memory cell.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, Chung-Te Lin, Katherine Chiang
  • Patent number: 10833664
    Abstract: An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 10, 2020
    Assignee: Apple Inc.
    Inventors: Greg M. Hess, Hemangi U. Gajjewar, Sachmanik Cheema
  • Patent number: 10825488
    Abstract: In accordance with the present disclosure, a data sensing circuit of a semiconductor apparatus includes a sensing portion configured to sense and amplify an input signal provided through an activated data line between a first data line and a second data line. The data sensing circuit also includes an offset sampling portion configured to generate a second offset voltage by sampling a first offset voltage of one to be activated between the first data line and the second data line and configured to store the second offset voltage into a parasitic capacitor of the other one between the first data line and the second data line.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Min Ho Yun
  • Patent number: 10811079
    Abstract: A semiconductor memory apparatus includes a memory cell unit and an internal voltage stabilization apparatus. The memory cell unit includes a row decoder, a column decoder, and a memory cell array. The internal voltage stabilization apparatus includes an operation termination determination unit configured to determine whether an operation of the semiconductor memory apparatus is terminated on the basis of an external input voltage and output an operation termination command, a termination voltage generation unit configured to generate a termination voltage having a preset voltage value on the basis of a determination result of operation termination by the operation termination determination unit, and a switch unit. The switch unit includes a plurality of switches that are turned in response to the operation termination command, and supplies the termination voltage, input from the termination voltage generation unit, to a plurality of internal nodes of the memory cell array.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Min Park, Dae Sun Kim, In Cheol Nam, Chang Soo Lee, Jin Seok Jeong
  • Patent number: 10811963
    Abstract: A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Xiaoqun Liu, Madan Mohan Reddy Vemula
  • Patent number: 10803932
    Abstract: According to one embodiment, a storage device includes: a memory cell including a storage component to which a plurality of data values are allowed to set in response to a plurality of resistance values of the storage component and a selector connected in series to the storage component; a word line configured to provide a signal to select the memory cell; a bit line configured to receive a data signal from the memory cell; a first conversion circuit configured to nonlinearly convert a first current, generated in response to the data signal input to the bit line, into a first voltage; and a comparison circuit configured to compare the first voltage, converted by the first conversion circuit, with a plurality of reference voltages.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Takahiko Iizuka
  • Patent number: 10803962
    Abstract: A semiconductor package includes an external power supply node, a current monitoring node, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies includes a first circuit and a second circuit. The first circuit is configured to supply a first operating current to that semiconductor die from the external power supply node. The second circuit is configured to mirror the first operating current on a reduced scale and output the mirrored first operating current to the current monitoring node. The mirrored first operating current from each semiconductor die of the plurality of semiconductor dies is summed on the current monitoring node.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tomoharu Tanaka
  • Patent number: 10796773
    Abstract: A memory device includes a memory array, a plurality of voltage generation systems, and a controller. The memory array includes a plurality of planes. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technolgy, Inc.
    Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
  • Patent number: 10789162
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks and a controller. The controller manages a garbage collection count for each of blocks containing data written by a host, the garbage collection count indicating the number of times the data in said each of the blocks has been copied by a garbage collection operation of the nonvolatile memory. The controller selects, as garbage collection target blocks, first blocks associated with a same garbage collection count. The controller copies valid data in the first blocks to a copy destination free block. The controller sets, as a garbage collection count of the copy destination free block, a value obtained by adding one to a garbage collection count of the first blocks.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10782728
    Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 22, 2020
    Assignee: Ambiq Micro, Inc.
    Inventor: Scott Hanson
  • Patent number: 10768857
    Abstract: A storage system, includes a controller and a solid state disk. The controller creates multiple segments in advance, selects a first die from the multiple dies, selects a first segment from the multiple segments, determines an available offset of the first segment, generates a write request, where the write request includes a write address, target data, and a data length of the target data, and the write address includes an identifier of a channel coupled to the first die, an identifier of the first die, an identifier of the first segment, and the available offset, and sends the write request to the solid state disk. The solid state disk receives the write request, and stores the target data according to the write address and the data length.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 8, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Meng Zhou, Kun Tang, Jui-Yao Yang, Jea Woong Hyun
  • Patent number: 10748640
    Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 18, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
  • Patent number: 10741233
    Abstract: A semiconductor memory device comprises a first memory cell with a first variable resistance element. A first write controller is configured to write data into the first memory cell using a first voltage that is supplied via a first wiring. A second write controller configured to write data into the first memory cell using a second voltage that is lower than the first voltage when the first voltage supplied via the first wiring is reduced below a threshold level.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiro Takahashi, Ryousuke Takizawa
  • Patent number: 10719266
    Abstract: A controller includes: a processor suitable for controlling a memory device to read map data stored in a memory and read out a physical address corresponding to data requested by a host to be read; a counter suitable for obtaining reliability information on the map data stored in the memory; a determining unit suitable for activating a pre-pumping mode when reliability of the map data is poor; a deciding unit suitable for determining a first target die of a pre-pumping operation for reading the data in the activated pre-pumping mode; and a pumping unit suitable for controlling the memory device to perform the pre-pumping operation on the first target die during a background operation for reading out the physical address.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Byeong-Gyu Park, Hyunjun Kim, Byoung-Sung You
  • Patent number: 10718808
    Abstract: The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 21, 2020
    Assignee: AEHR TEST SYSTEMS
    Inventors: Steven C. Steps, Scott E. Lindsey, Kenneth W. Deboe, Donald P. Richmond, II, Alberto Calderon
  • Patent number: 10698463
    Abstract: A control unit included in a PLC generates power-cut retaining information to be retained at a power cut, and stores the generated power-cut retaining information into a main memory. The control unit includes a file system unit for reading and writing target information from and into a nonvolatile memory. When the file system unit receives a power cut notification indicating a cut of power fed while reading or writing target information from or into a nonvolatile memory, the file system unit stops the reading or writing process, and writes the power-cut retaining information stored in the main memory into the nonvolatile memory using power fed from the auxiliary power supply.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 30, 2020
    Assignee: OMRON Corporation
    Inventors: Takamasa Mioki, Mizuki Mori
  • Patent number: 10665296
    Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 26, 2020
    Assignees: Jiangsu Advanced Memory Technology Co., Ltd., ALTO MEMORY TECHNOLOGY CORPORATION
    Inventors: Jui-Jen Wu, Fan-Yi Jien
  • Patent number: 10666243
    Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 26, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Dai-Guo Xu, Gang-Yi Hu, Ru-Zhang Li, Jian-An Wang, Guang-Bing Chen, Yu-Xin Wang, Dong-Bing Fu, Tao Liu
  • Patent number: 10636491
    Abstract: A flash memory device includes a first memory cell, a second memory cell, a row decoder, and a bias generator. The first memory cell is a selected memory cell, and the second memory cell is an unselected memory cell connected with a bit line that is connected to the first memory cell. The row decoder controls a word line voltage to be applied to the first memory cell and controls an unselected source line voltage to be applied to the second memory cell. The bias generator generates the word line voltage based on a threshold voltage of a word line transistor changing with an ambient temperature and generates the unselected source line voltage based on a voltage level of the selected bit line.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoyoung Shin, Myeonghee Oh
  • Patent number: 10629277
    Abstract: There are provided a signal generation circuit and a semiconductor memory device including the same. The signal generation circuit includes: a signal input component configured to generate a first internal output signal and a second internal output signal in response to an input signal, and to adjust potential levels of the first internal output signal and the second internal output signal in response to an output signal; and a signal output component configured to generate the output signal in response to the first internal output signal and the second internal output signal.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Wan Chai, Young Sub Yuk
  • Patent number: 10600467
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10593375
    Abstract: According to one embodiment, a semiconductor storage device comprises a first memory cell including a first resistance change element; a first bit line and a first source line coupled to the first memory cell; and a first resistance coupled to at least one of the first bit line and the first source line.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuyo Ishii
  • Patent number: 10586790
    Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 10, 2020
    Assignee: Arm Limited
    Inventors: Pranay Prabhat, James Edward Myers
  • Patent number: 10566070
    Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, William J. Wilcox, Girish N. Cherussery
  • Patent number: 10546082
    Abstract: Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: January 28, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Armen Asatryan, Patrick Gibson, Grigor Geoletsyan
  • Patent number: 10510429
    Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-yong Choi, Kyung-ryun Kim, Woong-dai Kang, Hyun-chul Yoon
  • Patent number: 10475489
    Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo
  • Patent number: 10468074
    Abstract: A controller includes an input/output circuit and a reference voltage generating circuit. The input/output circuit includes a plurality of receiving circuits. Each receiving circuit receives and processes one data bit and generates an output bit accordingly. The reference voltage generating circuit is coupled to the input/output circuit and includes a plurality of circuit units for providing a plurality of reference voltages. One of the circuit units is coupled to one of the receiving circuits to provide a reference voltage to the corresponding receiving circuit and the receiving circuit processes the data bit according to the received reference voltage.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: November 5, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Minglu Xu, Fan Jiang, Jiajia Xia
  • Patent number: 10454466
    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Manoj Kumar Kumar Tiwari, Saiyid Mohammad Irshad Rizvi
  • Patent number: 10446233
    Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Qing Li, Xiaoli Hu, Wei Zhao, Jieyao Liu
  • Patent number: 10438644
    Abstract: Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Giuseppe Marotta, Marco Domenico Tiburzi
  • Patent number: 10439827
    Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chen Lin, Shih-Lien Linus Lu, Wei-Min Chan
  • Patent number: 10429913
    Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
  • Patent number: 10424364
    Abstract: A memory device includes a memory array, a switch device, and a controller. The switch device is arranged between a first voltage node and a second voltage node. The second voltage node is connected to the memory array. The controller is enabled to output a refresh mode signal, a refresh trigger signal, and a pre-start up signal. The memory device enters a self-refresh mode in response to the refresh mode signal. The memory device performs a self-refresh on the memory array in the self-refresh mode. In self-refresh mode, the controller outputs the pre-start up signal first prior to the refresh trigger signal to enable the switch device, so that the voltage of the second voltage node is increased to the voltage of the first voltage mode.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 24, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Feng Lin
  • Patent number: 10416886
    Abstract: The data storage device includes scale-out storage devices and a controller configured to assign commands to the scale-out storage devices and re-assign the commands assigned to the scale-out storage devices based on state information output from a first scale-out storage device among the scale-out storage devices. Each of the scale-out storage devices includes a volatile memory device, a non-volatile memory device, and a scale-out controller configured to control the volatile memory device and the non-volatile memory device.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Ju Yi, Seok Won Ahn, Jun Ho Choi, Chan Ho Yoon
  • Patent number: 10416220
    Abstract: Even when parts having individual differences among identical parts or differences in deterioration speed between parts, or a part that does not have a non-volatile memory such as an EEPROM in a chip of the part itself, are mixed, there is no deterioration diagnosis device that can appropriately diagnose a state of deterioration due to temporal change or the like, because of which a mechanism (correction methodology) for evaluating and correcting deterioration in the precision or performance of an electronic part that has low precision or considerable temporal deterioration, and does not have a correction function, is incorporated in a deterioration diagnosis device, and a deterioration state is diagnosed using incorporated deterioration determination means when using a product after shipping.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masanori Kurimoto, Yuki Iwagami, Yoshitake Nishiuma, Takayuki Yanai
  • Patent number: 10409346
    Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
  • Patent number: 10403359
    Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
  • Patent number: 10403349
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 10396856
    Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip The first semiconductor chip includes a transmission circuit input unit, a transmission circuit unit, and a transmission unit. The second semiconductor chip includes a reception unit, a reception circuit unit, and a reception circuit output unit. The transmission unit and the reception unit can communicate with each other in a non-contact manner. A transmission circuit unit input signal having a predetermined transmission-side potential is input into the transmission circuit unit. A reception circuit unit input signal is input into the reception circuit unit via the non-contact communication between the transmission unit and the reception unit. The reception circuit unit outputs a reception circuit unit output signal having a predetermined reception-side potential. The ratio of the reception-side potential to the transmission-side potential can be changed.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 27, 2019
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10388387
    Abstract: A memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages suitable for storing data; and a controller suitable for receiving a plurality of commands from a host, performing a plurality of command executions on the plurality of memory blocks in response to the plurality of commands, checking parameters of the plurality of memory blocks according to the plurality of command executions performed on the plurality of memory blocks, selecting first memory blocks among the plurality of memory blocks according to the parameters, and copying data stored in the first memory blocks to second memory blocks among the plurality of memory blocks.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Byeong-Gyu Park
  • Patent number: 10381101
    Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
  • Patent number: 10374595
    Abstract: An RF switch includes two or more coupled RF switch cells, each RF switch cell including a transistor having a first source/drain node, a second source/drain node, and a gate node, a first varactor is coupled between the first source/drain node and the gate node, and a second varactor is coupled between the second source/drain node and the gate node.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 6, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Winfried Bakalski
  • Patent number: 10366771
    Abstract: Aspects of the present disclosure include a memory system monitors at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among a plurality of logical blocks. The memory system disassembles the first logical block among the plurality of logical blocks when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range, and the second physical block having an erasing time length or a programming time length falling outside the first range.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazutaka Takizawa, Masaaki Niijima
  • Patent number: 10354718
    Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja
  • Patent number: 10339995
    Abstract: Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-geun Do, Jong-ho Lee, Chan-yong Lee, Min-soo Jang
  • Patent number: 10340008
    Abstract: In one embodiment, an electronic device includes a power supply circuit that has a first switch circuit between a power supply line and a ground potential. The first switch circuit connects the power supply line to the ground potential upon receipt of a control signal that is supplied when a supply of power on the power supply line is cut off. A capacitor is connected between the power supply line and the ground potential. A second switch circuit is between the capacitor and the power supply line. The second switch circuit is configured to disconnect the capacitor from the power supply line upon receipt of the first control signal. A controller circuit is configured to supply the first control signal when the supply of power on the power supply line is cut off.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuma Kawamura, Naoki Kimura
  • Patent number: 10338817
    Abstract: Storage divisions are selected for garbage collection by use of a first selection criterion that is based on an amount of storage capacity freed by reclaiming the respective storage divisions. The first selection criterion may be overridden by a second, different selection criterion in response to determining that a wear variance of the storage divisions exceeds a threshold. The second selection criterion may select a storage division to reclaim based on a wear-level of the storage division. Overrides of the first selection criterion may be limited to a particular override frequency and/or period. The first selection criterion may comprise a logarithmic comparison of the amount of invalid data within the storage divisions. The amount of invalid data in a storage division may be calculated in terms of recovery blocks, having a size that exceeds the size of the physical storage locations within the storage divisions.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Jim Peterson, Michael Callahan
  • Patent number: 10319865
    Abstract: A pressure detecting includes a plurality of sensing cells arranged a plurality of rows and columns, each of the plurality of sensing cells including a pressure sensing element and a selection transistor. First driving signal lines are disposed in the rows, and the first driving signal lines are connected to the selection transistors of a first portion of the plurality of sensing cells in a respective row. Second driving signal lines are disposed in a portion of the plurality of rows, and the second driving signal lines are connected to the selection transistors of a second portion of the plurality of sensing cells in a respective row. First and second driving circuits are respectively connected to the first driving signal lines the second driving signal lines.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 11, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Katsuyoshi Hiraki, Osamu Sato, Kazuki Watanabe
  • Patent number: 10319417
    Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojiang Guo, Qiang Tang