Method of wire bonding for small clearance

Abstract

A method of wire bonding for small clearance is disclosed. The method employs a conductive bump over the pad of the chip to prevent the capillary from colliding with the chip during the three-dimensional package wiring process The conventional constraint which limits the clearance to greater than 0.2 mm so as to find the appropriate capillary is overcome in this method.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a method of wire bonding for small clearance, and more specifically, to a method of employing a conductive bump over the pad of the chip to prevent the capillary from colliding with the chip during the three-dimensional package wiring process.

BACKGROUND OF THE INVENTION

[0002] At present, the commercialized electronic products have a trend with light-weight, and thin, short, and small size. Therefore, very large scale integrated circuit (VLSI) have been widely used. As the development of the semiconductor, the total number of transistors in the die greatly increases, and at the same time, the requirement the density of package becomes more and more strictly. The three dimensional package is thus developed to greatly increase the package density to overcome the issue.

[0003] However, during packaging, the pad of the chip is soldered to the lead frame by wiring, and when the chips are adhered in three dimensional manner, the capillary may collide with some higher chips to damage the chips and the capillary because the size of the chip is similar while wiring.

[0004] In the prior art, the steps of wiring comprises: (1) the capillary solders the wire on a pad by a thermal process or super sonic technique; (2) the capillary rises to form a vertical wire; (3) the capillary translates the wire to the lead frame; and (4) another end of the wire is soldered onto the lead frame.

[0005] For the process which needs a long wire, the reverse loop D has to add to the stroke of the capillary to enhance the characteristic of the wire. This step is out of question in single chip package wiring. However, in the three dimensional package wiring, the effect of the reverse loop D has to take into consideration, as shown in FIG. 1. The sizes of the upper and lower chips 11 and 12 are almost the same in package application. Therefore, when the two chips 11 and 12 are assembled together by soldering process, the capillary 14 may collide with the chip 11 to damage the capillary 14 and the chip 11 resulting in failure of wiring if the distance A from the pad 13 in the chip 12 to the rim of the chip 11 is very small and one of the reverse loop D, the radius C of the capillary, and the thickness E of the chip 11 is too big, or the distance A from the center of the pad in the chip 12 to the rim of the chip 11 is too small. The solution of the prior art is to select smaller capillary 14. However, there is a disadvantage that the appropriate capillary can not be found if the distance A between the pad 13 in the chip 12 and the rim of the chip 11 is smaller than 0.2 mm.

SUMMARY OF THE INVENTION

[0006] An object of the present invention is to provide a method of wire bonding for small clearance, which overcomes the disadvantage in the prior arts that the distance A between the center of the pad in the chip 12 and the rim of the chip 11 is too small to perform the wiring process by the conventional wiring equipment. The method of the present invention can prevent the capillary from colliding with the chip during the three-dimensional package wiring process. In the present invention, a conductive bump 15 is first formed over the pad 13 of the chip 12 and then the chip is connected to the lead frame by the conventional wiring method. The height H of the bump 15 is determined by the reverse loop D, the radius C of the capillary 14, the thickness E of the chip 11, and the distance A between the pad 13 in the chip 12 and the rim of the chip 11.

[0007] Other features and advantages of the invention will become apparent from the following description of the invention that refers to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a schematic diagram illustrating the stub structure by a conventional chip wiring method; and

[0009] FIG. 2 is a schematic diagram illustrating the stub structure by a new chip wiring method according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0010] When the distance A is too small, as shown in FIG. 1, it is possible to overcome the issue that the capillary 14 may collide with the chip 11 by increasing the space for the reverse loop D of the capillary 14. With reference to FIG. 2, the stub structure used in the wiring method for small clearance according to the present invention comprises a body, which at least consists of the chips 11 and 12. The present invention is characterized as that the pad 13 is covered by a conductive bump 15, which is made of one conductive material selected from metal, alloy, polymer and the mixture. Apparently, the present invention increases the space for the reverse loop D of the capillary 14 with respect to the prior art shown in FIG. 1. The constraint to limit the clearance (distance A) between the chips is allowed of more wide range so as to overcome the failure of wiring in three dimensional package for small clearance.

[0011] In the steps of the method of the present invention, the pad 13 of the chip 12 is first covered with the conductive bump 15, and then the chip is connected to the lead frame by the conventional wiring process. The height H of the bump 15 is determined by the reverse loop D, the radius C of the capillary 14, the thickness E of the chip 11, and the distance A between the pad 13 in the chip 12 and the rim of the chip 11. The present invention provides the stability of the prior art and meets the requirement of the present and future process.

[0012] The present invention employs the convention technique to overcome the present problem in new process such that the issue that the capillary may collide with the chip is solved in three dimensional package for small clearance.

[0013] The present invention provides the advantages:

[0014] (1) the capillary may not collide with the chip is solved in the three dimensional package for small clearance;

[0015] (2) the clearance between the chip and the pad is allowed smaller than 0.2 mm in the three dimensional package;

[0016] (3) the present equipment is enough to implement the method of the present invention so as to save the cost; and

[0017] (4) only one step is added in the manufacturing process to keep the stability of the prior art.

[0018] Although only the preferred embodiments of this invention were shown and described in the above description, it is requested that any modification or combination that comes within the spirit of this invention be protected.

Claims

1. A method of wire bonding for small clearance, using a body comprising a plurality of chips, wherein said method is characterized as: a conductive bump with an appropriate height is first formed between a pad and a wire during a wiring process for connecting said pad in one side of said body to a lead frame.

2. The method as claimed in

claim 1, wherein said conductive bump is made of metal, alloy, polymer, or a mixture.

3. The method as claimed in

claim 2, wherein said metal is selected from gold, aluminum, or copper.

4. The method as claimed in

claim 1, wherein said bump is formed by evaporation, sputtering, etching, plating, printing, or stud bonding.

5. The method as claimed in

claim 1, wherein said bump has a height determined by a type and a radius of said capillary, a reverse loop, a thickness of said chip, and a distance from a center of said pad to a rim of the chip.

6. A stub structure for wire bonding with small clearance, comprising a body with a plurality of chips, wherein said stub structure is characterized as: a conductive bump with an appropriate height is first formed between a pad and a wire during a wiring process for connecting said pad in one side of said body to a lead frame.

7. The stub structure as claimed in

claim 6, wherein said conductive bump is made of metal, alloy, polymer, or a mixture.

8. The stub structure as claimed in

claim 7, wherein said metal is selected from gold, aluminum, or copper.

9. The stub structure as claimed in

claim 6, wherein said bump is formed by evaporation, sputtering, etching, plating, printing, or stud bonding.

10. The stub structure as claimed in

claim 6, wherein said bump has a height determined by a type and a radius of said capillary, a reverse loop, a thickness of said chip, and a distance from a center of said pad to a rim of the chip.