METHOD OF CONTROLLING COMMON-MODE IN DIFFERENTIAL GM-C CIRCUITS

Abstract

An apparatus and method is disclosed wherein a first gm-C cell has an output, a second gm-C cell has an input coupled to the output of the first gm-C cell, and a feedback loop is coupled between the first and the second gm-C cell to control a CM voltage with respect to a reference.

Description

FIELD OF THE INVENTION

[0001] This patent application describes a method of controlling common-mode (CM) voltage range in differential transconductor-capacitor (gm-C) circuits. It can also be applied equally as well to more generalized VCO, filter and amplifier circuits.

BACKGROUND OF THE INVENTION

[0002] Differential gm-C circuits offer good design trade-offs for speed and power for high frequency circuitry. Filters using transconductors and capacitors are often called “gm-C” filters. A transconductor is a circuit that has a voltage as an input and a current as an output. Most of the integrated gm-C filters use transconductance tuning vis a PLL, or transconductance fixing with an external precision resistor. However, differential gm-C circuits typically suffer from limited linear range, and the requirement for a common-mode control circuit. This need arises in both state-space and bi-quad structures, because of their dependence on integrator building blocks. The goal for a good integrator design is to maximize output impedance for high DC gain, and to minimize degradation of complex pole ‘Q’ factors. The high impedance outputs are loaded with differential or grounded capacitive loads. Differential filter structures, such as state-space or ladder structures, include differential feedback to control the differential signal excursions, however there is no implicit control of the common-mode (CM) voltage of amplifier outputs.

[0003] This is usually accomplished by sensing the CM level through a pair of differential amplifiers between the output and a CM reference, but large swing non-linearity can cause differential to common-mode conversion and added distortion. Lower distortion circuits can be created using resistors to sense the CM level, but these have the disadvantage of increasing output conductance, reducing ‘Q’ factors for bi-quad structures.

[0004] CM control circuits also must have settling time constants widely separated from the actual filter poles, either much higher or much lower. This is to prevent the differential signal flow and the common-mode signal paths from interacting.

[0005] Typical gm-C type integrators and some CM control methods can be found in Y. Tsividis & J. O. Voorman (editors), Integrated Continuous-Time Filters: Principles, Design, and Applications, IEEE Press, Copyright 1993.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which

[0007] FIG. 1 illustrates the schematic diagram of the CM control circuit with simple gm-C circuits and a feedback loop with an amplifier.

[0008] FIG. 2 illustrates the schematic diagram of the CM control circuit with simple gm-C circuits and a feedback loop without an amplifier.

[0009] FIG. 3 illustrates the fan-in connection.

[0010] FIG. 4 illustrates the fan-out connection.

[0011] FIG. 5 illustrates the process of the present invention.

[0012] FIG. 6 illustrates an example of the present invention as used in a common gm-C based second order low-pass filter topology.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0013] A filter structure apparatus and method wherein the CM voltage of the output of a first gm-C cell is controlled through a feedback loop from a subsequent gm-C cell is disclosed. An optional CM sensing amplifier may be included in this feedback loop between the first and the subsequent gm-C cell for sourcing a CM reference. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that these specific details need not be used to practice the present invention. In other circumstances, wellknown structures, materials, circuits, processes and interfaces have not been shown or described in detail in order not to unnecessarily obscure the present invention.

[0014] Referring to FIG. 1, the filter structure and CM control circuit 100 of the present invention can be applied to simple differential gm stages such as differential amplifiers, or any other structure of differential gm-cells with an identifiable differential ground referenced by the input CM voltage. In FIG. 1, two unit gm cells 110 and 120 are shown coupled in a typical configuration. In this typical structure, each gm cell is comprised of two differential pairs of transistors, a PMOS pair and an NMOS pair. In cell 110, the NMOS differential pair is identified as M1 and M2. It will be apparent to those of ordinary skill in the art that modifications of the basic gm cell structure are possible while still benefiting from the advantages of the present invention as will be described in more detail below. An input to the filter structure shown in FIG. 1 is identified as (in) to transistor M1 and (inb—also denoted in-bar or in-not) to transistor M2. As a result of the conventional properties and operation of the unit gm cell 110 upon receiving input (in) and (inb), outputs (out) and (outb—also denoted out-bar or out-not) are produced. These outputs are fed as inputs to the NMOS differential transistor pair of the next unit gm cell in the series, unit gm cell 120, in the example shown in FIG. 1. Clearly, this structure can be replicated for any number of unit gm cells in a desired series. As also shown in FIG. 1, the outputs (out) and (outb) of unit gm cell 110 are separately tied to a current source line through capacitors C1. The current through the current source line to which these capacitors C1 are tied is identified as I1.

[0015] Because the common mode (CM) output impedance of the NMOS differential pair (M1 and M2) is high, it is difficult to establish a good common mode reference on the output of a unit gm cell. For this reason, the present invention employs a feedback loop as shown in FIGS. 1 and 2. FIG. 1 illustrates an embodiment including an amplifier A(s) in the feedback loop. FIG. 2 illustrates an alternative embodiment without an amplifier in the feedback loop.

[0016] Referring to FIG. 1, the feedback loop of the present invention is coupled between the output of a first unit gm cell and the input of a second or subsequent unit gm cell in a series. This point in the circuit is shown as (out and outb) in FIGS. 1 and 2. As shown, (outb) is coupled to the current source line through transistor M3 and (out) is coupled to the current source line through transistor M4. Transistors M3 and M4 are controlled with an output of the second unit gm cell 120 through an amplifier A(s) as shown in FIG. 1. A common mode reference CM ref. is also provided as an input to the amplifier A(s). FIG. 2 illustrates this coupling of M3 and M4 to the output of unit gm cell 120 without the amplifier A(s). Note that transistors M3 and M4 can be very small (i.e. weak) transistors. In the preferred embodiment, only a small fraction, I3 and I4, of the total current in the current source line is traveling through nodes M3 and M4, respectively. As shown in FIGS. 1 and 2, the current through line (out) is given by the equation: ((I1/2)+I4) and the current through line (outb) is given by the equation: ((I1/2)+I3). Thus, the feedback loop will settle if the nodes M3 and M4 sink the excess current level that the PMOS devices are sourcing.

[0017] In the system illustrated in FIGS. 1 and 2, an integrator is formed with the differential pair 110 and load capacitors C1 on the left side of FIGS. 1 and 2 with a differential mode (DM) transfer function as set forth below. 1 V o ⁢   ⁢ u ⁢   ⁢ t V i ⁢   ⁢ n = V ⁡ ( o ⁢   ⁢ u ⁢   ⁢ t ) - V ⁡ ( o ⁢   ⁢ u ⁢   ⁢ t ⁢   ⁢ b ) V ⁡ ( i ⁢   ⁢ n ) - V ⁡ ( i ⁢   ⁢ n ⁢   ⁢ b ) = ( g m ⁡ ( 1 , 2 ) / g 0 ) 1 + s ⁡ ( C 1 / g 0 ) ≈ g m ⁡ ( 1 , 2 ) s ⁢   ⁢ C 1 = 1 ( s / ω D ⁢   ⁢ M )

[0018] Where the differential unity gain bandwidth is given by: 2 ω D ⁢   ⁢ M = g m ⁡ ( 1 , 2 ) C 1

[0019] The CM voltage of the output is controlled through the feedback loop on the right side of FIGS. 1 and 2. The CM sensing amplifier A(s) in this loop as shown in FIG. 1 is in the subsequent unit gm cell in the filter structure. This CM control loop has an open loop gain of: 3 H ⁡ ( s ) = A ⁡ ( s ) · g m ⁡ ( 3 , 4 ) s · C 1

[0020] In unity feedback, this yields a CM loop response of: 4 A ⁡ ( s ) = H ⁡ ( s ) 1 + H ⁡ ( s ) = 1 s ⁡ ( C 1 A ⁡ ( s ) · g m ⁡ ( 3 , 4 ) ) + 1 = 1 s ω C ⁢   ⁢ M + 1

[0021] Where the loop bandwidth is given by: 5 ω C ⁢   ⁢ M = A ⁡ ( s ) · g m3 C 1

[0022] Because both CM and differential loops are controlled by the same capacitor value, stability and time-constant separation is guaranteed if sufficiently different gm's are selected. Simplifications here include ignoring the bandwidth effects from the parasitic pole due to the source followers in the CM loop (from the second/subsequent unit gm cell differential pair devices). This is a reasonable simplification, and one benefit of this invention.

[0023] In this invention, the CM control loop bandwidth is generally smaller than the main gm-C filter bandwidth, although this is not the only possibility within the scope of this invention. The CM and differential mode (DM) loops can also be stable if the CM control loop has significantly larger bandwidth (i.e. wCM>wDM).

[0024] In practice, the amplifier with gain ‘A’ can be substituted with a direct connection, as shown in FIG. 2, thereby reducing the CM control bandwidth expression to: 6 ω C ⁢   ⁢ M = g ⁢   ⁢ m3 C 1

[0025] In this mode, the CM control voltage is given by the properties of the CM control NMOS devices (M3 and M4) as shown in FIGS. 1 and 2. The CM output voltage will be given by: 7 V C ⁢   ⁢ M = V T3 + 2 ⁢ I D3 k n ′ · L 3 W 3

[0026] A special case can occur when low-VT MOS devices are available, in which the output CM level is dominated by the (VGS-VT) bias point of M3 and M4. Assuming the bias currents are derived from the same sources, this can be designed to track the VD(SAT) of the bias current transistors 115 within the gm cells, providing an optimized CM level where the tail current sources are always operating just above the minimum VDS for saturated operation. This maximizes the available supply voltage for the active signals in the gm cells. This becomes increasingly important in low-voltage applications where these circuits must operate with less than 3V power supplies.

[0027] In our implementation, this causes no loop stability problems; because, the common source sensing node of the differential gm cells is an AC ground; thus, it does not affect the differential operation of the circuit. It is also typically a low-impedance node with very high CM bandwidth. This has the benefit of limiting the effect of parasitic poles in the CM control loop. The structure and operation of the present invention provides advantages including the effect that minimal additional current is required. The additional CM control currents (I3, I4) can be <10% of the gm cell current. Further, the invention adds no resistive load to gm cells in gm-C filter structures. Also, the invention adds no further distortion to cause CM-differential feed-through.

[0028] The present invention provides a simple method of controlling the common mode (CM) output level voltage of a differential gm-C circuit that is inherently stable, and causes minimal interaction with the differential loop. The invention provides a method of using an internal differential AC ground node to sense the CM voltage of the output of a previous stage. The invented apparatus provides a method of sensing the CM voltage of the output of a gm cell, which adds no additional distortion to the original gm cell, and without adding significant extra circuitry or using significant additional power. The invented apparatus also provides a method for applying the CM sensing information to the output of a gm amplifier to control it's CM voltage in a manner that is inherently stable. The invented apparatus also provides a method of controlling the CM voltage in a differential filter structure in such a way as to maximize the signal headroom of a differential gm cell. The invented apparatus also provides a method of controlling the CM voltage, which results in an optimal bias point for current sources of differential gm cells. The invented apparatus also provides a method of controlling CM voltage in differential gm-C filter structures which can be generically extended to include any other integrator structure with an identifiable node which is both a CM ground, and a representation of CM voltage.

[0029] In a manner described in more detail below, the filter structure of the present invention also provides a CM control method that can be easily extended to fan-in and fan-out topologies of gm-C filters. The above description illustrates the simple case of a single gm cell driving another gm cell. In most filter structures, there are also fan-in and fan-out cases in which multiple gm cells can drive single gm inputs, or single gm cells can drive multiple gm cells respectively. In both of these cases, general connection rules can be applied which allow the circuit of the present invention to be advantageously used.

[0030] In the fan-in connection case illustrated in FIG. 3, multiple driving cells (gm1 & gm2) are connected to a single load cell (gm3). This connection is shown in FIG. 3. In general, the feedback signal 310 is extracted from the driven gm cells (gm3), and fed back to both of the driving gm cells (gm1 and gm2).

[0031] A special implementation can be made for a cell structure in which the CM control circuit elements, including the pull-down MOS M3 & M4 and the CM bias current source ICM, are in a separate circuit block and can be added only as needed. This will potentially reduce the matching of gm cell output capacitance.

[0032] In the fan-out connection illustrated in FIG. 4, the feedback signal 410 can, in practice, only be taken from either one of the driven gm cells (gm2 or gm3) to prevent coupling of non-linear distortion between signal paths. The feedback is applied to the driving gm cell (gm1) in the same fashion as shown in FIGS. 1 and 2.

[0033] FIG. 5 illustrates the process of the present invention. Referring to FIG. 5, an output is produced by a first gm-C cell in block 510. This output is provided as an input to a second gm-C cell in block 520. Finally, a feedback loop is created by coupling the output of the first gm-C cell through a transistor controlled by an output of the second gm-C cell in block 530. Optionally, the transistor in the feedback loop can be controlled through an amplifier receiving a CM reference.

[0034] FIG. 6 illustrates an example of the present invention as used in a common gm-C based second order low-pass filter topology. In a manner similar to that shown in FIGS. 1 and 2, FIG. 6 shows a series of unit Gm cells, such as unit Gm cell I1, arranged in a filter topology. Transistors also shown in FIG. 6 are coupled to the outputs (out and outb) of Gm cell I1 in a configuration corresponding to load capacitors C1 shown in FIGS. 1 and 2. In an alternative embodiment, these transistors could be replaced by capacitors coupled in an equivalent configuration. The pull-down transistors M3 and M4 (not shown in FIG. 6) of the feedback loop of the present invention are coupled with their input tied to the unit Gm cell I1 pin labeled “cmfb”. The unit Gm cell I2 pin labeled “cmop” in FIG. 6 is the tap from the common-source node to feed back the CM voltage. This sample low-pass filter topology achieves all of the advantages of the present invention as described above.

[0035] Thus, a novel filter structure apparatus and method is disclosed. Although the present invention is described herein with reference to a specific preferred embodiment, many modifications and variations therein will readily occur to those with ordinary skill in the art. Accordingly, all such variations and modifications are included within the intended scope of the present invention as defined by the following claims.

APPENDIX A

[0036] William E. Alford, Reg. No. 37,764; Farzad E. Amini, Reg. No. 42,261; William Thomas Babbitt, Reg. No. 39,591; Carol F. Barry, Reg. No. 41,600; Jordan Michael Becker, Reg. No. 39,602; Lisa N. Benado, Reg. No. 39,995; Bradley J. Bereznak, Reg. No. 33,474; Michael A. Bernadicou, Reg. No. 35,934; Roger W. Blakely, Jr., Reg. No. 25,831; R. Alan Burnett, Reg. No. 46,149; Gregory D. Caldwell, Reg. No. 39,926; Andrew C. Chen, Reg. No. 43,544; Thomas M. Coester, Reg. No. 39,637; Donna Jo Coningsby, Reg. No. 41,684; Florin Corie, Reg. No. 46,244; Dennis M. deGuzman, Reg. No. 41,702; Stephen M. De Klerk, Reg. No. 46,503; Michael Anthony DeSanctis, Reg. No. 39,957; Daniel M. De Vos, Reg. No. 37,813; Sanjeet Dutta, Reg. No. 46,145; Matthew C. Fagan, Reg. No. 37,542; Tarek N. Fahmi, Reg. No. 41,402; George Fountain, Reg. No. 37,374; James Y. Go, Reg. No. 40,621; James A. Henry, Reg. No. 41,064; Libby N. Ho, Reg. No. 46,774; Willmore F. Holbrow III, Reg. No. 41,845; Sheryl Sue Holloway, Reg. No. 37,850; George W Hoover II, Reg. No. 32,992; Eric S. Hyman, Reg. No. 30,139; William W. Kidd, Reg. No. 31,772; Sang Hui Kim, Reg. No. 40,450; Walter T. Kim, Reg. No. 42,731; Eric T. King, Reg. No. 44,188; George Brian Leavell, Reg. No. 45,436; Kurt P. Leyendecker, Reg. No. 42,799; Gordon R. Lindeen III, Reg. No. 33,192; Jan Carol Little, Reg. No. 41,181; Robert G. Litts, Reg. No. 46,876; Joseph Lutz, Reg. No. 43,765; Michael J. Mallie, Reg. No. 36,591; Andre L. Marais, under 37 C.F.R. § 10.9(b); Paul A. Mendonsa, Reg. No. 42,879; Clive D. Menezes, Reg. No. 45,493; Chun M. Ng, Reg. No. 36,878; Thien T. Nguyen, Reg. No. 43,835; Thinh V. Nguyen, Reg. No. 42,034; Dennis A. Nicholls, Reg. No. 42,036; Robert B. O'Rourke, Reg. No. 46,972; Daniel E. Ovanezian, Reg. No. 41,236; Kenneth B. Paley, Reg. No. 38,989; Gregg A. Peacock, Reg. No. 45,001; Marina Portnova, Reg. No. 45,750; William F. Ryann, Reg. 44,313; James H. Salter, Reg. No. 35,668; William W. Schaal, Reg. No. 39,018; James C. Scheller, Reg. No. 31,195; Jeffrey Sam Smith, Reg. No. 39,377; Maria McCormack Sobrino, Reg. No. 31,639; Stanley W. Sokoloff, Reg. No. 25,128; Judith A. Szepesi, Reg. No. 39,393; Vincent P. Tassinari, Reg. No. 42,179; Edwin H. Taylor, Reg. No. 25,129; John F. Travis, Reg. No. 43,203; Joseph A. Twarowski, Reg. No. 42,191; Tom Van Zandt, Reg. No. 43,219; Lester J. Vincent, Reg. No. 31,460; Glenn E. Von Tersch, Reg. No. 41,364; John Patrick Ward, Reg. No. 40,216; Mark L. Watson, Reg. No. 46,322; Thomas C. Webster, Reg. No. 46,154; and Norman Zafman, Reg. No. 26,250; my patent attorneys, and Firasat Ali, Reg. No. 45,715; Justin M. Dillon, Reg. No. 42,486; Thomas S. Ferrill, Reg. No. 42,532; and Raul Martinez, Reg. No. 46,904, my patent agents, of BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, with offices located at 12400 Wilshire Boulevard, 7th Floor, Los Angeles, Calif. 90025, telephone (310) 207-3800, and Alan K. Aldous, Reg. No. 31,905; Edward R. Brake, Reg. No. 37,784; Ben Burge, Reg. No. 42,372; Jeffrey S. Draeger, Reg. No. 41,000; Cynthia Thomas Faatz, Reg No. 39,973; John N. Greaves, Reg. No. 40,362; Seth Z. Kalson, Reg. No. 40,670; David J. Kaplan, Reg. No. 41,105; Peter Lam, Reg. No. 44,855; Charles A. Mirho, Reg. No. 41,199; Leo V. Novakoski, Reg. No. 37,198; Thomas C. Reynolds, Reg. No. 32,488; Kenneth M. Seddon, Reg. No. 43,105; Mark Seeley, Reg. No. 32,299; Steven P. Skabrat, Reg. No. 36,279; Howard A. Skaist, Reg. No. 36,008; Gene I. Su, Reg. No. 45,140; Calvin E. Wells, Reg. No. P43,256, Raymond J. Werner, Reg. No. 34,752; Robert G. Winkle, Reg. No. 37,474; Steven D. Yates, Reg. No. 42,242; and Charles K. Young, Reg. No. 39,435; my patent attorneys, of INTEL CORPORATION; and James R. Thein, Reg. No. 31,710, my patent attorney with full power of substitution and revocation, to prosecute this application and to transact all business in the Patent and Trademark Office connected herewith.

APPENDIX B

Title 37, Code of Federal Regulations, Section 1.56

Duty to Disclose Information Material to Patentability

[0037] (a) A patent by its very nature is affected with a public interest. The public interest is best served, and the most effective patent examination occurs when, at the time an application is being examined, the Office is aware of and evaluates the teachings of all information material to patentability. Each individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability as defined in this section. The duty to disclosure information exists with respect to each pending claim until the claim is cancelled or withdrawn from consideration, or the application becomes abandoned. Information material to the patentability of a claim that is cancelled or withdrawn from consideration need not be submitted if the information is not material to the patentability of any claim remaining under consideration in the application. There is no duty to submit information which is not material to the patentability of any existing claim. The duty to disclosure all information known to be material to patentability is deemed to be satisfied if all information known to be material to patentability of any claim issued in a patent was cited by the Office or submitted to the Office in the manner prescribed by §§1 .97(b)-(d) and 1.98. However, no patent will be granted on an application in connection with which fraud on the Office was practiced or attempted or the duty of disclosure was violated through bad faith or intentional misconduct. The Office encourages applicants to carefully examine:

[0038] (1) Prior art cited in search reports of a foreign patent office in a counterpart application, and

[0039] (2) The closest information over which individuals associated with the filing or prosecution of a patent application believe any pending claim patentably defines, to make sure that any material information contained therein is disclosed to the Office.

[0040] (b) Under this section, information is material to patentability when it is not cumulative to information already of record or being made or record in the application, and

[0041] (1) It establishes, by itself or in combination with other information, a prima facie case of unpatentability of a claim; or

[0042] (2) It refutes, or is inconsistent with, a position the applicant takes in:

[0043] (i) Opposing an argument of unpatentability relied on by the Office, or

[0044] (ii) Asserting an argument of patentability.

[0045] A prima facie case of unpatentability is established when the information compels a conclusion that a claim is unpatentable under the preponderance of evidence, burden-of-proof standard, giving each term in the claim its broadest reasonable construction consistent with the specification, and before any consideration is given to evidence which may be submitted in an attempt to establish a contrary conclusion of patentability.

[0046] (c) Individuals associated with the filing or prosecution of a patent application within the meaning of this section are:

[0047] (1) Each inventor named in the application;

[0048] (2) Each attorney or agent who prepares or prosecutes the application; and

[0049] (3) Every other person who is substantively involved in the preparation or prosecution of the application and who is associated with the inventor, with the assignee or with anyone to whom there is an obligation to assign the application.

[0050] (d) Individuals other than the attorney, agent or inventor may comply with this section by disclosing information to the attorney, agent, or inventor.

Claims

1. A filter structure apparatus comprising:

a first gm-C cell having an output;

a second gm-C cell having an input coupled to said output of said first gm-C cell; and

a feedback loop coupled between the first and the second gm-C cell to control a CM voltage with respect to a reference.

2. The apparatus as claimed in claim 1 wherein the feedback loop further includes an amplifier to source a CM reference.

3. The apparatus as claimed in claim 1 wherein the feedback loop further includes transistor elements.

4. The apparatus as claimed in claim 1 wherein the feedback loop further includes capacitor elements.

5. The apparatus as claimed in claim 1 wherein the feedback loop includes a transistor controlled by an output of the second gm-C cell.

6. The apparatus as claimed in claim 5 wherein the strength of the transistor controlled by an output of the second gm-C cell is substantially weaker than any transistor in the first gm-C cell.

7. An apparatus comprising:

a means for providing a first gm-C cell output;

a means for providing a second gm-C cell input coupled to said output of said first gm-C cell; and

a means for providing a feedback loop coupled between the first and the second gm-C cell for controlling a CM reference.

8. The apparatus as claimed in claim 7 wherein the feedback loop further includes an amplifier means for sourcing a CM reference.

9. The apparatus as claimed in claim 7 wherein the feedback loop further includes a transistor means.

10. The apparatus as claimed in claim 7 wherein the feedback loop further includes a capacitor means.

11. The apparatus as claimed in claim 7 wherein the feedback loop includes a transistor me ans controlled by an output of the second gm-C cell.

12. The apparatus as claimed in claim 11 wherein the strength of the transistor means controlled by an output of the second gm-C cell is substantially weaker than any transistor means in the first gm-C cell.

13. A process comprising:

producing an output from a first gm-C cell;

providing the output as an input to a second gm-C cell; and

coupling the output through a transistor in a feedback loop to control a CM voltage with respect to a reference.

14. The process as claimed in claim 13 further including coupling the output through an amplifier with a CM reference input.

15. The process as claimed in claim 13 wherein the strength of the transistor in the feedback loop is substantially weaker than any other transistor in the first gm-C cell.