Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof

Abstract

A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film of a thickness of 0.5 nm to 5 nm is continuously formed on the thin SiGe film at the same temperature.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor device and to a method for manufacturing thereof. More specifically the present invention relates to a gate electrode including a thin SiGe film and to a method for manufacturing thereof.

DESCRIPTION OF THE BACKGROUND ART

[0002] In recent years, MOSFET (metal oxide semiconductor field effect transistor) as a semiconductor device has been extremely miniaturized and highly integrated. Concurrent to this trend, the thickness of a gate dielectric film has been reduced from the point of view of securing the driving current and saving power consumption. However, the value of parasitic capacitance resulted from the depletion generated in a gate electrode composed of polysilicon due to the reduction of the thickness of gate dielectric films has not been able to ignored, thereby arising problems in the highly integration and power saving of MOSFETs.

[0003] In order to cope with such problems, the use of silicon germanium (hereafter abbreviated to “SiGe”) for agate electrode has been proposed. The use of a SiGe film in the gate electrode of an MOSFET can improve the activation rate of conductive impurities (e.g., boron) in the gate electrode, inhibit the depletion of the gate electrode, thus reducing the parastic capacitance. This allows the use of a gate dielectric film with an increased thickness and the reduction of gate leakage current.

[0004] Although the width of the gate electrode (hereafter referred to as “gate length”) must be reduced with the above-described miniaturization of the MOSFET, the thickness of the gate electrode must also be reduced from the point of view of the stability and the processing accuracy of gate wiring patterns. For example, according to the ITRS Roadmap of 2001 Edition, the thickness of a gate electrode must be reduced to 35 nm to 70 nm in a semiconductor device of the 35-nm-gate-length generation.

[0005] In order to lower the resistance of a gate electrode, a silicide film may be formed above the SiGe film. In this case, there is a problem of the occurrence of silicide cohesion and defective resistance caused by Ge in the SiGe film during the formation of the cobalt silicide film. In order to solve this problem, there has been proposed to form a thick cap Si film on the SiGe film, and to adjust the Ge concentration in the surface of the cap Si film to 2% of less (e.g., refer to Japanese Patent Laid-Open No. 2002-261274 (Page 5, FIG. 1)).

[0006] In next-generation semiconductor devices, as described above, the thickness reduction of the SiGe film as the gate electrode is demanded. Furthermore, when a cap Si film is formed on the SiGe film to form a silicide film, since the thickness of the SiGe film must be the value of the entire thickness of the gate electrode minus the thickness of the silicon film, the SiGe film must further be thinned.

[0007] However, the own examinations by the present inventor revealed the occurrence of problems described below when the SiGe film is thinned.

[0008] FIGS. 13A to 13C are SEM photographs showing the cross section of the thinned SiGe film grown on a gate dielectric film composed of a SiO2 film. Specifically, FIG. 13A shows the case where the SiGe film of a thickness of 150 nm is formed, FIG. 13B shows the case where the SiGe film of a thickness of 50 nm is formed, and FIG. 13C shows the case where the SiGe film of a thickness of 20 nm is formed.

[0009] As FIG. 13A shows, when the SiGe film is relatively thick (150 nm), the continuous film free of voids is attained. However, as FIG. 13B shows, when the growth time is shortened to make the thickness of the SiGe film 50 nm, voids (refer to circled portions in FIG. 13B) generate in the SiGe film. When the growth time is further shortened to make the thickness of the SiGe film 20 nm, the film becomes discontinuous due to surface roughness as FIG. 13C shows.

[0010] When the SiGe film is thinned, as described above, there are problems that voids generate in the SiGe film during growing the grains of the SiGe film, or the SiGe film becomes discontinuous due to surface roughness of the SiGe film, that is, a defective SiGe film is produced. There are also problems that the conformation of the SiGe film varies due to heat treatment performed after the formation of the SiGe film, thus forming of a defective SiGe film.

[0011] If the above-described defective film is formed due to the thinning of the SiGe film, it is difficult to form the SiGe film having a uniform Ge content in the boundary between the gate dielectric film and the gate electrode. In addition, when a gate electrode is formed using dry etching, locally defective processing caused by the non-uniformity of the thickness of the SiGe film. Since the voids generated in the SiGe film causes variation in the wiring resistance of the gate wirings and the driving ability of the transistor, the yield of transistor manufacturing is affected.

SUMMARY OF THE INVENTION

[0012] The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide novel and useful method for manufacturing a semiconductor device.

[0013] A more specific object of the present invention is to form a high-quality thin SiGe film free of voids on a gate dielectric film.

[0014] The above object of the present invention is attained by a following semiconductor device and a following method for manufacturing a semiconductor device.

[0015] According to first aspect of the present invention, the semiconductor device comprises a gate dielectric film formed on a substrate and a gate electrode formed on the gate dielectric film. The gate electrode includes a seed Si film formed on the gate dielectric film; a thin SiGe film formed on the seed Si film and having a thickness of 50 nm or less; and a thin cap Si film formed on the thin SiGe film and having a thickness of 0.5 nm to 5 nm.

[0016] According to second aspect of the present invention, in the method, a gate dielectric film is first formed on a substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film is continuously formed with a thickness of 0.5 nm to 5 nm on the thin SiGe film at the same temperature. The thin cap Si film, the thin SiGe film, and the seed Si film is patterned to form a gate electrode. Source-drain regions are formed in an upper layer of the substrate through ion implantation using the gate electrode as a mask.

[0017] According to third aspect of the present invention, in the method, a gate dielectric film is first formed on a substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film is continuously formed with a thickness of 0.5 nm to 5 nm on the thin SiGe film at the same temperature. An upper Si film is formed on the thin cap Si film at a temperature higher than a temperature of forming the thin SiGe film. The upper Si film, the thin cap Si film, the thin SiGe film, and the seed Si film are patterned to form a gate electrode. Source-drain regions are formed in an upper layer of the substrate through ion implantation using the gate electrode as a mask.

[0018] Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a schematic cross-sectional view for illustrating a semiconductor device according to a first embodiment of the present invention;

[0020] FIGS. 2A to 2D are process sectional views for illustrating a method for manufacturing the semiconductor device shown in FIG. 1:

[0021] FIGS. 3A and 3B are graphs showing the relationship between the Ge content in a thin SiGe film and the depletion rate in an MOS capacitor;

[0022] FIG. 4 is a graph showing the relationship between the growth temperature of a thin SiGe film, and the growth rate and the uniformity of the film thickness on the surface of the thin SiGe film;

[0023] FIGS. 5A to 5C are SEM photographs showing the cross sections of a thin SiGe film when the growth pressure of the thin SiGe film was varied

[0024] FIGS. 6A and 6B are SEM photographs showing the cross sections of a thin SiGe film as formed and after forming a thin cap Si film thereon;

[0025] FIG. 7 is a schematic cross-sectional view for illustrating a semiconductor device according to a second embodiment of the present invention;

[0026] FIG. 8 is a process sectional view for illustrating a method for manufacturing the semiconductor device according to a second embodiment of the present invention;

[0027] FIGS. 9A and 9B are SEM photographs showing the cross sections of the thin SiGe film after heat treatment corresponding to the growth of the upper Si film in the case when a thin cap Si film is formed and not formed on the thin SiGe film;

[0028] FIGS. 10A and 10B are SEM photographs showing the cross sections of a thin SiGe film when the growth temperature of the upper Si film is changed in the formation of the upper Si film on the thin SiGe film through the thin cap Si film;

[0029] FIG. 11 is a schematic cross-sectional view for illustrating a semiconductor device according to a third embodiment of the present invention;

[0030] FIGS. 12A and 12B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a third embodiment of the present invention;

[0031] FIG. 13 is a schematic cross-sectional view for illustrating a semiconductor device according to a fourth embodiment of the present invention;

[0032] FIGS. 14A and 14B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a fourth embodiment of the present invention;

[0033] FIG. 15 is a schematic cross-sectional view for illustrating a semiconductor device according to a fifth embodiment of the present invention;

[0034] FIGS. 16A and 16B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a fifth embodiment of the present invention;

[0035] FIG. 17 is a schematic cross-sectional view for illustrating a semiconductor device according to a sixth embodiment of the present invention;

[0036] FIG. 18 is a schematic cross-sectional view for illustrating a semiconductor device according to a seventh embodiment of the present invention;

[0037] FIGS. 19A to 19C are SEM photographs showing the cross section of the thinned SiGe film grown on a gate dielectric film composed of a SiO2 film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] In the following, principles and embodiments of the present invention will be described with reference to the accompanying drawings. The members and steps that are common to some of the drawings are given the same reference numerals and redundant descriptions therefore may be omitted.

[0039] First Embodiment

[0040] First, the structure of a semiconductor device according to a first embodiment of the present invention will be described.

[0041] FIG. 1 is a schematic cross-sectional view for illustrating a semiconductor device according to a first embodiment of the present invention.

[0042] As FIG. 1 shows, a silicon substrate serving as the substrate 2 has element regions on which semiconductor elements such as transistors are formed, and isolation regions for isolating the element regions, in which field insulating films (also referred to as “element-isolating insulating films”) 4 are formed. Well regions (not shown) are formed in the element regions of the substrate 2.

[0043] On the substrate 2 in the element regions, a gate dielectric film 6 is formed. As the gate dielectric film 6, for example, a SiO2 film, a Si3N4 film, or a SiON film (hereafter collectively referred to as “SiO2 film or the like”) can be used. The thickness of the gate dielectric film 6 composed of a SiO2 film or the like is, for example, 1.0 nm to 1.5 nm. In place of the SiO2 film or the like, a high-dielectric-constant film (high-k dielectric film) can be used as the gate dielectric film 6. A laminated film composed of a SiO2 film or the like and a high-dielectric-constant film can also be used as the gate dielectric film 6. In this case, the thickness of the SiO2 film or the like is less than 1.0 nm. Here, as the high-dielectric-constant film, for example, a metal oxide such as Al2O3, HfO2, ZrO2, and La2O3, a metal nitride, a metal oxynitride, a metal silicate such as HfSiOx and ZrSiOx, or a metal aluminate such as HfAlOx and ZrAlOx, can be used.

[0044] On the gate dielectric film 6 is formed a gate electrode composed of the laminate of a seed Si film 8, a thin SiGe film 10, and a thin cap Si film 12. Source-drain regions 14 sandwiching a channel region (not shown) underneath the gate electrode are formed in the upper layer of the silicon substrate 2.

[0045] Next, the gate electrode will be described.

[0046] On the gate dielectric film 6 is formed an amorphous Si film serving as the seed Si film 8. The thickness of the seed Si film 8 is preferably 1 nm to 5 nm.

[0047] On the seed Si film 8 is formed a thin SiGe film 10 as a lower electrode film. The thickness of the thin SiGe film 10 is preferably 50 nm or below. The thin SiGe film 10 is represented by a composition formula of Si(1-x)Gex, and the Ge content X is preferably 0.15 or more and smaller than 0.4 (15% or more and smaller than 40%), and more preferably about 0.3 (30%) (described later). The thin SiGe film 10 is preferably grown at a growth temperature of 450° C. or above and below 494° C. (described later). The thin SiGe film 10 is also preferably a polycrystalline thin SiGe film grown under a growth pressure of 30 Pa or amorphous SiGe grown under a growth pressure 150 Pa or above (described later).

[0048] On the thin SiGe film 10 is formed a thin cap Si film 12. The thickness of the thin cap Si film 12 is preferably 0.5 nm to 5 nm (described later). It is preferable that the thin SiGe film 10 and the thin cap Si film 12 are continuously formed using the same apparatus at the same temperature.

[0049] Next, a method for manufacturing the above-described semiconductor device will be described.

[0050] FIGS. 2A to 2D are process sectional views for illustrating a method for manufacturing the semiconductor device shown in FIG. 1.

[0051] First, as FIG. 2A shows, field insulating films 4 are formed in the isolation regions of a silicon substrate 2 using STI (shallow trench isolation) method. Then, the ions of a conductive impurity are implanted into the element regions (not shown) of the silicon substrate 2, and annealing is performed to form well regions.

[0052] Next, after a predetermined pretreatment (e.g., the removal of natural oxide films) has been performed, a SiO2 film or the like (described above) with a thickness of, for example, 1.0 nm to 1.5 nm is formed as a gate dielectric film 6 on the silicon substrate 2 using a method such as thermal oxidation (or thermal nitriding or thermal oxynitriding) or plasma oxidation (or plasma nitriding or plasma oxynitriding).

[0053] As described above, a high-k dielectric film can be formed as the gate dielectric film 6 in place of the SiO2 film or the like, or together with the SiO2 film or the like. When a laminated structure composed of a SiO2 film or the like and a high-k dielectric film is used, the thickness of the SiO2 film or the like is less than 1.0 nm. The high-k dielectric film can be grown using an ALD (atomic layer deposition) method or an MOCVD (metal organic chemical vapor deposition) method.

[0054] Next, as FIG. 2A shows, an amorphous Si film as a seed Si film 8 with a thickness of, for example, 1 nm to 5 nm is formed on the gate dielectric film 6 using a CVD (chemical vapor deposition) method. For the formation of the seed Si film 8, for example, a batch-type vertical LPCVD apparatus can be used. The conditions for forming the seed Si film 8 in the LPCVD apparatus are, for example, an SiH4 flow rate of 1 slm, a growth temperature of 475° C., and a growth time of 5 to 20 minutes.

[0055] Then, as FIG. 2B shows, a thin SiGe film 10 is formed on the seed Si film 8 using the above-described LPCVD apparatus. Specifically, the seed Si film 8 and the thin SiGe film 10 are continuously formed.

[0056] Here, the Ge content X in the thin SiGe film 10 represented by the composition formula, Si(1-x)Gex, is preferably 0.15 or more and smaller than 0.4 (15% or more and smaller than 40%), and most preferably 0.3 (30%). The own examinations by the present inventor on the Ge content will be described below. The present inventor examined the relationship between the Ge content in a thin SiGe film formed on a gate dielectric film through a seed Si film and the depletion rate in an MOS capacitor.

[0057] FIGS. 3A and 3B are graphs showing the relationship between the Ge content in a thin SiGe film and the depletion rate in an MOS capacitor. In other words, FIGS. 3A and 3B are graphs showing the Ge-content dependency of the depletion rate in an MOS capacitor. Specifically, FIG. 3A is a graph showing the Ge-content dependency of the depletion rate in a PMOS capacitor; and FIG. 3B is a graph showing the Ge-content dependency of the depletion rate in an NMOS capacitor. Here, the depletion rate means the percentage of the inverted capacitance to the accumulated capacitance in an MOS capacitor.

[0058] As FIG. 3A shows, the depletion rate on a PMOS capacitor is improved with increase in the Ge content, and although the improving effect is not satisfactory when the Ge content is less than 0.15 (15%), the improving effect is saturated when the Ge content is 0.3 (30%) or more. This shows that increase in the Ge content to 0.15 (15%) or more improves the depletion rate of the PMOS capacitor, and improve the driving ability of the PMOS transistor. On the other hand, as FIG. 3B shows, although the depletion rate of an NMOS capacitor little changes when the Ge content is 0.3 (30%) or less, the depletion rate is lowered when the Ge content is 0.4 (40%), and the driving ability of the NMOS transistor is lowered.

[0059] Therefore, in order to make the improvement of gate depletion and driving ability of a PMOS transistor compatible to the avoidance of lowered driving ability of an NMOS transistor, the Ge content in the thin SiGe film 10 is preferably 0.15 or more and smaller than 0.4 (15% or more and smaller than 40%), and most preferably 0.3 (30%) as described above.

[0060] The growth temperature of the thin SiGe film 10 is preferably 450° C. or above and 494° C. or below, and most preferably 475° C. The own examinations by the present inventor on the growth temperature will be described below. The present inventor examined the relationship between the growth temperature of a thin SiGe film formed on a gate dielectric film composed of a SiO2 film through a seed Si film, and the growth rate and the uniformity of the film thickness on the surface of the thin SiGe film.

[0061] FIG. 4 is a graph showing the relationship between the growth temperature of a thin SiGe film, and the growth rate and the uniformity of the film thickness on the surface of the thin SiGe film. Here, the uniformity of the film thickness on the surface means the variation &sgr; (%) of the thickness of the thin SiGe film measured at 49 points on the surface. The thin SiGe film having a Ge content of 0.3 (30%) was grown under a flow-rate ratio of H2-diluted 10% GeH4 to SiH4 of 0.96.

[0062] As FIG. 4 shows, although the growth rate increases with the elevation of the growth temperature, the uniformity of the film thickness on the surface of the thin SiGe film (film thickness variation &sgr;) worsens. When the growth temperature is 525° C. or above, the value of film thickness variation &sgr; increases to larger than 2%, and the uniformity of the film thickness on the surface worsens. If the growth temperature is even higher, the value of the surface roughness of the thin SiGe film increases, and the consequent etching process of the gate electrode will become difficult. In order to make the value of film thickness variation &sgr; 1%, that is, in order to achieve a favorable uniformity of the film thickness on the surface, the growth temperature is preferably 494° C. or below, and more preferably 475° C. Although not shown in the graph, the growth temperature of below 450° C. is not preferable from the point of view of productivity, because the growth rate of the thin SiGe film is lowered, and therefore the throughput is lowered.

[0063] Therefore, in order to achieve a favorable uniformity of the film thickness on the surface of the thin SiGe film 10, the growth temperature of the thin SiGe film 10 is preferably 450° C. or above and 494° C. or below, and most preferably 475° C.

[0064] The quality of the thin SiGe film 10 varies depending on the growth pressure. The growth pressure of the thin SiGe film 10 is preferably below 30 Pa, or 150 Pa or above, and more preferably 10 Pa. The own investigation by the present inventor will be described below. The present inventor investigated the conformation of the thin SiGe film by varying the growth pressure of the thin SiGe film formed on a gate dielectric film composed of a SiO2 film through a seed Si film.

[0065] FIGS. 5A to 5C are SEM photographs showing the cross sections of a thin SiGe film when the growth pressure of the thin SiGe film was varied. Specifically, FIGS. 5A, 5B, and 5C are SEM photographs showing film morphology of thin SiGe film when the growth pressure of the thin SiGe film was 30 Pa, 20 Pa, and 200 Pa, respectively.

[0066] As FIG. 5A shows, when the thin SiGe film was formed under a pressure of 30 Pa, voids (in the circled portions) were formed in the thin SiGe film. On the other hand, as FIG. 5B shows, when the thin SiGe film was formed under a pressure of 20 Pa, the number of voids (in the circled portions) decreased significantly, and the film quality was improved. This is because the film deposition rate is low when the thin SiGe film is grown under a pressure lower than 30 Pa, impurities such as hydrogen are released during the deposition of the film, and a polycrystalline thin SiGe film having a low impurity content and a low amorphous-component content can be formed. Thereby, a void-free polycrystalline thin SiGe film of small volume change due to change in temperature that excels in thermal stability can be obtained.

[0067] As FIG. 5C shows, when the thin SiGe film was formed under a pressure of 200 Pa, no voids were formed in the thin SiGe film, and the surface roughness was significantly improved. This is because the film deposition rate is high when the thin SiGe film is grown under a pressure of 200 Pa or above, and the deposition of film is quicker than the crystalline growth of the film. The results of X-ray diffraction analysis showed that the thin SiGe film was amorphous. Thereby, a viod-free amorphous thin SiGe film that excels in surface flatness can be obtained.

[0068] Therefore, in order to achieve favorable thermal stability and surface flatness, the growth pressure of the thin SiGe film 10 is preferably below 30 Pa, or 150 Pa or above, and more preferably 10 Pa.

[0069] Next, as FIG. 2B shows, a thin cap Si film 12 is formed on the thin SiGe film 10 using the above-described LPCVD apparatus. Specifically, the thin SiGe film 10 and the thin cap Si film 12 are continuously formed at the same temperature. Here, the present inventor examined the effect of forming the thin cap Si film 12 on the thin SiGe film 10.

[0070] FIGS. 6A and 6B are SEM photographs showing the cross sections of a thin SiGe film as formed and after forming a thin cap Si film thereon. Here, the Ge content in the thin SiGe film is 0.3 (30%), the growth temperature is 475° C., the growth pressure is 10 Pa, and the thickness of the grown film is 50 nm. The growth temperature of the thin cap Si film is 475° C., the same as the growth temperature of the thin SiGe film, the flow rate of SiH4 is 1 slm, and the thickness of the grown film is 5 nm. The present inventor confirmed the growth rate of the thin cap Si film is 0.25 nm/min at the above-described growth condition. Therefore, the cap Si film cannot be thickened, i.e. the thick cap Si film cannot be applied to the mass production, since throughput is lowered. When the growth temperature is raised for improving the throughput, there are problems that voids generate in the thin SiGe film and the surface of the SiGe film is roughened.

[0071] As FIG. 6A shows, when the thin cap Si film is not formed, that is, immediately after forming the thin SiGe film 10, there are voids in the thin SiGe film 10 (in the circled portions). As FIG. 6B shows, by forming the thin cap Si film 12, voids in the thin SiGe film 10 disappear, and a high-quality thin SiGe film can be obtained. The reason why voids disappear is that the formation of the thin cap Si film 12 lowers the surface energy compared with the case when the thin SiGe film 10 is exposed on the surface, and thermally stabilizes the thin SiGe film 10.

[0072] Therefore, by continuously growing the thin cap Si film 12 after growing the thin SiGe film 10 on the gate dielectric film 6 through the seed Si film 8, a high-quality void-free thin SiGe film can be obtained. The thermal stability of the configuration of the thin SiGe film 10 is also improved. Thus, a void-free thin SiGe film that excels in surface flatness can be obtained.

[0073] The present inventor confirmed the problems of increase in surface roughness of the thin SiGe film and the formation of voids in the film when the thin SiGe film 10 and the thin cap Si film 12 are not continuously formed, or not formed at the same temperature, that is, the temperature is changed. Increase in surface roughness causes increase in non-uniformity of impurity introduction in the consequent process, or increase in non-uniformity of gate processing. The formation of voids deteriorates electrical properties due to the acceleration of the reduction and decomposition of the gate dielectric film even if the voids are minute. However, as described above, the occurrence of such problems can be prevented by continuously forming the thin SiGe film 10 and the thin cap Si film 12 at the same temperature.

[0074] Next, as FIG. 2C shows, the thin cap Si film 12, the thin SiGe film 10, the seed Si film 8, and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed.

[0075] Finally, as FIG. 2D shows, conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 on the upper layer of the silicon substrate 2.

[0076] In the first embodiment, as described above, the thin SiGe film 10 is formed on the gate dielectric film 6 through the seed Si film 8 at low growth temperature (450° C. or above and 494° C. or below), and a thin cap Si film 12 of a thickness of 0.5 nm to 5 nm is formed thereon at the same growth temperature. By forming the thin cap Si film 12, a void-free high-quality thin SiGe film 10 can be formed on the gate dielectric film 6. Thus, the thin SiGe film 10 that excels in the uniformity of film thickness can be formed in the boundary between the gate dielectric film 6 and the gate electrode, and a uniform Ge content in the boundary can be achieved. Therefore, the thickness of the thin SiGe film 10 can be reduced, and high-performance transistors can be manufactured in high reproducibility. Further a high quality thin SiGe film can be attained with restraint of deterioration of throughput, since the thickness of the thin cap Si film 12 is within the range of 0.5 nm to 5 nm.

[0077] In addition, as described above, since the thin SiGe film 10 is a thin film having a favorable film-thickness uniformity, local defective processing such as the dent of the silicon substrate 2 caused by voids in the thin SiGe film during dry etching for forming the gate electrode can be avoided. Thereby, the process margin in the gate processing can be enlarged, and high-performance transistors can be stably manufactured.

[0078] Second Embodiment

[0079] First, the structure of a semiconductor device according to a second embodiment of the present invention will be described.

[0080] FIG. 7 is a schematic cross-sectional view for illustrating a semiconductor device according to a second embodiment of the present invention.

[0081] The semiconductor device according to the second embodiment shown in FIG. 7 differs from the above-described semiconductor device according to the first embodiment in that an upper Si film 16 is further formed on the thin cap Si film 12.

[0082] Specifically, as FIG. 7 shows, in the semiconductor device according to the second embodiment, a gate electrode formed on a silicon substrate 2 through a gate dielectric film 6 comprises a seed Si film 8, a thin SiGe film 10 of a thickness of 50 nm or below, a thin cap Si film 12 of a thickness of 0.5 nm to 5 nm, and an upper Si film 16 of a thickness of 60 nm to 120 nm. The total thickness of the gate electrode is preferably 80 nm to 160 nm.

[0083] Next, a method for manufacturing the semiconductor device will be described.

[0084] FIG. 8 is a process sectional view for illustrating a method for manufacturing the semiconductor device according to the second embodiment.

[0085] First, in the same manner as in the manufacturing method according to the first embodiment, elements up to the thin cap Si film 12 are formed.

[0086] Next, as FIG. 8 shows, an upper Si film 16 is formed on the thin cap Si film 12 using a LPCVD method. The upper Si film 16 can be formed using the above-described batch-type vertical LPCVD apparatus, and the growth conditions of the upper Si film 16 are, for example, an SiH4 flow rate of 1 slm, a growth temperature of 530° C., and a growth pressure of 100 Pa.

[0087] Here, the present inventor examined the effect obtained from the structure having the thin cap Si film 12 underneath the upper Si film 16.

[0088] FIGS. 9A and 9B are SEM photographs showing the cross sections of the thin SiGe film after heat treatment corresponding to the growth of the upper Si film in the case when a thin cap Si film is formed and not formed on the thin SiGe film. Specifically, FIG. 9B is a photograph showing the state of the thin SiGe film after the heat treatment corresponding to the growth of the upper Si film 16 without forming a thin cap Si film after forming a thin SiGe film on the gate dielectric film through a seed Si film; and FIG. 9B is a photograph showing the state of the thin SiGe film after the heat treatment corresponding to the growth of the upper Si film 16 when a thin cap Si film is formed on the thin SiGe film after forming the thin SiGe film on the gate dielectric film through a seed Si film. The Ge content of the thin SiGe film is 0.3 (30%), the growth temperature is 475° C., the thickness of the grown film is 40 nm, and the growth pressure is 200 Pa. As the heat treatment corresponding to the growth of the upper Si film 16, heat treatment is performed at a temperature of 530° C. for about 60 minutes. This heat treatment corresponds the growth of the upper Si film with a thickness of 120 nm.

[0089] As FIG. 9A shows, when no thin cap Si film is formed, the film configuration of the thin SiGe film, which was continuous and flat before heat treatment (i.e., immediately after the growth of the thin SiGe film) is significantly changed, the surface roughness is enlarged, and a discontinuous film is formed (refer to the circled portion in FIG. 9A). In addition, voids are formed in the thin SiGe film after heat treatment. However, as FIG. 9B shows, when the thin cap Si film is formed, the thin SiGe film after heat treatment is maintained continuous, and the flatness is also maintained. Furthermore, no voids are formed in the thin SiGe film after heat treatment.

[0090] Therefore, the formation of the thin cap Si film 12 between the thin SiGe film 10 and the upper Si film 16 can restrict the formation of voids in the thin SiGe film during the formation of the upper Si film 16.

[0091] The temperature for forming the upper Si film 16 is preferably higher than the temperature for forming the underlying thin cap Si film 12 and the thin SiGe film 10, for example, 530° C. to 620° C. Since the formation of the upper Si film 16 at such a high temperature increases the growth rate and improves the throughput, the productivity of semiconductor device is improved.

[0092] FIGS. 10A and 10B are SEM photographs showing the cross sections of a thin SiGe film when the growth temperature of the upper Si film is changed in the formation of the upper Si film on the thin SiGe film through the thin cap Si film after forming the thin SiGe film on the gate dielectric film through the seed Si film. Specifically, FIG. 10A is a photograph showing the state of the laminated film when the upper Si film is formed under the condition of an SiH4 flow rate of 1 slm, a temperature of 530° C., and a pressure of 100 Pa; and FIG. 10B is a photograph showing the state of the laminated film when the upper Si film is formed under the condition of an SiH4 flow rate of 0.6 slm, a temperature of 620° C., and a pressure of 20 Pa. The Ge content of the thin SiGe film is 0.3 (30%), the growth temperature is 475° C., and the thickness of the grown film is 40 nm. The growth temperature of the thin cap Si film is 475° C., the same as the growth temperature of the thin SiGe film, and the thickness of the grown film is 5 nm.

[0093] As FIGS. 10A and 10B show, when the upper Si film is formed under either condition, no voids are formed in the thin SiGe film, and a continuous thin SiGe film can be formed.

[0094] Next, in the same manner as in the first embodiment, the upper Si film 16, the thin cap Si film 12, the thin SiGe film 10, the seed Si film 8, and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed. Finally, conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 in the upper layer of the silicon substrate 2. Performing the above-described processes attains the semiconductor device shown in FIG. 7.

[0095] In the second embodiment, as described above, a thin SiGe film 10 is formed on a gate dielectric film 6 through a seed Si film 8 at low growth temperature, and a thin cap Si film 12 of a thickness of 0.5 nm to 5 nm is continuously formed thereon at the same growth temperature. By forming the thin cap Si film 12, as in the above-described first embodiment, a void-free high-quality thin SiGe film 10 can be formed on the gate dielectric film 6. Thus, the uniform thin SiGe film 10 can be formed in the boundary between the gate dielectric film 6 and the gate electrode, and a uniform Ge content in the boundary can be achieved. Therefore, the thickness of the thin SiGe film 10 can be reduced, and high-performance transistors can be manufactured in high reproducibility.

[0096] In addition, as described above, since the thin SiGe film 10 is a thin film having a favorable film-thickness uniformity, local defective processing such as the dent of the silicon substrate 2 caused by voids in the thin SiGe film 10 during dry etching for forming the gate electrode can be avoided. Thereby, the process margin in the gate processing can be enlarged, and high-performance transistors can be stably manufactured.

[0097] Furthermore, in the second embodiment, an upper Si film 16 is formed on the thin cap Si film 12 at a temperature higher than the growth temperature of the thin SiGe film 10. Therefore, the throughput is increased, and the productivity is improved, since the upper Si film 16 is formed at high deposition rate with maintaining quality of the thin SiGe film 10.

[0098] Third Embodiment

[0099] FIG. 11 is a schematic cross-sectional view for illustrating a semiconductor device according to a third embodiment of the present invention.

[0100] The semiconductor device according to the third embodiment shown in FIG. 11 differs from the above-described semiconductor device according to the second embodiment in that sides of the gate electrode are covered by sidewalls 20, and that silicide layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14. Further, extension regions 18 having an impurity concentration lower than the source-drain regions 14 in the substrate 2 below the sidewalls 20.

[0101] That is to say, the semiconductor device has the silicide layers 22 formed using a well-known salicide technique in uppermost layer of the gate electrode and the source-drain regions 14. The thickness of NiSi layers serving as the silicide layers 22 is, for example, about 10 nm.

[0102] Next, a method for manufacturing the semiconductor device will be described.

[0103] FIGS. 12A and 12B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a third embodiment of the present invention.

[0104] First, in the same manner as in the manufacturing method according to the second embodiment, the upper Si film 16, the thin cap Si film 12, the thin SiGe film 10, the seed Si film 8, and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Next, as FIG. 12A shows, extension regions 18 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a low concentration using the gate electrode as a mask.

[0105] Next, an insulating film such as SiO2 or Si3N4 is formed over the entire of the substrate 2, and the insulating film is etched using an anisotropic dry etching method. Thus, as FIG. 12B shows, sidewalls 20 are formed on the sides of the gate electrode. Source-drain regions 14 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a high concentration using the gate electrode and sidewalls 20 as a mask.

[0106] Next, stacked layers composed of Ni film/TiN film are formed with thickness of 11 nm/10 nm over the entire of the substrate, and a heat treatment is performed. Thus, Ni film is reacted with the upper Si film 16 and the source-drain regions 14, and NiSi layers 22 are formed. Here, quality of the thin SiGe film is maintained during the heat treatment by the presence of the cap Si film 12. The semiconductor device shown in FIG. 11 is attained by getting rid of the Ni film/TiN film which has not reacted using chemical solution.

[0107] In the third embodiment, as described above, the NiSi layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14 using salicide technique. The quality of the thin SiGe film 10 can be maintained even if the heat treatment for forming the NiSi layers 22 is done in addition to the effects attained in the second embodiment.

[0108] Fourth Embodiment

[0109] FIG. 13 is a schematic cross-sectional view for illustrating a semiconductor device according to a fourth embodiment of the present invention.

[0110] The semiconductor device according to the fourth embodiment shown in FIG. 13 differs from the above-described semiconductor device according to the first embodiment in that thin SiGe film 10 made by stacking a plurality of SiGe layers 10a and 10b. This difference will be described as follows.

[0111] In the fourth embodiment, on the seed Si film 8 is formed the thin SiGe film 10 by stacking a first SiGe layer 10a and a second SiGe layer 10b. The first and second SiGe layers 10a and 10b differ in Ge content X of formula Si(1-x)Gex representing the first and second SiGe layers 10a and 10b respectively. The first and second SiGe layers 10a and 10b are continuously formed at the same growth temperature. Here, each Ge content X of the SiGe layers 10a and 10b is 0.15 or more and smaller than 0.4. The film thickness of the first SiGe layer 10a may differ from the film thickness if the second SiGe layer 10b. Total thickness of the SiGe layers 10a and 10b is preferably 50 nm or below.

[0112] On the second SiGe layer 10b is formed the thin cap Si film 12 of the thickness of 0.5 nm to 5 nm. The first and second SiGe layer 10a and 10b and the thin cap Si film 12 are continuously formed at the same temperature.

[0113] Next, a method for manufacturing the semiconductor device will be described.

[0114] FIGS. 14A and 14B are process sectional views for illustrating a method for manufacturing the semiconductor device according to the fourth embodiment.

[0115] First, in the same manner as in the manufacturing method according to the first embodiment, the gate dielectric film 6 is formed on the substrate 2, and the seed Si film 8 is formed on the gate dielectric film 6.

[0116] Next, the first SiGe layer 10a is formed on the seed Si film 8, the second SiGe layer 10b is formed on the first SiGe layer 10a, and the thin cap Si film 12 is formed on the second SiGe layer 10b. Thereby, the structure shown in FIG. 14A is attained. Here, the first SiGe layer 10a, the second SiGe layer 10b and the thin cap Si film 12 are continuously formed at the same temperature. The forming temperature is preferably 450° C. or above and 494° C. or below, and most preferably 475° C. The first and second SiGe layers having different Ge content are formed by changing the flow-rate ratio of H2-diluted 10% GeH4 to SiH4.

[0117] Next, as FIG. 14B shows, the thin cap Si film 12, the second SiGe layer 10b, the first SiGe layer 10a, the seed Si film 8, and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed.

[0118] Finally, conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 in the upper layer of the silicon substrate 2. Performing the above-described processes attains the semiconductor device shown in FIG. 13.

[0119] Therefore, according to the fourth embodiment, the equivalent effects as the effects obtained in the first embodiment can be obtained.

[0120] In the fourth embodiment, although the thin SiGe film 10 is formed by two SiGe layers 10a and 10b, the thin SiGe film 10 may be formed by stacking three or more SiGe layers.

[0121] Although the thin SiGe film 10 is formed by the SiGe layers having different Ge content, the thin SiGe film 10 may be formed by stacking an amorphous SiGe layer and a polycrystalline SiGe layer. In this case, the amorphous SiGe layer can be grown under a growth pressure 150 Pa, and the polycrystalline SiGe layer can be grown under a growth pressure of 30 Pa.

[0122] Further, an upper Si may be formed on thin cap Si film 12 using the same manner as in the manufacturing method according to the second embodiment (The same applies to second to fifth embodiments described later.).

[0123] Fifth Embodiment

[0124] FIG. 15 is a schematic cross-sectional view for illustrating a semiconductor device according to a fifth embodiment of the present invention.

[0125] In the semiconductor device shown in FIG. 15, the gate electrode comprises a plurality of SiGe layers 10a and 10b and a plurality of thin cap Si films 12a and 12b. The SiGe layers and the thin cap films are stacked alternately. The difference between the fifth embodiment and the first embodiment will be described as follows.

[0126] In the fifth embodiment, on the seed Si film 8 is formed a first SiGe layer 10a, and a first thin cap Si film 12a is formed on the first SiGe layer 10a. On the first thin cap Si film 12a is formed a second SiGe layer 10b, and a second thin cap Si film 12b is formed on the second SiGe layer 10b. Here, each Ge content X of the SiGe layers 10a and 10b is 0.15 or more and smaller than 0.4. The film thickness of the first SiGe layer 10a may differ from the film thickness if the second SiGe layer 10b. Total thickness of the SiGe layers 10a and 10b is preferably 50 nm or below. The each film thickness of the first and second thin cap Si films 12a and 12b is preferably 0.5 nm to 5 nm.

[0127] Next, a method for manufacturing the semiconductor device will be described.

[0128] FIGS. 16A and 16B are process sectional views for illustrating a method for manufacturing the semiconductor device according to the fifth embodiment.

[0129] First, in the same manner as in the manufacturing method according to the first embodiment, the gate dielectric film 6 is formed on the substrate 2, and the seed Si film 8 is formed on the gate dielectric film 6.

[0130] Next, the first SiGe layer 10a is formed on the seed Si film 8, and the first thin cap Si film 12a is formed on the first SiGe layer 10a. The second SiGe layer 10b is formed on the first thin cap Si film 12a, and the second thin cap Si film 12b is formed on the second SiGe layer 10b. Thereby, the structure shown in FIG. 16A is attained. Here, the first SiGe layer 10a, the first thin cap Si film 12a, the second SiGe layer 10b and the second thin cap Si film 12b are continuously formed at the same temperature. The forming temperature is preferably 450° C. or above and 494° C. or below, and most preferably 475° C.

[0131] Next, as FIG. 16B shows, the second thin cap Si film 12b, the second SiGe layer 10b, the first thin cap Si film 12a, the first SiGe layer 10a, the seed Si film 8, and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed.

[0132] Finally, conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 in the upper layer of the silicon substrate 2. Performing the above-described processes attains the semiconductor device shown in FIG. 15.

[0133] Therefore, according to the fifth embodiment, the equivalent effects as the effects obtained in the first embodiment can be obtained.

[0134] In the fourth embodiment, the first and second SiGe layers 10a and 10b may be formed under the same growth condition, and may be formed under the different growth conditions as described in the fourth embodiment.

[0135] Sixth Embodiment

[0136] A sixth embodiment is attained by applying the fourth embodiment to the third embodiment.

[0137] FIG. 17 is a schematic cross-sectional view for illustrating a semiconductor device according to a sixth embodiment of the present invention.

[0138] In the sixth embodiment, on the seed Si film 8 is formed the thin SiGe film 10 by stacking a first SiGe layer 10a and a second SiGe layer 10b. The first and second SiGe layers 10a and 10b differ in Ge content X of formula Si(1-x)Gex representing the first and second SiGe layers 10a and 10b respectively. The first and second SiGe layers 10a and 10b are continuously formed at the same growth temperature. Here, each Ge content X of the SiGe layers 10a and 10b is 0.15 or more and smaller than 0.4. The film thickness of the first SiGe layer 10a may differ from the film thickness if the second SiGe layer 10b. Total thickness of the SiGe layers 10a and 10b is preferably 50 nm or below.

[0139] On the second SiGe layer 10b is formed the thin cap Si film 12 of the thickness of 0.5 nm to 5 nm. The first and second SiGe layer 10a and 10b and the thin cap Si film 12 are continuously formed at the same temperature. The upper Si film 16 of the thickness of 60 nm to 120 nm is formed on the thin cap Si film 12.

[0140] Sides of the gate electrode are covered by sidewalls 20. Extension regions 18 having an impurity concentration lower than the source-drain regions 14 in the substrate 2 below the sidewalls 20. NiSi layers 22 are formed as silicide layers in upper portions of the upper Si film 16 and source-drain regions 14.

[0141] Next, a method for manufacturing the semiconductor device will be described.

[0142] First, in the same manner as in the manufacturing method according to the first embodiment, the gate dielectric film 6 is formed on the substrate 2, and the seed Si film 8 is formed on the gate dielectric film 6.

[0143] Next, in the same manner as in the manufacturing method according to the fourth embodiment, the first SiGe layer 10a, the second SiGe layer 10b and the thin cap Si film 12 are continuously formed on the seed Si film 8 at the same temperature.

[0144] Next, in the same manner as in the manufacturing method according to the second embodiment, the upper Si film 16 is formed on the thin cap Si film 12 at a temperature higher than the growth temperature of the first SiGe layer 10a.

[0145] The upper Si film 16, thin cap Si film 12, the second SiGe layer 10b, the first SiGe layer 10a, the seed Si film 8, and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed. Extension regions 18 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a low concentration using the gate electrode as a mask. sidewalls 20 are formed on the sides of the gate electrode. Source-drain regions 14 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a high concentration using the gate electrode and sidewalls 20 as a mask. Further, NiSi layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14 using salicide technique. Performing the above-described processes attains the semiconductor device shown in FIG. 17.

[0146] Therefore, according to the sixth embodiment, the equivalent effects as the effects obtained in the first, second and third embodiments can be obtained.

[0147] Seventh Embodiment

[0148] A seventh embodiment is attained by applying the fifth embodiment to the third embodiment.

[0149] FIG. 18 is a schematic cross-sectional view for illustrating a semiconductor device according to a seventh embodiment of the present invention.

[0150] In the seventh embodiment, on the seed Si film 8 is formed a first SiGe layer 10a, and a first thin cap Si film 12a is formed on the first SiGe layer 10a. On the first thin cap Si film 12a is formed a second SiGe layer 10b, and a second thin cap Si film 12b is formed on the second SiGe layer 10b. Here, each Ge content X of the SiGe layers 10a and 10b is 0.15 or more and smaller than 0.4. The film thickness of the first SiGe layer 10a may differ from the film thickness if the second SiGe layer 10b. Total thickness of the SiGe layers 10a and 10b is preferably 50 nm or below. The each film thickness of the first and second thin cap Si films 12a and 12b is preferably 0.5 nm to 5 nm.

[0151] The upper Si film 16 of the thickness of 60 nm to 120 nm is formed on the thin cap Si film 12.

[0152] Sides of the gate electrode are covered by sidewalls 20. Extension regions 18 having an impurity concentration lower than the source-drain regions 14 in the substrate 2 below the sidewalls 20. NiSi layers 22 are formed as silicide layers in upper portions of the upper Si film 16 and source-drain regions 14.

[0153] Next, a method for manufacturing the semiconductor device will be described.

[0154] First, in the same manner as in the manufacturing method according to the first embodiment, the gate dielectric film 6 is formed on the substrate 2, and the seed Si film 8 is formed on the gate dielectric film 6.

[0155] Next, in the same manner as in the manufacturing method according to the fifth embodiment, the first SiGe layer 10a, the first thin cap Si film 12a, the second SiGe layer 10b and the second thin cap Si film 12b are continuously formed on the seed Si film 8 at the same temperature.

[0156] Next, in the same manner as in the manufacturing method according to the second embodiment, the upper Si film 16 is formed on the second thin cap Si film 12b at a temperature higher than the growth temperature of the first SiGe layer 10a.

[0157] The upper Si film 16, the second thin cap Si film 12b, the second SiGe layer 10b, the first thin cap Si film 12a, the first SiGe layer 10a, the seed Si film 8, and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed. Extension regions 18 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a low concentration using the gate electrode as a mask. sidewalls 20 are formed on the sides of the gate electrode. Source-drain regions 14 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a high concentration using the gate electrode and sidewalls 20 as a mask. Further, NiSi layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14 using salicide technique. Performing the above-described processes attains the semiconductor device shown in FIG. 18.

[0158] Therefore, according to the seventh embodiment, the equivalent effects as the effects obtained in the first, second and third embodiments can be obtained.

[0159] This invention, when practiced illustratively in the manner described above, provides the following major effects:

[0160] According to the present invention, a high-quality thin SiGe film free of voids can be formed on a gate dielectric film.

[0161] Further, the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention.

[0162] The entire disclosure of Japanese Patent Application No. 2003-129986 filed on May 8, 2003 containing specification, claims, drawings and summary are incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising:

a gate dielectric film on a substrate; and

a gate electrode on the gate dielectric film, having:

a seed Si film on the gate dielectric film;

an SiGe film on the seed Si film and having a thickness not exceeding 50 nm; and

a cap Si film on the thin SiGe film and having a thickness in a range from 0.5 nm to 5 nm.

2. The semiconductor device according to claim 1, wherein the cap Si film lowers surface energy of the SiGe film.

3. The semiconductor device according to claim 1, wherein the gate electrode further includes an upper Si film on the cap Si film.

4. The semiconductor device according to claim 1, wherein the gate electrode further has an upper Si film on the cap Si film and a silicide layer in an upper portion of the upper Si film.

5. The semiconductor device according to claim 1, wherein the SiGe film includes a plurality of laminated SiGe layers.

6. The semiconductor device according to claim 5, wherein the plurality of SiGe layers differ in proportion of Ge content.

7. The semiconductor device according to claim 1, wherein the gate electrode has a plurality of SiGe layers and a plurality of cap Si films, and the SiGe layers and cap Si films are stacked alternately.

8. The semiconductor device according to claim 1, wherein proportion of Ge content of the SiGe film is in a range from 0.15 to less than 0.4.

9. A method for manufacturing a semiconductor device, comprising:

forming a gate dielectric film on a substrate;

forming a seed Si film on the gate dielectric film;

forming a SiGe film on the seed Si film at a temperature between 450° C. and 494° C., and continuously forming a cap Si film with a thickness of 0.5 nm to 5 nm on the SiGe film at the same temperature at which the SiGe film is formed;

patterning the cap Si film, the SiGe film, and the seed Si film to form a gate electrode; and

forming source-drain regions the substrate by ion implantation using the gate electrode as a mask.

10. The method for manufacturing a semiconductor device according to claim 9, wherein surface energy of the SiGe film is lowered by forming the cap Si film.

11. The method for manufacturing a semiconductor device according to claim 9, including forming the SiGe film at a pressure lower than 30 Pa, or 150 Pa or higher.

12. A method for manufacturing a semiconductor device, comprising:

forming a gate dielectric film on a substrate;

forming a seed Si film on the gate dielectric film;

forming a SiGe film on the seed Si film at a temperature between 450° C. and 494° C., and continuously forming a cap Si film with a thickness of 0.5 nm to 5 nm on the SiGe film at the same temperature at which the SiGe film is formed;

forming an upper Si film on the cap Si film at a temperature higher than the temperature of forming the SiGe film;

patterning the upper Si film, the cap Si film, the SiGe film, and the seed Si film to form a gate electrode; and

forming source-drain regions in the substrate by ion implantation using the gate electrode as a mask.

13. The method for manufacturing a semiconductor device according to claim 12, including forming the upper Si film at a temperature between 530° C. and 620° C.

14. The method for manufacturing a semiconductor device according to claim 12, wherein surface energy of the thin SiGe film is lowered by forming the thin cap Si film.

15. The method for manufacturing a semiconductor device according to claim 12, including forming the SiGe film at a pressure lower than 30 Pa, or 150 Pa or higher.

16. The method for manufacturing a semiconductor device according to claim 12, wherein forming the SiGe film comprises:

forming a first SiGe layer on the seed Si film; and

forming a second SiGe layer on the first SiGe layer, the second SiGe layer being different in composition from the first SiGe layer.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the proportion of Ge content of each of the first and second SiGe layers is different.

18. A method for manufacturing a semiconductor device, comprising:

forming a gate dielectric film on a substrate;

forming a seed Si film on the gate dielectric film;

forming a SiGe film on the seed Si film at a temperature between 450° C. and 494° C., and continuously forming a cap Si film with a thickness of 0.5 nm to 5 nm on the SiGe film at the same temperature at which the SiGe film is formed;

forming an upper Si film on the cap Si film at a temperature higher than the temperature at which the SiGe film is formed;

patterning the upper Si film, the cap Si film, the SiGe film, and the seed Si film to form a gate electrode;

forming extension regions in an upper layer of the substrate by ion implantation, using the gate electrode as a mask;

forming sidewalls covering sides of the gate electrode after forming the extension regions;

forming source and drain regions in the substrate by ion implantation, using the gate electrode and the sidewalls as a mask; and

forming suicide layers in upper portions of the upper Si film and the source and drain regions using a saliciding technique.

19. A method for manufacturing a semiconductor device, comprising:

forming a gate dielectric film on a substrate;

forming a seed Si film on the gate dielectric film;

forming a first SiGe layer on the seed Si film at a temperature between 450° C. and 494° C., and continuously forming a first cap Si film with a thickness of 0.5 nm to 5 nm on the first SiGe layer at the same temperature at which the first SiGe layer is formed, and continuously forming a second SiGe layer on the first cap Si layer at the same temperature at which the first SiGe layer is formed, and continuously forming a second cap Si film with a thickness of 0.5 nm to 5 nm on the second SiGe layer at the same temperature at which the first SiGe layer is formed;

patterning the second cap Si film, the second SiGe layer, the first cap Si film, the first SiGe layer, and the seed Si film to form a gate electrode; and

forming source and drain regions in the substrate by ion implantation, using the gate electrode as a mask.

20. A method for manufacturing a semiconductor device, comprising:

forming a gate dielectric film on a substrate;

forming a seed Si film on the gate dielectric film;

forming a first SiGe layer on the seed Si film at a temperature between 450° C. and 494° C., and continuously forming a first cap Si film with a thickness of 0.5 nm to 5 nm on the first SiGe layer at the same temperature at which the first SiGe layer is formed, and continuously forming a second SiGe layer on the first cap Si layer at the same temperature at which the first SiGe layer is formed, and continuously forming a second cap Si film with a thickness of 0.5 nm to 5 nm on the second SiGe layer at the same temperature at which the first SiGe layer is formed;

forming an upper Si film on the second cap Si film at a temperature higher than the temperature at which the first SiGe layer is formed;

patterning the upper Si film, the second cap Si film, the second SiGe layer, the first cap Si film, the first SiGe layer, and the seed Si film to form a gate electrode;

forming extension regions in the substrate by ion implantation, using the gate electrode as a mask;

forming sidewalls covering sides of the gate electrode after forming the extension regions;

forming source and drain regions in the substrate by ion implantation, using the gate electrode and the sidewalls as a mask; and

forming silicide layers in upper portions of the upper Si film and the source and drain regions using a saliciding technique.