Insulated Gate Field Effect Transistor In Integrated Circuit Patents (Class 257/368)
  • Patent number: 11152355
    Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fan-Shuen Meng, Huang-Kui Chen, Min-Yann Hsieh
  • Patent number: 11152501
    Abstract: A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: October 19, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura
  • Patent number: 11145759
    Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Liang-Yi Chen
  • Patent number: 11145727
    Abstract: A semiconductor structure includes a pair of active regions, a first isolation structure, a gate structure, and a pair of contacts. The first isolation structure is disposed between the active regions. The gate structure is disposed on the first isolation structure. The contacts are respectively disposed on the active regions. Each of the contacts has a bottom surface and a sidewall substantially perpendicular to the bottom surface.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 12, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Sheng-Hwa Lee, Hsiu-Ming Chen
  • Patent number: 11137453
    Abstract: A stress compensation control circuit of the present invention is provided which is capable of using a compensation error similar to that at room temperature even at a high temperature and reducing the area of a chip for a semiconductor sensor as compared with the related art. The stress compensation control circuit compensates for a change in detection sensitivity due to a stress to be applied to the semiconductor sensor. The stress compensation control circuit includes a stress compensation voltage generating circuit generating a stress compensation voltage corresponding to the applied stress in accordance with a difference between changes in transconductance due to stresses in a first depletion transistor and a first enhancement transistor, and performs compensation for the detection sensitivity in correspondence to the stress applied to the semiconductor sensor.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: October 5, 2021
    Assignee: Ablic Inc.
    Inventors: Tomoki Hikichi, Kentaro Fukai
  • Patent number: 11133332
    Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: September 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11121174
    Abstract: A memory cell is provided in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source/drain contact structures of a transistor, and a lower contact structure is connected to another of the source/drain contact structures of the transistor. In the present application, the MRAM device and the lower contact structure are present in the middle-of-the-line ((MOL) not the back-end-of-the-line (BEOL). Moreover, the bottom electrode of the MRAM device, and a lower portion of the lower contact structure are present in a same dielectric material (i.e., a MOL dielectric material).
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Michael Rizzolo, Ruilong Xie
  • Patent number: 11121023
    Abstract: A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 14, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jiehui Shu, Hong Yu, Jinping Liu, Hui Zang
  • Patent number: 11114390
    Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: September 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
  • Patent number: 11114447
    Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, TaeYong Kwon, Dongwon Kim
  • Patent number: 11106854
    Abstract: A method including the operations of receiving a preliminary device layout including a plurality of active areas, analyzing the preliminary device layout to identify empty areas between the plurality of active areas, determining the configurations of the active areas bordering the empty areas, selecting a transition cell from a transition cell library in which the transition cell has a transitional configuration for reducing density gradient effects in the active areas adjacent the transition cell, and inserting the transition cells into the empty areas to define a modified device layout.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Hsu Chuang, Wen-Shen Chou, Yung-Chow Peng, Yu-Tao Yang, Yun-Ru Chen
  • Patent number: 11094597
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie, Chih-Yung Lin
  • Patent number: 11088024
    Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) including IC elements, e.g., memory components. A first contact etch stop layer is formed over the IC elements. A TFR layer stack including a TFR etch stop layer, a TFR film layer, and a second contact etch stop layer is formed over the first contact etch stop layer, and in some cases over one or more pre-metal dielectric layers. A patterned mask is formed over the IC stack, and the stack is etched, through both the first and second contact etch stop layers, to simultaneously form (a) first contact openings exposing contact regions of the IC elements and (b) second contact opening(s) exposing the TFR film layer. The first and second contact openings are filled with conductive material to form conductive contacts to the IC elements and the TFR film layer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: August 10, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Patent number: 11069685
    Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Chan Suh, Gi-Gwan Park, Dong-Woo Kim, Dong-Suk Shin
  • Patent number: 11069677
    Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 20, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Patent number: 11069579
    Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiang-Bau Wang, Li-Wei Yin, Chen-Huang Huang, Ming-Jhe Sie, Ryan Chia-Jen Chen
  • Patent number: 11062953
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
  • Patent number: 11063136
    Abstract: A semiconductor device structure and fabrication method thereof are disclosed. The method may include providing a substrate; forming a gate structure on the substrate; forming a spacer structure on the gate structure, and forming a contacting conductive structure on the spacer structure. The spacer structure may cover a side wall of the gate structure, and may include a first spacer layer having a first dielectric constant and a second spacer layer having a second dielectric constant different from the first dielectric constant. The contacting conductive structure may cover a side wall of the spacer structure that is defined by a first side surface of the first spacer layer and a second side surface of the second space. The ratio of the area of the second side surface of the second spacer layer to the total area of the side wall of the spacer structure may be in a range from 78% to 98%.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 13, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Rongfu Zhu
  • Patent number: 11063132
    Abstract: A semiconductor device includes a semiconductor substrate, a trench isolator portion in the semiconductor substrate, a dummy gate on the semiconductor substrate, a first doped region between the trench isolator portion and the dummy gate in the semiconductor substrate, and a first connecting member electrically connected the dummy gate with the first doped region. With the dummy gate electrically connected to the first doped region, a transistor including the dummy gate is turned off, thereby preventing the occurrence of current leakage and improving the reliability of a memory device having the semiconductor device.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 13, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Gang Qian, Yiming Miao, Yanlin Sun, Xubo Chen
  • Patent number: 11063043
    Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Shu Wu, Shu-Uei Jang, Wei-Yeh Tang, Ryan Chia-Jen Chen, An-Chyi Wei
  • Patent number: 11056594
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region adjacent to the well pick-up region. The semiconductor device structure also includes a first fin structure with a first width and a third fin structure with a third width formed adjacent to each other in the well pick-up region and a second fin structure with a second width and a fourth fin structure with a fourth width formed adjacent to each other in the active region. The first width is different than the second width, the third width is different than the fourth width, and the first width is substantially equal to or greater than the third width.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 11056537
    Abstract: A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Richard A. Conti, Ruilong Xie, Kangguo Cheng
  • Patent number: 11049940
    Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Juntao Li, Heng Wu
  • Patent number: 11043577
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 11043598
    Abstract: A method of forming a semiconductor structure includes forming a metal liner above and in direct contact with a bottom source/drain region, a fin spacer on sidewalls of a fin extending upward from a substrate and a hard mask positioned on top of the fin, the bottom source/drain region includes an epitaxially grown material in direct contact with a bottom portion of the fin not covered by the fin spacer, forming an organic planarization layer directly above the metal liner, simultaneously etching the organic planarization layer and the metal liner until all portions of the metal liner perpendicular to the substrate have been removed and only portions of the metal liner parallel to the substrate remain in contact with the bottom source/drain region, and annealing the semiconductor structure to form a metal silicide layer from the portions of the metal liner in contact with the bottom source/drain region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Soon-Cheon Seo, Injo Ok, Alexander Reznicek
  • Patent number: 11043408
    Abstract: A dummy gate layer is formed over a substrate. A patterned mask is formed over the dummy gate layer. The patterned mask includes an opening. The opening is etched into the dummy gate layer. The patterned mask serves as a protective mask as the opening is etched. A lateral etching process is performed to portions of the dummy gate layer laterally exposed by the opening. The lateral etching process etches away the dummy gate layer without substantially affecting the patterned mask. After the lateral etching process is performed, a dielectric material is formed in the opening. An air gap is formed in the dielectric material. After the air gap is formed, the patterned mask and portions of the dielectric material formed over the patterned mask are removed. The dummy gate layer is replaced with a metal-containing gate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11043429
    Abstract: A method is presented for forming dielectric isolated fins. The method includes forming a plurality of fin structures over a semiconductor substrate, forming spacers adjacent each of the plurality of fins, recessing the semiconductor substrate to form bottom fin profiles, and forming shallow trench isolation (STI) regions between the plurality of fins and the bottom fin profiles. The method further includes etching the STI regions, a select number of the plurality of fins, and a portion of a select number of the bottom fin profiles to create cavities between a mechanical anchor defined between a pair of fins of the plurality of fins, the etching resulting in undercutting of remaining fins.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Jay W. Strane
  • Patent number: 11037937
    Abstract: Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: June 15, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Meixiong Zhao, Randy W. Mann, Sanjay Parihar, Anton Tokranov, Hong Yu, Hongliang Shen, Guoxiang Ning
  • Patent number: 11018060
    Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 25, 2021
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Yang Beom Kang, Kang Sup Shin
  • Patent number: 11011516
    Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-han Lee, Sun-ghil Lee, Myung-il Kang, Jeong-yun Lee, Seung-hun Lee, Hyun-jung Lee, Sun-wook Kim
  • Patent number: 11011623
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Patent number: 11011635
    Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 18, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sheng-Chin Kung, Hua Chung
  • Patent number: 11004850
    Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Junli Wang, Michael P. Belyansky
  • Patent number: 10998315
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench within the substrate. The trench surrounds the source region and the drain region. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate metal having a first sidewall and a second gate metal having a first outer sidewall that contacts the first sidewall directly over the upper surface of the substrate.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Patent number: 10991699
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 27, 2021
    Inventors: Hui-Jung Kim, Min Hee Cho, Bong-Soo Kim, Junsoo Kim, Satoru Yamada, Wonsok Lee, Yoosang Hwang
  • Patent number: 10985161
    Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Wenyu Xu, Xin Miao, Chen Zhang, Kangguo Cheng
  • Patent number: 10978589
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 13, 2021
    Assignee: United Microelectronics Corp.
    Inventors: Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 10964813
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an LDD region below the first dummy gate structure. The first dummy gate structure includes a first dummy gate dielectric layer at the first device region, a first dummy gate on the first dummy gate dielectric layer, and a first spacer layer at a side wall of the first dummy gate. The second dummy gate structure includes a second dummy gate dielectric layer at the second device region, a second dummy gate on the second dummy gate dielectric layer, and a second spacer layer at a side wall of the second dummy gate.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Fei Zhou
  • Patent number: 10965279
    Abstract: A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180° out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yogesh Kumar Ramadass, Bhushan Talele, Shailendra Kumar Baranwal, Yinglai Xia, Junmin Jiang
  • Patent number: 10964600
    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, including isolation regions and a device region between adjacent isolation regions; a plurality of fin structures, formed on the device region of the substrate; and an isolation layer, formed on the substrate. A top surface of the isolation layer is lower than top surfaces of the fin structures. A height of each fin structure exposed by the isolation layer is identical.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10957794
    Abstract: According to an embodiment of the present invention, a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a first vertical fin connected to a gate and a first doped region, wherein the first doped region is formed on a substrate, a second vertical fin connected to the gate and a source or a drain (S/D), wherein the S/D is formed on the substrate and a bottom contact self-aligned with and connected to the gate and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Patent number: 10957544
    Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 23, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Andrew M. Greene, Ryan O. Jung, Ruilong Xie
  • Patent number: 10957604
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10950732
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a gate structure formed over a substrate. A spacer layer is formed on side portions of the gate structure. A first dielectric layer is formed over the gate structure. A conductive cap layer passes through the first dielectric layer and is formed over the gate structure. A top surface of the conductive cap layer is above a top surface of the spacer layer. The semiconductor device further includes a conductive layer formed over the conductive cap layer. The conductive layer is electrically coupled with the conductive cap layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 10943820
    Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, and depositing a first dielectric material on the first semiconductor fin and the second semiconductor fin on the semiconductor substrate using an atomic layer deposition process. There is a first trench between the first semiconductor fin and the second semiconductor fin. The method also includes filling the first trench with a flowable dielectric material, and heating the flowable dielectric material and the first dielectric material to form an isolation structure between the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Wei-Jin Li, Chung-Chi Ko, Yu-Cheng Shiau, Han-Sheng Weng, Chih-Tang Peng, Tien-I Bao
  • Patent number: 10943814
    Abstract: A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ryan W. Sporer, Jiehui Shu
  • Patent number: 10943828
    Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10937793
    Abstract: According to an embodiment of the present invention a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a vertical fin. The vertical fin includes a bottom source or drain (S/D) and a top (S/D) each formed in a doped region. The fin also includes a gate wrapping around a channel region. A bottom contact is connected to the gate, the first doped region and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Patent number: 10937876
    Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ding-Kang Shih, Sung-Li Wang, Pang-Yen Tsai
  • Patent number: 10937861
    Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 2, 2021
    Assignee: Tessera, Inc.
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty