Insulated Gate Field Effect Transistor In Integrated Circuit Patents (Class 257/368)
  • Patent number: 10811415
    Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rwik Sengupta, Joon Goo Hong, Vassilios Gerousis, Mark S. Rodder
  • Patent number: 10811520
    Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 20, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Huajun Jin, Guipeng Sun
  • Patent number: 10804157
    Abstract: A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. The separation region comprises a first separation region neighboring a first side of the fins and a second separation region neighboring a second side of the fins; forming a first and a second insulation layers on the substrate structure; forming a barrier layer; performing a first etching process using the barrier layer as a mask; removing the barrier layer; performing a second etching process using the remaining second insulation layer as a mask; forming a third insulation layer on side surfaces of the remaining first and second insulation layers; and performing a third etching process using the remaining second insulation layer and the third insulation layer as a mask.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 13, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hai Zhao
  • Patent number: 10804222
    Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicrolectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Patent number: 10804381
    Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes an isolation feature over the substrate and over sides of the fin feature; a semiconductor oxide feature including the first semiconductor material and disposed on sidewalls of the first portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extending into recesses that are into a top portion of the semiconductor oxide feature and below the second portion of the fin feature.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Carlos H. Diaz, Chih-Hao Wang, Zhiqiang Wu
  • Patent number: 10804163
    Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10804271
    Abstract: Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Patent number: 10797131
    Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Pakal Technologies, Inc.
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
  • Patent number: 10797223
    Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bin Liu, Eng Huat Toh, Yinjie Ding, Kangho Lee, Elgin Kiok Boone Quek
  • Patent number: 10784335
    Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 22, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Shinichiro Miyahara, Atsuya Akiba, Katsumi Suzuki, Yukihiko Watanabe
  • Patent number: 10784379
    Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
  • Patent number: 10784168
    Abstract: The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Meng-Hung Shen, Ru-Gun Liu, Wei-Cheng Lin
  • Patent number: 10770598
    Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
  • Patent number: 10763342
    Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 1, 2020
    Assignees: Interanational Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Cheng Chi, Ruilong Xie
  • Patent number: 10763254
    Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Soo Kim, Gi Gwan Park, Jung Hun Choi, Koung Min Ryu, Sun Jung Lee
  • Patent number: 10763213
    Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 1, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Patent number: 10755919
    Abstract: A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10756095
    Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Theodore W. Houston, Thomas J. Aton, Scott W. Jessen
  • Patent number: 10749024
    Abstract: A semiconductor device of an embodiment includes a first region including a first portion of a semiconductor layer having first and second planes, a first trench, a first gate electrode, a first source electrode and a drain electrode; a second region adjacent to the first region in a first direction and including a second portion of the semiconductor layer, a second trench, a second gate electrode, a second source electrode on the first plane side, and the drain electrode; a third region adjacent to the first region in a second direction crossing the first direction and including a third portion of the semiconductor layer, a third trench, a third gate electrode, a third source electrode on the first plane side, and the drain electrode; a first gate electrode pad connected to the first gate electrode; and a second gate electrode pad connected to the second and third gate electrodes.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 18, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Akihiro Tanaka
  • Patent number: 10748813
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shih-Wei Wang
  • Patent number: 10741564
    Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, TaeYong Kwon, Dongwon Kim
  • Patent number: 10734531
    Abstract: A device and method for manufacturing a two-dimensional electrostrictive field effect transistor having a substrate, a source, a drain, and a channel disposed between the source and the drain. The channel is a two-dimensional layered material and a gate proximate the channel. The gate has a column of an electrostrictive or piezoelectric or ferroelectric material, wherein an electrical input to the gate produces an elongation of the column that applies a force or mechanical stress on the channel and reduces a bandgap of two-dimensional material such that the two-dimensional electrostrictive field effect transistor operates with a subthreshold slope that is less than 60 mV/decade.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: August 4, 2020
    Assignee: The Penn State Research Foundation
    Inventor: Saptarshi Das
  • Patent number: 10727343
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region. Each of the well pick-up region and the active region includes a first well region and a second well region that have different conductivity types. There is a well boundary between the first well region and the second well region. A first fin structure is in the first well region of the well pick-up region and second fin structures are in the first well region of the active region. The minimum distance between the well boundary and the first fin structure is greater than the minimum distance between the well boundary and one of the second fin structures that is closest to the well boundary.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 10727336
    Abstract: A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalk. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalk. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 10714597
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • Patent number: 10714349
    Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz
  • Patent number: 10707349
    Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ka-Hing Fung, Zhiqiang Wu
  • Patent number: 10707133
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Anthony St. Amour, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10707216
    Abstract: Provided is a method for manufacturing a semiconductor device including: patterning a substrate to form a plurality of active patterns including two adjacent active patterns having a first trench therebetween; forming a semiconductor layer on the plurality of active patterns to cover the plurality of active patterns; forming a device isolation layer on the semiconductor layer to cover the semiconductor layer for oxidization and fill the first trench; patterning the device isolation layer and the plurality of active patterns so that a second trench intersecting the first trench is formed and the two active patterns protrudes from the device isolation layer in the second trench; and forming a gate electrode in the second trench. Here, a first thickness of the semiconductor layer covering a top surface of each of the two active patterns is greater than a second thickness of the semiconductor layer covering a bottom of the first trench.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmi Yoon, Chunhyung Chung
  • Patent number: 10707322
    Abstract: A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 7, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Yen Chen, Shin-Cheng Lin, Hsin-Chih Lin
  • Patent number: 10700064
    Abstract: Devices and methods are provided to fabricate multi-threshold voltage gate-all-around field-effect transistor devices (e.g., nanosheet field-effect transistor devices) wherein threshold voltage tuning is achieved by adjusting a channel spacing between active channel layers of the gate-all-around field-effect transistor devices in different device regions, and forming common high-k dielectric/metal gate structures for the gate-all-around field-effect transistor devices to achieve different thickness combinations of common work function metal layers in different channel spacings between active channel layers of the gate-all-around field-effect transistor devices.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, ChoongHyun Lee
  • Patent number: 10693013
    Abstract: A minute transistor with low parasitic capacitance, high frequency characteristics, favorable electrical characteristics, stable electrical characteristics, and low off-state current is provided. A semiconductor device includes a semiconductor over a substrate, a source and a drain over the semiconductor, a first insulator over the source and the drain, a second insulator over the semiconductor, a third insulator in contact with a side surface of the first insulator and over the second insulator, and a gate over the third insulator. The semiconductor includes a first region overlapping with the source, a second region overlapping with the drain, and a third region overlapping with the gate. The length between a top surface of the third region of the semiconductor and a bottom surface of the gate is longer than the length between the first region and the third region.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Takashi Hamada, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Ryunosuke Honda, Shunpei Yamazaki
  • Patent number: 10693012
    Abstract: A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 10692775
    Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 23, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
  • Patent number: 10685887
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion including a first channel material, a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion including second channel material, and a sacrificial portion separating the first stack portion from the second stack portion, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other; exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Subhadeep Kal
  • Patent number: 10679980
    Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
  • Patent number: 10680107
    Abstract: Sacrificial gate structures are simultaneously formed in isolation regions that are wider than the sacrificial gate structures formed in the active region. The wider sacrificial gate structures are formed by taking advantage of a smaller lateral etch of p-type silicon than undoped or n-type doped silicon during reactive ion etching. Amorphous or polycrystalline silicon is used as a sacrificial pattern transfer patterning layer in the gate patterning process. The p-type amorphous or polycrystalline silicon increases the sacrificial gate structure length in the isolation region and thus reduces spacing between the sacrificial gate structures in the isolation region. During inner spacer formation, the inner spacers pinch-off all sacrificial gate structures in the isolation region preventing the shallow trench isolation structure to be undercut and thus preventing the collapsing of the sacrificial gate structures in the isolation region.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10665674
    Abstract: A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10658285
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Patent number: 10658464
    Abstract: A monolithically integrated MOS transistor, comprising a doped well region of a first conductivity type, an active MOS transistor region formed in the well region, comprising doped source and drain regions of a second conductivity type and at least one MOS channel region extending between the source and drain regions under a respective gate stack, and a dielectric isolation layer of the STI or LOCOS type and laterally surrounding same, wherein well portions of the well region adjoin the MOS channel region in the two opposite longitudinal directions oriented perpendicular to a notional connecting line extending from the source through the MOS channel region to the drain region, and which extend as far as a surface of the active MOS transistor region, so that the respective well portion adjoining the MOS channel region is arranged between the MOS channel region and the dielectric isolation layer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 19, 2020
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
    Inventor: Roland Sorge
  • Patent number: 10658388
    Abstract: A method includes forming a first circuit element in and above a first semiconductor layer, the first semiconductor layer being formed on a first buried insulating layer, forming drain and source regions of the first circuit element at least partially in the first semiconductor layer, and forming a layer stack above the first circuit element, the layer stack including a conductive layer, a second buried insulating layer formed above the conductive layer, and a second semiconductor layer formed above the second buried insulating layer, wherein the conductive layer is electrically isolated from the drain and source regions.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Pawlak
  • Patent number: 10643992
    Abstract: A semiconductor device is provided, the semiconductor device including: a semiconductor substrate having a first-conductivity-type drift region; one or more transistor portions provided in the semiconductor substrate; and one or more diode portions provided in the semiconductor substrate, wherein both the transistor portions and the diode portions have trench portions that lie from a top surface of the semiconductor substrate to the drift region and include conductive portions, and in a top view of the semiconductor substrate, a main direction of the trench portions in the transistor portions is different from a main direction of the trench portions in the diode portions.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 5, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10636706
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 28, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
  • Patent number: 10636709
    Abstract: A method is presented for forming dielectric isolated fins. The method includes forming a plurality of fin structures over a semiconductor substrate, forming spacers adjacent each of the plurality of fins, recessing the semiconductor substrate to form bottom fin profiles, and forming shallow trench isolation (STI) regions between the plurality of fins and the bottom fin profiles. The method further includes etching the STI regions, a select number of the plurality of fins, and a portion of a select number of the bottom fin profiles to create cavities between a mechanical anchor defined between a pair of fins of the plurality of fins, the etching resulting in undercutting of remaining fins.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Jay W. Strane
  • Patent number: 10629654
    Abstract: A thin film transistor array formed substrate including a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer formed in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 21, 2020
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Hina Chujo, Mamoru Ishizaki
  • Patent number: 10629481
    Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
  • Patent number: 10622448
    Abstract: Techniques are disclosed for forming transistors including retracted raised source/drain (S/D) to reduce parasitic capacitance. In some cases, the techniques include forming ledges for S/D epitaxial regrowth on a high-quality crystal nucleation surface. The techniques may also include forming the raised sections of the S/D regions (e.g., the portions adjacent to spacer material between the S/D regions and the gate material) in a manner such that the S/D raised sections are retracted from the gate material. This can be achieved by forming a notch at the interface between a polarization charge inducing layer and an oxide layer using a wet etch process, such that a relatively high-quality surface of the polarization charge inducing layer material is exposed for S/D regrowth. Therefore, the benefits derived from growing the S/D material from a high-quality nucleation surface can be retained while reducing the parasitic overlap capacitance penalty that would otherwise be present.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 14, 2020
    Assignee: Intel Corproation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung
  • Patent number: 10608036
    Abstract: Various embodiments are directed to a light pipe. The light pipe may include a channel within a substrate of an image sensor. The channel may be formed by a plurality of layers. The plurality of layers may include a first layer and a second layer. The second layer may be spaced apart from the first layer along an axis of the channel.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jian Ma, Biay-Cheng Hseih, Sergiu Radu Goma
  • Patent number: 10600799
    Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: March 24, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shibun Tsuda, Tomohiro Yamashita
  • Patent number: 10593701
    Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 17, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCE INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae-Woo Seo, Youngsoo Shin