Insulated Gate Field Effect Transistor In Integrated Circuit Patents (Class 257/368)
  • Patent number: 11522061
    Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Cheng Lin, Horng-Huei Tseng
  • Patent number: 11515402
    Abstract: The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Robert B. Turkot, Marko Radosavljevic, Han Wui Then, Willy Rachmady, Sansaptak Dasgupta, Jack T. Kavalieros
  • Patent number: 11508736
    Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11495548
    Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 8, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Jun Lu, Long-Ching Wang, Madhur Bobde, Bo Chen, Shuhua Zhou
  • Patent number: 11489058
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active area including a channel region sandwiched between two source/drain regions; an insulation region surrounding the active area from a top view; and a dielectric layer disposed over and in contact with an interface between the insulation region and the source/drain regions. A method of manufacturing the same is also disclosed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsin-Li Cheng, Yu-Chi Chang
  • Patent number: 11482611
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11476328
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 18, 2022
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Patent number: 11476343
    Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
  • Patent number: 11476357
    Abstract: The present invention relates to a Semiconductor device including a first electrode, a second electrode and at least one semiconductor material or layer between the first and second electrode. The semiconductor device further includes at least one field plate structure for increasing a breakdown voltage of the semiconductor device. The at least one field plate structure comprises at least two recesses in the at least one semiconductor material or layer, the at least two recesses defining a semiconductor region therebetween, and a third electrode contacting or provided on the semiconductor region.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 18, 2022
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Elison de Nazareth Matioli, Jun Ma
  • Patent number: 11461620
    Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Borna J. Obradovic, Titash Rakshit, Rwik Sengupta, Joon Goo Hong, Ryan M. Hatcher, Jorge A. Kittl, Mark S. Rodder
  • Patent number: 11437315
    Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-hyung Kim, Jung-ho Do, Dae-young Moon, Sang-yeop Baeck, Jae-hyun Lim, Jae-seung Choi, Sang-shin Han
  • Patent number: 11437474
    Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
  • Patent number: 11424238
    Abstract: A semiconductor device is provided with circuit patterns and dummy patterns. The circuit patterns facilitate circuit operations and the dummy patterns do not facilitate circuit operations. The dummy patterns are formed as patterns at which crystal defects are more likely to be caused by stress than the circuit patterns.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 23, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Atsushi Yabata
  • Patent number: 11424263
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed within a substrate and a plurality of memory devices disposed within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure. A logic wall is arranged on the protrusion and surrounds the plurality of memory devices.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Cheng Wu, Chien-Hung Chang
  • Patent number: 11417601
    Abstract: A device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source/drain region and a source/drain contact above the source/drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. A height of the buried conductive line is greater than a height of the source/drain contact.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 16, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xin-Yong Wang, Liu Han, Li-Chun Tien, Chih-Liang Chen
  • Patent number: 11404412
    Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 2, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Munhyeon Kim, Youngchai Jung, Mingyu Kim, Seon-Bae Kim, Yeonho Park
  • Patent number: 11404443
    Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 2, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taejoong Song, Ha-Young Kim, Jung-Ho Do, Sanghoon Baek, Jinyoung Lim, Kwangok Jeong
  • Patent number: 11398425
    Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sidharth Rastogi, Subhash Kuchanuri, Jae Seok Yang, Kwan Young Chun
  • Patent number: 11393722
    Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey, Anh Phan
  • Patent number: 11387140
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate and a gate electrode overlying the substrate. Further, the integrated chip includes a contact layer overlies the substrate and is laterally spaced apart from the gate electrode by a spacer structure. The spacer structure may surround outermost sidewalls of the gate electrode. A hard mask structure may be arranged over the gate electrode and between portions of the spacer structure. A contact via extends through the hard mask structure and contacts the gate electrode. The integrated chip may further include a liner layer that is arranged directly between the hard mask structure and the spacer structure, wherein the liner layer is spaced apart from the gate electrode.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
  • Patent number: 11387166
    Abstract: Devices are formed on a substrate. A first-tier alternating stack of first insulating layers and first spacer material layers having first stepped surfaces and a first retro-stepped dielectric material portion are formed over the substrate. A sacrificial contact via structure is formed through the first retro-stepped dielectric material portion. A second-tier alternating stack of second insulating layers and second spacer material layers is formed with second stepped surfaces. A second retro-stepped dielectric material portion including a doped silicate glass liner and a silicate glass material portion is formed over the second stepped surfaces. Memory stack structures are formed through the second-tier alternating stack and the first-tier alternating stack. A contact via cavity is formed down to the sacrificial contact via structure. The doped silicate glass liner is recessed and the sacrificial contact via structure is removed, to form a contact via structure in the contact via cavity.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: July 12, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Keigo Kitazawa
  • Patent number: 11380388
    Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 11374089
    Abstract: A method of forming a semiconductor device includes forming a first semiconductor strip protruding above a first region of a substrate and a second semiconductor strip protruding above a second region of the substrate, forming an isolation region between the first semiconductor strip and the second semiconductor strip, forming a gate stack over and along sidewalls of the first semiconductor strip and the second semiconductor strip, etching a trench extending into the gate stack and isolation regions, the trench exposing the first region of the substrate and the second region of the substrate, forming a dielectric layer on sidewalls and a bottom surface of the trench and filling a conductive material over the dielectric layer and in the trench to form a contact, where the contact extends below a bottommost surface of the isolation region.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yuan Wang, Shu-Fang Chen
  • Patent number: 11367661
    Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 21, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Yang Beom Kang, Kang Sup Shin
  • Patent number: 11355569
    Abstract: An active device substrate includes a substrate, a silicon layer, a first insulating layer, a first gate, a first dielectric layer, a first transfer electrode, a second transfer electrode, and a second dielectric layer. Two openings penetrate through the first dielectric layer and overlap the silicon layer. The first transfer electrode and the second transfer electrode are respectively located in the two openings. The second dielectric layer is located on the first transfer electrode and the second transfer electrode. Two first through-holes penetrate through the second dielectric layer. The first transfer electrode and the second transfer electrode are etch stop layers of the two first through-holes.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 7, 2022
    Assignee: Au Optronics Corporation
    Inventors: Chen-Shuo Huang, Hung-Wei Li
  • Patent number: 11335600
    Abstract: A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Jack T. Kavalieros, Anand S. Murthy, Glenn A. Glass, Karthik Jambunathan
  • Patent number: 11335683
    Abstract: A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 17, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, ChihWei Kuo, Junjing Bao
  • Patent number: 11335638
    Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Po-Jen Wang
  • Patent number: 11320738
    Abstract: In a pattern formation method, a bottom layer is formed over an underlying layer. A middle layer is formed over the bottom layer. A resist pattern is formed over the middle layer. The middle layer is patterned by using the resist pattern as an etching mask. The bottom layer is patterned by using the patterned middle layer. The underlying layer is patterned. The middle layer contains silicon in an amount of 50 wt % or more and an organic material. In one or more of the foregoing and following embodiments, an annealing operation is further performed after the middle layer is formed.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Ching-Yu Chang, Shang-Wern Chang, Yen-Hao Chen
  • Patent number: 11309418
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mu Li, Liang-Yi Chen, Wen-Chu Hsiao
  • Patent number: 11309218
    Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
  • Patent number: 11302779
    Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Hee Choi, Seokhoon Kim, Choeun Lee, Edward Namkyu Cho, Seung Hun Lee
  • Patent number: 11296189
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 5, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Patent number: 11296201
    Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Wen Hsieh, Yi-Chun Lo, Wen-Jia Hsieh
  • Patent number: 11296089
    Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmi Yoon, Donghyun Im, Jooyub Kim, Juhyung We, Namhoon Lee, Chunhyung Chung
  • Patent number: 11289494
    Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Patent number: 11289393
    Abstract: Methods, devices, and systems are provided for the molding and encapsulation of flexible electronic devices. The encapsulation includes providing a mold shell made from an encapsulation material, positioning a flexible electronic device in the mold shell, and dispensing an encapsulant, in a liquid form, around the flexible electronic device. The mold shell, the dispensed encapsulant, and the electronic device forms an integral encapsulation package when the encapsulant is cured. The mold shell and the encapsulant may be made from a same material and, once cured, become an integral part of the encapsulated flexible electronic device.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: March 29, 2022
    Assignee: Flex Ltd.
    Inventors: Weifeng Liu, Jesus A. Tan, William L. Uy, Dongkai Shangguan
  • Patent number: 11282852
    Abstract: A vertical memory device includes a gate line structure including a cell region in which a vertical channel structure is formed, and a first connection region and a second connection region which are respectively arranged at first and second ends of the cell region in a first direction. Each of the first connection region and the second connection region includes a first protrusion of the first gate line and a second protrusion of the second gate line which are parallel to a top surface of the substrate and arranged as steps in a second direction perpendicular to the first direction. The first protrusion of the second connection region is arranged diagonally from the first protrusion of the first connection region with respect to a center line of the cell region which is parallel to the first direction.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Bum Kim, Sung-Hoon Kim
  • Patent number: 11276680
    Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Pedone, Hans-Joachim Schulze, Rolf Gerlach, Christian Kasztelan, Anton Mauder, Hubert Rothleitner, Wolfgang Scholz, Philipp Seng, Peter Tuerkes
  • Patent number: 11276696
    Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Hsieh, Yu-Min Liao, Jhon-Jhy Liaw
  • Patent number: 11276753
    Abstract: A transistor and electronic apparatus are disclosed. In one example, a transistor includes a semiconductor substrate containing an electrically-conductive impurity. A device separation layer defines a device region. A buried insulation layer is provided in the device region, and a gate electrode crosses the device region. A drain region and a source region are opposed to each other with the gate electrode in between in the device region. A concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in an end region including at least an end portion of the gate electrode on drain region side is different from a concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in a middle region including a middle portion of the gate electrode.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 15, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Katsuhiko Fukasaku
  • Patent number: 11276578
    Abstract: A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11275050
    Abstract: Semiconductor-based sensor devices and methods for detection of biological agents are described herein.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 15, 2022
    Assignee: FemtoDx, Inc.
    Inventor: Pritiraj Mohanty
  • Patent number: 11271089
    Abstract: Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chai-Wei Chang, Che-Cheng Chang, Po-Chi Wu, Yi-Cheng Chao
  • Patent number: 11271095
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • Patent number: 11264503
    Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 11251314
    Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
  • Patent number: 11251086
    Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Chih-Sheng Chang, Sey-Ping Sun
  • Patent number: 11251091
    Abstract: A semiconductor device includes a semiconductor fin, a gate cut region, a first gate structure and a second gate structure. The semiconductor fin extends from a substrate. The gate cut region extends in parallel with a longitudinal axis of the semiconductor fin and not overlaps the semiconductor fin. The first gate structure and the second gate structure extend across the semiconductor fin. The first gate structure is laterally between the gate cut region and the second gate structure along a direction parallel with the longitudinal axis of the semiconductor fin. The first gate structure has a greater width variation than the second gate structure.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon-Jhy Liaw
  • Patent number: 11251312
    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mongsong Liang, Sung-Dae Suk, Geumjong Bae