ULTRA HIGH-SPEED SI/SIGE MODULATION-DOPED FIELD EFFECT TRANSISTORS ON ULTRA THIN SOI/SGOI SUBSTRATE
A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.
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1. Field of the Invention
The present invention relates generally to silicon and silicon germanium based semiconductor transistor devices, and more specifically, to a device design including a grown epitaxial field effect transistor structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. Preferably, the epitaxial field effect transistor structure includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve fmax in excess of 200 GHz.
2. Description of the Prior Art
The attractiveness of substantial electron mobility enhancement (i.e. 3-5 times over bulk silicon) in modulation-doped tensile-strained Si quantum wells has inspired a long history of device development on Si/SiGe n-channel modulation doped filed-effect transistors (MODFETs). Subsequently, it has been demonstrated that SiGe MODFETs consume lower power and have lower noise characteristics compared to SiGe Heterojunction Bipolar Transistors (HBTs). Similarly, when compared to RF bulk Si CMOS device, SiGe MODFETs still have lower noise characteristics, and higher maximum oscillation frequency (fmax). Consequently, Si/SiGe MODFETs are becoming more and more attractive devices for high speed, low noise, and low power communication applications, where low cost and compatibility with CMOS logic technology are required and often essential. Recently, n-channel MODFETs with long channel lengths ranging from 0.2 μm to 0.5 μm have demonstrated encouraging device performances.
Typically, a Si/SiGe MODFET device have an undoped, tensile strained silicon (NFET) or a compressively strained SiGe (PFET) quantum well channels whereby the induced strain is used to increase the carrier mobility in the channel, in addition to providing carrier confinement. The synergistic addition of modulation doping further improves the carrier mobility in the channel by reducing the ionized impurity scattering from the dopants and further reducing the surface roughness scattering in a buried channel. Record high room temperature mobilities of 2800 cm2/Vs have been achieved for electron mobilities in a tensile strained silicon channel grown on a relaxed Si0.7Ge0.3 buffer. Conversely, very high hole mobility of 1750 cm2V-s in a pure Ge channel grown on a Si0.35Ge0.65 buffer has been achieved [R. Hammond, et al, DRC, 1999]. The highest fT that has been achieved for a strained silicon nMODFET is 90 GHz [M. Zeuner, 2002], and the highest fmax is 190 GHz [Koester, et al to be published]. So far, neither fT nor fmax has reached 200 GHz with Si/SiGe MODFETs.
As described in a simulation study conducted by the inventors, in order to achieve higher speed, the MODFET has to be scaled properly, both in the vertical dimensions and the horizontal (or lateral) dimensions. However, it turns out that the scaling of MODFETs is even more challenging than for CMOS scaling due to the following: 1) the horizontal scaling brings the source and drain closer, and, like the case in the CMOS, short-channel effects and bulk punchthrough become the major hurdles preventing the lateral scaling; and, 2) the vertical scaling of the layer structure turns out to be crucial. The lateral scaling alone cannot keep the scaling of the performance. However, the vertical scaling of the MODFET structures to reduce the depth of the quantum well (dQW) is quite challenging, particularly due to the scaling and abruptness of the n+ supply layer, which is typically doped with Phosphorus as explained in the Annual Review of Materials Science, vol. 30, 2000, pp. 348-355.
It would be highly desirable to provide a scaling technique for MODFET device structures that overcomes the lateral and vertical scaling challenges in the manufacture of MODFET device structures.
It has been further been demonstrated in commonly-owned, co-pending U.S. patent application Ser. No. 10/389,145 entitled “Dual Strain State SiGe Layers for Microelectronics” by J. Chu, et al, filed Mar. 15, 2003, the contents and disclosure of which is incorporated by reference as if fully set forth herein, that MODFETs on a thick Silicon-Germanium-on-Insulator (SGOI) substrate will behave like MODFET on a bulk substrate. Co-pending U.S. patent application Ser. No. 10/389,145 particularly describes a generic MODFET layer structure on a SGOI substrate without specifying the critical layer structure for high performance.
It would be further highly desirable to provide a scaled MODFET device structure that is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, wherein the MODFET device structure exhibits ultra-high speed device performance (e.g., fT, fmax>300 GHz) with better noise figures, acceptable voltage gain and good turn-off characteristics.
SUMMARY OF THE INVENTIONThe invention is directed to a high-electron-mobility n-channel MODFET device that is properly scaled and constructed on a thin SGOI/SOI substrate that exhibits greatly improved RF performance.
The present invention is directed to a MODFET device and method of manufacture that addresses the prior art limitations and achieves vertical scaling of the nMODFET layer structure and the source/drain junction and lateral scaling of the device structure to unprecedented degrees, resulting in a device exhibiting ultra-high speed performance (i.e. fT, fmax>300 GHz) with acceptable voltage gain and good turn-off characteristics.
In the method of manufacturing the MODFET device of the invention, the MODFET device is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, such that the body is fully depleted. Due to the suppressed short channel effects, the output conductance (gd) may be thus be reduced. Therefore, the DC voltage gain (gm/gd), the linearity and fmax is significantly improved. In addition, the provision of ultra-thin SiGe buffer layers also reduces the self-heating due to the low thermal conductivity of SiGe, which reduces the drive current. Compared to a bulk MODFET, a fully-depleted SGOI MODFET exhibits better noise figures and lower soft error rate. Preferably, the epitaxial field effect transistor structure of the invention includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve fmax of >300 GHz.
As studies have shown that the Phosphorus incorporation rate can be controlled by the growth rate (See aforementioned Annual Review of Materials Science, vol. 30, 2000, pp. 348-355), it is thus a further object of the present invention to provide a novel MODFET device structure method of achieving thin SiGe epitaxial layer with an abrupt P doping. In this objective, a novel low temperature growth technique is implemented for achieving abrupt phosphorous doping profiles in order to accommodate and to match the proper vertical scaling or design of the MODFET layer structure required for ultra-high speed performances.
In order to prevent the Phosphorus diffusion during the fabrication process, a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer in the manner as described in commonly-owned, co-pending U.S. patent application Ser. No. 09/838,892 (Docket YOR920010308US1) entitled “Epitaxial and Polycrystalline Growth of Si1−x−yGexCy and S1−yCy Alloy Layers on Si by UHV-CVD”, the contents and disclosure of which is incorporated by reference as if fully set forth herein.
The invention further is directed to a high-hole-mobility p-channel MODFET that is properly scaled and constructed on a thin SGOI/SOI substrate will also have very high RF performance.
BRIEF DESCRIPTION OF THE DRAWINGSFurther features, aspects and advantages of the apparatus and methods of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
FIGS. 1(a)-1(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structure on thin SGOI substrate (G1-G4) properly scaled in accordance with the invention;
FIGS. 1(a)-1(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structures on thin SiGe-on-Insulator (SGOI) substrate (generation G1-G4 devices) properly scaled in accordance with the invention.
The composition of the channel region 25 of device 10 in
To form the transistor device of
In an alternate embodiment the seed layer 31 of
In an alternate embodiment of the structure 50 of
To form the pMODFET transistor device of
Completed devices comprising embodiments depicted in FIGS. 1(a)-1(e) having the different layer structures and design were grown by UHVCVD under growth temperature conditions ranging between 400-600° C., and preferably in a range of 500-550° C. and in a pressure ranging from 1 mTorr-20 mTorr.
As mentioned hereinabove, experimentally it has been found that Phosphorus (P) doping can be controlled by the Ge content and its associated growth rate in a UHV CVD system.
As shown in the steady-state P concentration vs. growth rate graph of
The growth rate calibration 170 for a SiGe (Ge content of 30%) is shown in
Using a reduced flow combination of SiH4 to GeH4 of (15 sccm/17 sccm), a G1 doping profile has been obtained just like secondary ion mass spectroscopy (SIMS) profiles 201, 202 as shown in
Using a lower flow combination SiH4 to GeH4 of (10/17), a G2 doping profile has been achieved as shown in the SIMS profiles P doping and Ge concentration profiles shown in
Using an even lower flow combination SiH4 to GeH4 of (8/10), a G3 doping profile has been achieved as shown in the SIMS profiles P doping and Ge concentration profiles shown in
While the invention has been particularly shown and described with respect to illustrative and preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention that should be limited only by the scope of the appended claims.
Claims
1. A high-electron-mobility layer semiconductor structure comprising:
- an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm, and having a p-type doping concentration ranging between 1e14 cm−3-5e17 cm−3;
- an epitaxial Si0.95Ge0.05 seed layer grown on top of said SiGe layer and ranging in thickness between 0 nm-5 nm;
- a regrown Si1−xGex buffer layer grown on top of said seed layer and ranging in thickness between 20 nm-30 nm and having Ge content x ranging between 10%-40%;
- an epitaxial tensile strained Si layer grown on top of said buffer layer and ranging in thickness between 5 nm-7 nm;
- an epitaxial Si1−yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm-5 nm and having Ge content y ranging between 30-40%;
- an epitaxial Si1−zGez supply layer grown on top of said spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm−3-2e19 cm−3 and having Ge content ranging between 35-50%; and,
- an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm−3-5e19 cm−3.
2. The high-electron-mobility layer semiconductor structure as claimed in claim 1, wherein said Si1−yGey spacer layer includes a Ge content y=x+a, where “a” ranges between 0-20%.
3. The high-electron-mobility layer semiconductor structure as claimed in claim 1, wherein said Si1−zGez supply layer includes a Ge content z=x+b, where “b” ranges between 0-30%.
4. The high-electron-mobility layer semiconductor structure as claimed in claim 1, wherein said Si1−zGez supply layer comprises a Si1−m−nGemCn layer, where m=x+c, and “c” ranges between 0-20%, and “n” ranges between 0.1-2%.
5. The high-electron-mobility layer semiconductor structure as claimed in claim 1, further comprising:
- a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
- a gate conductor formed on top of said gate dielectric layer;
- a drain region having a n-type doping concentration greater than 5e19 cm−3; and,
- a source region having a n-type doping concentration greater than 5e19 cm−3, wherein said structure forms a high-electron-mobility field effect transistor.
6. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said Si1−zGez supply layer ranges from about 5 nm-8 nm in thickness and has a sheet doping density of about 3e12 cm−2.
7. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said Si1−zGez supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm−2.
8. The high-electron-mobility field effect transistor as claimed in claim 6, wherein said Si1−zGez supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
9. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
10. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
11. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said gate conductor is one of: a T-gate geometry, rectangular geometry or a multi-finger geometry.
12. The high-electron-mobility field effect transistor as claimed in claim 5, wherein a gate length ranges between 30 nm-100 nm.
13. The high-electron-mobility field effect transistor as claimed in claim 5, wherein a distance between said gate conductor and either said drain or source region ranges from about 20 nm-100 nm.
14. The high-electron-mobility field effect transistor as claimed in claim 5, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
15. A high-electron-mobility field effect transistor comprising: an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm, and having a p-type doping concentration ranging between 1e14 cm−3-5e17 cm−3;
- a regrown Si1−xGex buffer layer grown on top of said SiGe layer and ranging in thickness between 20 nm-30 nm, and having a Ge content x of 30-40%;
- an epitaxial tensile strained Si layer grown on top of said buffer layer and ranging in thickness between 5 nm-7 nm;
- an epitaxial Si1−yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm-5 nm and having Ge content ranging between 30-40%;
- an epitaxial Si1−zGez supply layer grown on top of said spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm−3-2e19 cm−3 and having Ge content ranging between 35-50%;
- an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm−3-5e19 cm−3;
- a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
- a gate conductor formed on top of said gate dielectric layer;
- a drain region having a n-type doping concentration greater than 5e19 cm−3; and,
- a source region having a n-type doping concentration greater than 5e19 cm−3.
16. A high-electron-mobility layer semiconductor structure comprising:
- an SGOI substrate comprising a Si1−xGex layer on insulator ranging in thickness between 10 nm-50 nm,
- an epitaxial Si0.95Ge0.05 seed layer grown on top of said SiGe layer and ranging in thickness between 0 nm-5 nm;
- an epitaxial Si1−zGez supply layer grown on top of said seed layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm−3-5e19 cm−3; and,
- an epitaxial Si1−yGey spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-5 nm;
- an epitaxial tensile strained Si layer grown on top of said spacer layer and ranging in thickness between 3 nm-10 nm;
- an epitaxial Si1−yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 1 nm-2 nm; and,
- an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between 0 nm-2 nm.
17. The high-electron-mobility layer semiconductor structure as claimed in claim 16, wherein said SGOI substrate includes a Si1−xGex layer with a Ge content x ranging between 30-50%.
18. The high-electron-mobility layer structure as claimed in claim 16, wherein said Si1−zGez supply layer has a Ge content z=x+a, where “a” ranges between about 0-30% and x ranges between 30-50%.
19. The high-electron-mobility layer semiconductor structure as claimed in claim 16, wherein said Si1−zGez supply layer comprises a Si1−m−nGemCn layer, where m=x+b, and “b” ranges between 0-30%, and “n” ranges between 0.1-2%.
20. The high-electron-mobility layer semiconductor structure as claimed in claim 16, wherein said Si1−yGey spacer layer includes a Ge content y=x+c, where “c” ranges between 0-20%.
21. The high-electron-mobility layer semiconductor structure as claimed in claim 16, farther comprising:
- a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
- a gate conductor formed on top of said gate dielectric layer;
- a drain region having a n-type doping concentration greater than 5e19 cm−3; and,
- a source region having a n-type doping concentration greater than 5e19 cm−3, wherein said structure forms a high-electron-mobility field effect transistor.
22. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said Si1−zGez supply layer is about 5 nm-8 nm in thickness and has a sheet doping density of about 3e12 cm−2.
23. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said Si1−zGez supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm−2.
24. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said Si1−zGez supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
25. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
26. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
27. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said gate conductor is one of: a T-gate geometry, rectangular geometry or a multi-finger geometry.
28. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein a gate length ranges between 30 nm-100 nm.
29. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein a distance between said gate conductor and either said drain or source region ranges from about 20 nm-100 nm.
30. The high-electron-mobility layer semiconductor structure as claimed in claim 21, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
31. A high-electron-mobility field effect transistor comprising:
- an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm; an epitaxial Si1−zGez supply layer grown on top of said SiGe layer ranging in thickness between 2.5 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm−3-2e19 cm−3 and having Ge content ranging between 35-50%;
- an epitaxial Si1−yGey spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-5 nm and having Ge content ranging between 30-40%;
- an epitaxial tensile strained Si channel layer grown on top of said spacer layer ranging in thickness between 5 nm-7 nm and having a doping concentration less than 1e16 cm−3;
- an epitaxial Si1−yGey spacer layer grown on top of said Si channel layer and ranging in thickness between 1 nm-2 nm and having Ge content ranging between 30-40%;
- an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between 0 nm-2 nm;
- a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
- a gate conductor formed on top of said gate dielectric layer;
- a drain region having a n-type doping concentration greater than 5e19 cm−3; and,
- a source region having a n-type doping concentration greater than 5e19 cm−3.
32. A high-electron-mobility layer semiconductor structure comprising:
- an SGOI substrate comprising a Si1−zGez supply layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm−3-5e19 cm−3; and,
- an epitaxial Si1−yGey spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-5 nm;
- an epitaxial tensile strained Si layer grown on top of said spacer layer and ranging in thickness between 3 nm-10 nm;
- an epitaxial Si1−yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 1 nm-2 nm; and,
- an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between 0 nm-2 nm.
33. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said SGOI substrate includes a Ge content “x” ranging between 30-50%.
34. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said doped transferred Si1−zGez supply layer has a Ge content z=x+a, where “a” ranges between about 0-30% and may be formed by a wafer bonding and smart-cut process.
35. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said doped transferred Si1−zGez supply layer comprises a Si1−m−nGemCn layer, where m=x+b, and “b” ranges between 0-30%, and “n” ranges between 0.1-2%.
36. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said Si1−yGey spacer layer includes a Ge content y=x+c, where “c” ranges between 0-20%.
37. The high-electron-mobility layer semiconductor structure as claimed in claim 32, further comprising:
- a gate dielectric layer formed on top of said strained Si cap layer and less than 1 nm in thickness;
- a gate conductor formed on top of said gate dielectric layer;
- a drain region having a n-type doping concentration greater than 5e19 cm−3; and,
- a source region having a n-type doping concentration greater than 5e19 cm−3.
38. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said doped transferred Si1−zGez supply layer is about 5 nm-8 nm in thickness and has a sheet doping density of about 3e12 cm−2.
39. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said doped transferred Si1−zGez supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm−2.
40. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said doped transferred Si1−zGez supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
41. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
42. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
43. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said gate conductor is one of: a T-gate geometry, rectangular geometry, or a multi-finger geometry.
44. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein a gate length ranges between 30 nm-100 nm.
45. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein a distance between said gate conductor and either said drain or source region ranges from about b 20 nm-100 nm.
46. The high-electron-mobility layer semiconductor structure as claimed in claim 37, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
47. A high-electron-mobility layer semiconductor structure comprising:
- an SGOI substrate comprising a SiGe layer on insulator ranging in thickness between 10 nm-50 nm, and having a n-type doping concentration ranging between 1e17 cm−3-5e19 cm−3;
- a Si1−xGex regrown buffer layer grown on top of said SiGe layer and ranging in thickness between 10 nm-50 nm and serving as a bottom spacer layer;
- an epitaxial tensile strained Si layer grown on top of said regrown buffer layer and ranging in thickness between 3 nm-10 nm;
- an epitaxial Si1−yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm-5 nm;
- an epitaxial Si1−zGez supply layer grown on top of said spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm−3-5e19 cm−3; and,
- an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm−3-5e19 cm−3.
48. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said SGOI substrate includes a Ge content ranging between 30-50%.
49. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Si1−xGex regrown buffer layer includes a Ge content x ranging between 10-35%.
50. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Si1−yGey spacer layer includes a Ge content y=x+a, where “a” ranges between 0-20%.
51. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Si1−zGez supply layer includes a Ge content z=x+b, where “b” ranges between 0-30%.
52. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Si1−zGez supply layer comprises a Si1−m−nGemCn layer, where m=x+c, and “c” ranges between 0-20%, and “n” ranges between 0.1-2%.
53. The high-electron-mobility layer semiconductor structure as claimed in claim 47, further comprising:
- a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
- a gate conductor formed on top of said gate dielectric layer;
- a drain region having a n-type doping concentration greater than 5e19 cm−3; and,
- a source region having a n-type doping concentration greater than 5e19 cm−3.
54. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said Si1−zGez supply layer is about 5 nm-8 nm in thickness and has a sheet doping density of about 3e12 cm−2.
55. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said Si1−zGez supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm−2.
56. The high-electron-mobility layer semiconductor structure as claimed in claim 54, wherein said Si1−zGez supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
57. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
58. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
59. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said gate conductor is one of: a T-gate, rectangular, or multi-finger geometry.
60. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein a gate length ranges between 30 nm-100 nm.
61. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein a distance between said gate conductor and either said source or drain region ranges from about 20 nm-100 nm.
62. The high-electron-mobility layer semiconductor structure as claimed in claim 53, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
63. A high-hole-mobility layer semiconductor structure comprising:
- an SGOI substrate comprising an epitaxial Si1−jGej supply layer ranging in thickness between 5 nm-25 nm, and having a p-type doping concentration ranging between 1e18-5e19 cm−3;
- an epitaxial Si1−kGek spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-7 nm;
- an epitaxial compressively strained Si1−mGem channel layer grown on top of said spacer layer and ranging in thickness between 5 nm-20 nm; and,
- an epitaxial strained Si1−nGen cap layer grown on top of said strained Si1−mGem channel layer and ranging in thickness between 2 nm-10 nm.
64. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said Si1−jGej supply layer includes a Ge content j ranging between 30-70%.
65. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said Si1−kGek spacer layer includes a Ge content k ranging between 30-70%.
66. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said Si1−mGem channel layer includes a Ge content m ranging between 60-100%.
67. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said strained Si1−nGen cap layer includes a Ge content n ranging between 0%-30%.
68. The high-hole-mobility layer semiconductor structure as claimed in claim 63, further comprising:
- a gate conductor formed on top of said gate dielectric layer;
- a drain region having a p-type doping concentration greater than 5e19 cm−3; and,
- a source region having a p-type doping concentration greater than 5e19 cm−3.
69. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
70. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
71. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein said gate conductor is one of: a T-gate, rectangular, or multi-finger geometry.
72. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein a gate length ranges between 30 nm-100 nm.
73. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein a distance between said gate conductor and either said drain or source region ranges from about 20 nm-100 nm.
74. The high-hole-mobility layer semiconductor structure as claimed in claim 68, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
75. A method of preparing a high-electron-mobility layer structure comprising the steps of:
- a) providing a SGOI substrate having a relaxed Si1−xGex layer on insulator;
- b) forming a Si0.95Ge0.05 seed layer on top of said Si1−xGex layer;
- c) forming a regrown Si1−x Gex buffer layer on top of said Si0.95Ge0.05 seed layer;
- d) forming a strained silicon channel layer on top of said regrown Si1−xGex layer,
- e) forming a Si1−yGey spacer layer on top of said strained silicon layer;
- f) forming a Si1−zGez supply layer on top of said Si1−yGey spacer layer, doping said Si1−zGez supply layer n-type to a concentration level in a range of 1e18-5e19 atoms/cm−3; and,
- g) forming a silicon cap layer on top of said Si1−zGez supply layer.
76. The method according to claim 75, wherein said forming steps b)-g) comprise implementing a UHVCVD process.
77. The method according to claim 75, wherein said forming steps b)-g) comprise implementing one of MBE, RTCVD, LPCVD processes.
78. The method according to claim 75, wherein said layer forming steps b)-g) comprise growing the layers in a temperature range between 450° C.-600° C.
79. The method according to claim 75, wherein said layer forming steps b)-g) comprise growing the layers in a pressure range from 1 mTorr-20 mTorr.
80. The method according to claim 75, wherein said step a) of providing a SGOI substrate having a relaxed Si1−xGex layer on insulator further includes the step of: doping the relaxed Si1−xGex layer on insulator p-type to a concentration level of 1e14 cm−3-5e17 cm−3 using one of: ion implantation or in-situ doping.
81. The method according to claim 75, wherein said step a) of providing a SGOI substrate having a relaxed Si1−xGex layer on insulator further includes the step of: predoping the relaxed Si1−xGex layer to a concentration level of 1e14 cm−3-5e17 cm−3 prior to transferring said layer in forming the SGOI substrate.
82. The method according to claim 75, wherein said step f) of forming a Si1−zGez supply layer further includes the step of: in-situ doping said Si1−zGez supply layer using phosphine gas as a dopant precursor singly or in a mixture thereof including one or more elements selected from the group comprising: H2, He, Ne, Ar, Kr, Xe, N2.
83. The method according to claim 75, including growing said Si1−zGez supply layer at a reduced growth rate for a higher P steady state concentration and transient incorporation by reducing the SiH4 and GeH4 gas flow rate by a factor of greater than 3 while keeping the SiH4:GeH4 gas flow ratio constant.
84. The method according to claim 82, wherein a flow rate for said phosphine gas dopant precursor is a linear ramp or a graded profile such that said in-situ doping is performed without disrupting the epitaxial growth process.
85. The method according to claim 82, wherein the phosphine doped Si1−zGez layer is grown in a temperature range between 425° C.-550° C.
86. The method according to claim 82, further including doping the Si1−zGez supply layer with carbon at 1-2% level in a temperature range of 425° C.-550° C.
87. The method according to claim 75, wherein said step f) of forming a n-type Si1−zGez supply layer further includes the step of using a precursor of one of: AsH3 or SbH3.
88. A method of preparing a high-electron-mobility layer structure comprising the steps of:
- a) providing a SGOI substrate having a relaxed Si1−xGex layer on insulator;
- b) forming a regrown Si1−xGex buffer layer on top of said relaxed Si1−xGex layer;
- c) forming a strained silicon channel layer on top of said regrown Si1−xGex layer,
- d) forming a Si1−yGey spacer layer on top of said strained silicon layer;
- e) forming a Si1−zGez supply layer on top of said Si1−yGey spacer layer, doping said Si1−zGez supply layer n-type to a concentration level in a range of 1e18-5e19 atoms/cm3; and,
- f) forming a silicon cap layer on top of said Si1−zGez supply layer.
89. A method of preparing a high-electron-mobility layer structure comprising the steps of:
- a) providing a SGOI substrate having a relaxed Si1−xGex layer on insulator;
- b) forming an epitaxial Si0.95Ge0.05 seed layer on top of said SiGe layer;
- c) forming an epitaxial Si1−zGez supply layer on top of said spacer layer and doping said supply layer with n-type dopant concentration ranging between 1e18 cm−3-5e19 cm−3;
- d) forming an epitaxial Si1−yGey spacer layer on top of said supply layer and ranging in thickness between 3 nm-5 nm;
- e) forming an epitaxial tensile strained Si layer on top of said spacer layer;
- f) forming an epitaxial Si1−yGey spacer layer on top of said strained Si layer and ranging in thickness between 1 nm-2 nm; and,
- g) forming an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-2 nm.
90. A method of preparing a high-electron-mobility layer structure comprising steps of:
- a) providing a SGOI substrate having a Si1−xGex supply layer on insulator, and doping the Si1−xGex supply layer n-type to a concentration level ranging between 1e18-5e19 atoms/cm3;
- b) forming an epitaxial Si1−yGey spacer layer over above doped Si1−xGex layer,
- c) forming an epitaxial tensile strained Si channel layer on top of said spacer layer;
- d) forming an epitaxial Si1−yGey spacer layer on top of said strained Si channel layer; and,
- e) forming an epitaxial strained Si cap layer on top of said spacer layer.
91. The method as claimed in claim 90, further including the step of doping the Si1−xGex layer on insulator n-type to a concentration level of 1e18-5e19 atoms/cm3 using ion implantation or in-situ doping.
92. The method as claimed in claim 90, further including the step of predoping the Si1−xGex layer to a concentration level of 1e18-5e19 atoms/cm3 before a layer transfer in forming the SGOI substrate.
93. A method of preparing a high-electron-mobility layer structure comprising the steps of:
- a) providing a SGOI substrate comprising a relaxed SiGe layer on insulator ranging in thickness between 10 nm-50 nm, and doping said relaxed SiGe layer with n-type doping concentration ranging between 1e14 cm−3-5e17 cm−3;
- b) forming a Si1−xGex regrown buffer layer grown on top of said SiGe layer and ranging in thickness between 10 nm-50 nm;
- c) forming an epitaxial tensile strained Si layer on top of said regrown buffer layer and ranging in thickness between 3 nm-10 nm;
- d) forming an epitaxial Si1−yGey spacer layer on top of said strained Si layer and ranging in thickness between 3 nm-5 nm;
- e) forming an epitaxial Si1−zGez supply layer on top of said spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm−3-5e19 cm−3; and,
- f) forming an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm−3-5e19 cm−3.
94. A method of preparing a high-hole-mobility layer structure comprising steps of:
- a) providing a SGOI substrate having a relaxed Si1−jGej layer on insulator;
- b) forming a Si1−kGek spacer layer on top of said doped Si1−jGej layer;
- c) forming a compressively strained Si1−mGem channel layer on top of said Si1−kGek spacer layer; and,
- d) forming a Si1−nGen spacer layer on top of said compressively strained Si1−mGem channel layer.
95. The method as claimed in claim 94, further including the step of doping the Si1−jGej layer p-type to a concentration level ranging between 1e18-5e19 atoms/cm3 using ion implantation or in-situ doping.
96. The method as claimed in claim 94, whereby the relaxed Si1−jGej layer may be predoped p-type to a concentration level of 1e18-5e19 boron atoms/cm3 before a layer transfer in forming the SGOI substrate.
Type: Application
Filed: Aug 29, 2003
Publication Date: Mar 3, 2005
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (ARMONK, NY)
Inventors: Jack Chu (Manhasset Hills, NY), Qiqing Ouyang (Yorktown Heights, NY)
Application Number: 10/652,400