Integrated circuit package
In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate. In another aspect, the invention features an integrated circuit package including a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, a semiconductor die electrically coupled with the conductive via, at least a portion of the semiconductor die being disposed inside the cavity of the substrate, an encapsulant material encapsulating a portion of the semiconductor die such that at least a portion of a surface of the semiconductor die is exposed.
The present invention relates to integrated circuit packaging and manufacturing thereof, and more particularly, to integrated circuit packaging for improved dissipation of thermal energy.
BACKGROUND OF THE INVENTIONA semiconductor device generates a great deal of heat during normal operation. As the speed of semiconductors has increased, so too has the amount of heat generated by them. It is desirable to dissipate this heat from an integrated circuit package in an efficient manner.
A heat sink is one type of device used to help dissipate heat from some integrated circuit packages. Various shapes and sizes of heat sink devices have been incorporated onto, into or around integrated circuit packages for improving heat dissipation from the particular integrated circuit package. For example, U.S. Pat. No. 5,596,231 to Combs, entitled “High Power Dissipation Plastic Encapsulated Package For Integrated Circuit Die,” discloses a selectively coated heat sink attached directly on to the integrated circuit die and to a lead frame for external electrical connections.
SUMMARY OF THE INVENTIONIn one aspect, the invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.
In another aspect, the invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a plurality of cavities, each said cavity through the substrate between the first and second surfaces, and a plurality of conductive vias, each said via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of said substrate, mounting a plurality of semiconductor dies on the strip, at least a portion of each semiconductor die being disposed inside each cavity, encapsulating in a molding material at least a portion of the first surface of said substrate, and removing the strip from the substrate to expose a surface of each semiconductor die.
In a further aspect, the invention features an integrated circuit package including a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, a semiconductor die electrically coupled with the conductive via, at least a portion of the semiconductor die being disposed inside the cavity of the substrate, an encapsulant material encapsulating a portion of the semiconductor die such that at least a portion of a surface of the semiconductor die is exposed.
BRIEF DESCRIPTION OF THE DRAWINGSThe foregoing features and other aspects of the invention are explained in the following description taken in connection with the accompanying drawings, wherein:
Various embodiments of the integrated circuit package and various examples of methods for manufacturing integrated circuit packages according to the present invention will now be described with reference to the drawings.
As shown in
In one embodiment, traces 112 may be embedded photolithographically into the substrate 101, and are electrically conductive to provide a circuit connection between the semiconductor die 103 and the substrate 101. Such traces 112 may also provide an interconnection between input and output terminals of the semiconductor die 103 and external terminals provided on the package. In particular, the substrate 101 of the embodiment shown in
As shown in
One embodiment may include a conductive trace 112 in the form of a ring around the cavity 120 in the substrate 101. Such a ring-shaped conductive trace 112 may be connected to the top surface of the substrate 101 by means of electrically conductive vias 110. Such an arrangement may allow a heat slug 108 to be electrically connected to the semiconductor die 103 by the way of wire bonding 104, thereby resulting in a ground plane surface beneath the semiconductor die 103, which may enhance the electrical characteristics of the package.
In a preferred embodiment shown in
Example methods of manufacturing embodiments of the integrated circuit packages will now be described with reference to the drawings, in particular,
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The heat slug 108 shown in
Although specific embodiments of integrated circuit packages, integrated circuit package assemblies, and methods of manufacturing integrated circuit packages have been shown and described, it is to be understood that there are other embodiments which are equivalent to the described embodiments. Moreover, although a particular order of certain manufacturing steps has been discussed, it is to be understood that aspects of the invention are not limited to the particular order disclosed. The scope of the invention is not to be limited by the specific embodiments and examples depicted and described herein, but only by the claims.
Claims
1-22. (canceled)
23. An integrated circuit package, comprising:
- a substrate comprising: a first surface, a second surface opposite said first surface, a cavity through said substrate between said first and second surfaces, and a conductive via extending through said substrate and electrically connecting said first surface of said substrate with said second surface of said substrate;
- a semiconductor die electrically coupled with said conductive via at said first surface of said substrate, at least a portion of said semiconductor die being disposed inside said cavity of said substrate;
- an encapsulant material encapsulating a portion of said semiconductor die such that at least a portion of a surface of said semiconductor die is exposed; and
- a heat slug thermally and electrically coupled with said semiconductor die, wherein said conductive via is further electrically coupled with said heat slug to provide a ground connection for said semiconductor die at said first surface of said substrate.
24. The integrated circuit package of claim 23, further comprising a conductive member adapted for attachment of said integrated circuit package to an external device.
25. The integrated circuit package of claim 24, said conductive member attached to said first surface of said substrate.
26. The integrated circuit package of claim 23, further comprising at least one wire electrically coupling said semiconductor die with said conductive via.
27. The integrated circuit package of claim 23, at least a portion of said first surface of said substrate being adapted for coupling said integrated circuit package with a second integrated circuit package.
28. The integrated circuit package of claim 23, said substrate further comprising a multi-layer trace embedded therein.
29. An integrated circuit package assembly comprising the integrated circuit package of claim 23 attached to at least one other integrated circuit package.
30. The integrated circuit package assembly of claim 29, wherein one of said integrated circuit packages is stacked on top of at least one of the other of said integrated circuit packages.
31. The integrated circuit package of claim 25, further comprising a second conductive member attached to said second surface of said substrate.
32. The integrated circuit package of claim 23, said package having a thickness dimension of about one millimeter.
33. The integrated circuit package of claim 39, said package having a width dimension of about seven millimeters.
34. The integrated circuit package of claim 23, said substrate being substantially planar and said semiconductor die being aligned in a plane with said substrate.
35. The integrated circuit package of claim 23, said integrated circuit package being a land grid array.
36. The integrated circuit package of claim 23 said integrated circuit package being a ball grid array.
37. The integrated circuit package of claim 23, said encapsulant material comprising an epoxy.
38. The integrated circuit package of claim 23, further comprising a ring-like trace embedded in said substrate.
39. The integrated circuit package of claim 33, said package having a width dimension of about 7 mm to 50 mm inclusively.
40. An integrated circuit package, comprising:
- a substrate comprising: a first surface, a second surface opposite said first surface, a cavity through said substrate between said first and second surfaces, and means for electrically connecting said first surface of said substrate with said second surface of said substrate;
- a semiconductor die, at least a portion of which is disposed inside said cavity of said substrate;
- an encapsulant material encapsulating a portion of said semiconductor die such that at least a portion of a surface of said semiconductor die is exposed; and
- means for thermally coupling said semiconductor die to a printed circuit board, wherein said means for thermally coupling is electrically coupled with said means for electrically connecting said first surface of said substrate with said second surface of said substrate to provide a ground connection for said semiconductor die at said first surface of said substrate.
41. An integrated circuit package assembly comprising the integrated circuit package of claim 40 attached to at least one other integrated circuit package.
42. The integrated circuit package assembly of claim 41, wherein one of said integrated circuit packages is stacked on top of at least one of the other of said integrated circuit packages.
Type: Application
Filed: Aug 6, 2003
Publication Date: Apr 14, 2005
Inventors: Neil McLellan (Hong Kong), Chun Fan (Hong Kong), Edward Combs (Foster, CA), Tsang Cheung (New Territories), Chow Keung (Kowloon), Sadak Labeeb (Tsuen Wan)
Application Number: 10/635,839