Floating gate and fabrication method therefor
A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.
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1. Field of the Invention
The invention is relates to a floating gate, and more particularly to a floating gate with multiple tips and a fabrication method thereof.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use, in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
An advantage of EPROM is electrical programmability, but for erasing, EPROM requires exposure to ultraviolet (UV) light.
In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device.
EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain.
One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, normally taking just 1 to 2 seconds for the complete removal of a whole block of memory. Another advantage of the flash memory is low power consumption. The voltages of a control gate, a source, and a drain are adjusted to program or erase in a split gate flash memory.
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A split gate flash memory is completed after a control gate is formed on the floating gate and the silicon substrate 101 is implanted to form source/drain devices.
In the program step, high voltage is applied between the source and drain. Another high voltage is applied to the control gate and goes to the floating gate because of the electric capacity coupling, and a high electric field is produced on the film gate oxide layer. The electricity is injected into the floating gate through the film gate oxide layer from the drain.
In the erase step, a high voltage is applied between the drain and the control gate. A high electric field is produced on the film gate oxide layer because of the electric capacity coupling. The electricity injects into the drain through the film gate oxide layer from the floating gate, such that the gate oxide layer is damaged by the high voltage.
When the edge of the floating gate is a tip, the electric field is easily concentrated in the tip, and the point is easily discharged. If the point discharge is increased, the erase effect is strong.
In addition, die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices.
SUMMARY OF THE INVENTIONThe present invention is directed to a floating gate with multiple tips and a fabrication method thereof.
Accordingly, the present invention provides a method for forming a floating gate. A semiconductor substrate is provided. A patterned hard mask layer with an opening is formed on the semiconductor substrate. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer is removed. The gate dielectric layer, the portion of the protecting layer, and the portion of the first spacer are removed to expose the surface of the first conducting layer.
Accordingly, the present invention also provides a method for forming a floating gate. A semiconductor substrate is provided, with a dielectric layer, a hard mask layer, and a patterned resist layer sequentially formed thereon. The hard mask layer is etched to form an opening using the patterned resist layer as a mask, wherein the opening exposes the surface of the semiconductor substrate. The patterned resist layer is removed. A gate dielectric layer is formed on the exposed surface of the semiconductor substrate. A first poly layer is formed on the hard mask layer, and the opening is filled with the first poly layer. The first poly layer is chemical mechanical polished to expose the surface of the hard mask layer. The first poly layer in the opening is etched to a first predetermined thickness. An insulating layer is conformally formed on the surface of the hard mask layer and the opening. The insulating layer is anisotropically etched to form a first spacer on the sidewall of the opening. A second poly layer is conformally formed on the surface of the hard mask layer and the opening. The second poly layer is anisotropically etched to form a second spacer on the sidewall of the first spacer, wherein the second spacer covers the surface of the first spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the second spacer. A protecting layer is formed in the opening. The patterned resist layer is removed. A protecting layer is formed in the opening. The patterned resist layer, the first oxide layer, the portion of the protecting layer, and the portion of the first spacer are removed to expose the surface of the first conducting layer.
Accordingly, the present invention provides a floating gate. The floating gate comprises a conductive base and a conductive protruding layer, wherein the edge of the conductive base is tip-shaped, and the conductive protruding layer is crescent-shaped. The crescent-shaped structure is aligned with the tip-shaped structure, the bottom portion of the conductive protruding layer is narrower than the top portion of the conductive base, and a multi-tip floating gate is provided by the conductive base and the conductive protruding layer.
Accordingly, the present invention also provides a floating gate. The floating gate comprises a conductive base and a conductive protruding layer. The top edge of the conductive base is tip-shaped. The conductive base has a first sidewall and a second sidewall, wherein the first sidewall is parallel to the second sidewall. The conductive protruding layer is crescent-shaped, wherein the crescent-shaped structure is aligned with the tip-shaped structure. The bottom portion of the conductive protruding layer connects to the top portion of the conductive base, wherein the bottom portion of the conductive protruding layer is narrower than the conductive base, and a multi-tip floating gate is provided by the conductive base and the conductive protruding layer.
BRIEF DESCRIPTION OF THE DRAWINGSFor a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which:
A method for forming a multi-tip floating gate according to the present invention is shown in
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An insulating layer 210 is conformally formed on the surface of the hard mask layer 203, such as silicon oxide layer, and the opening 209, wherein the material of the insulating layer 210 is different from that of the hard mask layer 203.
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The floating gate 213 comprises a conductive base 208c and a conductive protruding layer 211a. The edge of the conductive base 208c is tip-shaped. The conductive base 208c has a first sidewall and a second sidewall, wherein the fist sidewall is parallel to the second sidewall. The conductive protruding layer 211a is formed on the conductive base 208c, wherein the bottom portion of the conductive protruding layer 211a connects to the top portion of the conductive base 208c, and the bottom portion of the conductive protruding layer 211a is narrower than the top portion of the conductive base 208c. The top portion of the conductive protruding layer 211a is crescent-shaped, and the crescent-shaped structure is aligned with the tip-shaped structure.
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Electric field concentration easily occurs at the tip, and the point is easily discharged. The effect of point discharge is increased by the floating gate's multiple tips in the present invention. Therefore, data erase for the flash memory having the floating gate with multiple tips is increased.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1-19. (canceled)
20. A floating gate, comprising:
- a conductive base, wherein a top edge of the conductive base is tip-shaped; and
- a conductive crescent-shaped protruding layer aligned with the tip-shaped structure, wherein a bottom portion of the conductive protruding layer is narrower than the conductive base, and a multi-tip floating gate is provided by the conductive base and the conductive protruding layer.
21. The floating gate of claim 20, wherein the conductive base is a poly layer.
22. The floating gate of claim 20, wherein the conductive protruding layer is a poly layer.
23. A floating gate, comprising:
- a conductive base, wherein a top edge of the conductive base is tip-shaped, the conductive base has a first sidewall and a second sidewall, the first sidewall parallel to the second sidewall; and
- a conductive protruding layer having a crescent-shaped structure, wherein the crescent-shaped structure is aligned with the tip-shaped structure, a bottom portion of the conductive protruding layer is connected to a top portion of the conductive base, the bottom portion of the conductive protruding layer is narrower than the conductive base, and a multi-tip floating gate is provided by the conductive base and the conductive protruding layer.
24. The floating gate of claim 23, wherein the conductive base is a poly layer.
25. The floating gate of claim 23, wherein the conductive protruding layer is a poly layer.
Type: Application
Filed: Dec 15, 2004
Publication Date: May 12, 2005
Applicant:
Inventors: Ying-Cheng Chuang (Bade City), Chung-Lin Huang (Taichung), Chi-Hui Lin (Taipei)
Application Number: 11/014,483