FOUR-PHASE DUAL PUMPING CIRCUIT
A four-phase dual pumping circuit has a number of stages according to the required output voltage based on an input voltage. Each stage has a first pumping unit and a second pumping unit that are mirror and identical to each other and electrically coupled to each other. The dual pumping circuit is controlled by four-phase clocks which are made from one pair of out of phase clocks. The transistors of the dual pumping circuit have special substrate connection to minimize body effects. The four-phase dual pumping circuit uses NMOSFETS for negative pumping and PMOSFETS for positive pumping.
1. Field of the Invention
The invention generally relates to charge pumps, and more particularly, to methods and apparatus for generating a high positive or a negative voltage for memory devices.
2. Description of the Prior Art
The era of digital information has arrived which pushed the development of electronic information processing devices such as computers, wireless devices, personal digital assistants (PDAs), portable multimedia players/recorders, and the like in the recent years. One crucial component to any electronic information processing device is the memory device which has gone under substantial advancement. The performance in speed and reliability along with the size and packaging of these memory devices have greatly improved as a result smaller and faster memory devices are continuously being introduced to the market.
In order to reduce power consumption and extend battery life, much of the integrated circuitry such as memory devices used in portable devices is being designed to run at low voltage levels. This reduces the power usage and reduces the heat generated by the circuit components allowing more components to be placed closer to one another. The circuitry and components used in portable computers typically are being designed to operate at voltages levels substantially less than the previous standard of 5V, with 1.0V and lower becoming increasingly common.
A major problem is that conventional charge pumps have difficulty dealing with the lower battery voltages being used. In particular, the MOS transistors used in the charge pumps have switching threshold voltages that are a large fraction of the supply voltage. The problem is related to the fact that diode-connected transistors develop increasing back-bias between the source and the body of the transistor as the voltage increases along the length of the pump. The result of this back-bias (also known as the “source-body effect”, “M factor”, or “body effect”) is to increase the effective threshold of the transistor, in some higher voltage cases almost doubling it. With increased effective transistor thresholds and decreased supply voltages, the charge pump transistors would no longer switch properly and the charge pump would not work.
Many designs used a technique called “bootstrapping” to generate higher amplitude clock signals to compensate for the increased effective threshold voltages relative to the supply voltage. The bootstrapping technique involves the use of a charge capacitor that charges on every clock pulse and discharges between pulses, adding the discharged voltage to the original input voltage of the bootstrapping circuit so the output could be multiplied to a number of times the original input. Applying a uniform high clock voltage, generated by bootstrapping, leads to energy inefficiency because the greater the current delivered by the clocking voltage, the less efficient the bootstrapping operation. In the latter stages where high voltages are required, this inefficiency was unavoidable. In the initial stages of the charge pump, where as high a voltage is not needed, the clock bootstrapping operation was inefficient.
In general, currently available charge pumps are inefficient, large, and complex. They do not properly deal with low initial supply voltages and fail to address the problems inherent with higher threshold voltages caused by the body effect. A solution, which would provide a simple charge pump with efficient operation using a low initial supply voltage, has long been sought but has eluded those skilled in the art. As the popularity grows of portable battery-powered devices in which such a design could be particularly useful, it is becoming more pressing that a solution be found.
Different approaches to designing charge pumps were previously disclosed. “Charge pump circuit having a boosted output signal” U.S. Pat. No. 4,935,644 by J. Tsujimoto shown in
It is therefore a primary objective of the claimed invention to provide four-phase dual pumping circuits that provide a high positive voltage that is above the supply voltage and at the same time a high negative voltage that is lower than the ground voltage which are required for write and erase operations in memory devices to solve the abovementioned problem.
It is another objective of the claimed invention to provide four-phase dual pumping circuits that efficiently generates the required high positive and high negative voltages using the same triple-well technology at a low supply voltage.
It is another objective of the claimed invention to provide a four-phase dual pumping circuit that minimizes the body effect of the main pass transistors so the output voltage is maximized.
It is another objective of the claimed invention to provide a four-phase dual pumping circuit that avoids p-n junction conduction.
According to the claimed invention, a four-phase dual pumping circuit is provided that can both operate as either a negative or positive dual pumping circuit. The negative dual pumping circuit uses NMOS transistors and the positive dual pumping circuit uses PMOS transistors. The dual pumping circuit of the present invention has a number of stages according to the required output voltage based on an input voltage. Each stage has a first pumping unit and a second pumping unit that are mirror and identical to each other and electrically coupled to each other, where each stage is electrically coupled to the preceding and subsequent stages. The first pumping unit and the second pumping unit of each stage generate outputs Vout1 and Vout2 respectively which are used as inputs for the subsequent stages for pumping the input voltage to a required output voltage. The first pumping unit and the second pumping unit of each stage has a main pass transistor, a boosting transistor, and a substrate transistor, where the main pass transistor is used to transfer charge to the subsequent stage, the boosting transistor is used to pre-charge the current stage, and the substrate transistor is used to supply a high voltage to the body of the control and boosting transistors during charge transfer to reduce body effects, wherein the main pass transistor, boosting transistor, and substrate transistor have a source, drain, gate, and body terminal. The substrate transistor of either pump circuit is controlled by a high voltage signal sent from the other pump circuit. As a result the first pumping unit and the second pumping unit of each stage alternately perform the pre-charge and charge transfer operation. The operation of the dual pumping circuit of the present invention is controlled by four sets of clock pulses in which one pair of clock pulses is out of phase and one pair of clock pulses may be generated by a high voltage circuit. One clock pulse from each pair (i.e. together two) is used to control each pumping circuit of the dual pumping circuit in an alternating manner. The output of the final stage is cross-coupled to maximize the output voltage. Additionally the input voltage of the final stage can be cross-coupled to increase the amplitude of the input voltage.
According to the claimed invention, a method for the first stage of the dual pumping circuit is provided which includes supplying an input voltage to the source terminals of the main pass transistors of the first pumping unit and the second pumping unit; during interval one to three, the first pumping unit performs charge sharing while the second pumping unit performs pre-charge; in interval one, rendering the main pass transistors of the first pumping unit and the second pumping unit, the substrate transistor of the second pumping unit, and the boosting transistor of the first pumping unit off, and the substrate transistor of the first pumping unit and the boosting transistor of the first pumping unit on; following in interval two, rendering the main pass transistor of the first pumping unit, the substrate transistor of the first pumping unit, and the boosting transistor of the second pumping unit on, and the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off; and continuing in interval three, rendering the main pass transistor of the first pumping unit, the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off, the boosting transistor of the second pumping unit, and the substrate transistor of the first pumping unit on.
During intervals four to six, the second pumping unit performs charge sharing while the first pumping unit performs pre-charge; in interval four, rendering the substrate transistor of first pumping unit, the main pass transistor of the first pumping unit, the main pass transistor of the second pumping unit, the boosting transistor of the second pumping unit off, and the boosting transistor of the first pumping unit, and the substrate transistor of the second pumping unit on; following in interval five, rendering the main pass transistor of the second pumping unit, the substrate transistor of the second pumping unit, and the boosting transistor of the first pumping unit on, and the substrate transistor of the first pumping unit, the main pass transistor of the first pumping unit, and the boosting transistor of the second pumping unit off; and continuing in interval six, rendering the main pass transistor of the second pumping unit, the substrate transistor of the first pumping unit, the main pass transistor of the first pumping unit, and the boosting transistor of the second pumping unit off, and the substrate transistor of the second pumping unit and the boosting transistor of the first pumping unit on.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF DRAWINGS
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The dual pumping circuit 500 comprises four serially linked stages 510, 520, 530, and 540 for achieving the required output voltage Vout from a low supply voltage Vdd. The positive dual pumping circuit 500 uses PMOS transistors based on triple-well with p-substrate technology which differs slightly that the negative dual pumping circuit 1500 that uses NMOS transistors. The stages 510, 520, 530, and 540 are all identical and each stage is comprised of a mirror structure further comprising an identical pair of a first pumping unit 512 and a second pumping unit 514. The first pumping unit 512 and the second pumping unit 514 of each stage are respectively electrically coupled to the first pumping unit and the second pumping unit of the preceding and subsequent stages with the exception that the first stage 510 of the dual pumping circuit is electrically coupled to an input voltage Vdd which is further electrically coupled to an inverter and the last stage 540 of the dual pumping circuit is electrically coupled to an output stage 550. The output Vout of the dual pumping circuit is electrically coupled to an output capacitor CL and is cross-coupled so that the charge can be transferred to the output more efficiently.
Four set of clock pulses labeled Fa, Fb, Fc, and Fd control the operation of the dual pumping circuit 500 wherein Fa and Fc are regular clock pulses and Fb and Fd may be high voltage clock pulses generated by a high voltage circuit (HVC) which is further described in
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In interval 1, in the first pumping unit, the clock pulse φb is at high so the gate of the first main pass transistor 812 is raised and is off but the clock pulse φa goes from high to low so the first large capacitor is not charged. The first substrate transistor 816 is turned on so the high voltage from the source of the second boosting transistor 824 in the second pumping unit 804 is transferred to the body of the first and second main pass transistors 812 and 822. At this instant, the source of the first main pass transistor 812 is high but the drain of the first main pass transistor 814 is low because the gate of the first main pass transistor 812 is raised. The first main pass transistor 814 is in an off state ready for charge sharing in the subsequent interval 2.
While the first pumping unit 802 is getting ready to perform charge sharing, the second pumping unit 804 performs pre-charge. In the second pumping unit 804, the clock pulse φc goes from low to high and clock pulse (Dd is at high and the second small capacitor 828 is charged and the large capacitor 830 is not charged. The second boosting transistor 824 is turned on from receiving the clock pulse φa that is at low to allow the source and drain of the second boosting transistor 824 to be in conduct to send the high voltage to the gate of the second main pass transistor 822. At the same time, the clock pulse φc that is at high raises the gate of the second substrate transistor 826 so it is off. The high voltage from the clock pulse φd at high renders the second main pass transistor 822 off so the second pumping unit 804 remains in pre-charge state.
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In this embodiment for a positive dual pumping circuit, the body of the transistors performing charge sharing is pumped to the highest voltage. In interval 2, in the first pumping unit 802, the body potentials of all the first main pass transistor 812, the first boosting transistor 814, and the first substrate transistor 816 are high when the gate of the first main pass transistor 812 receives the clock pulse φb that is at low. At this instant, the voltage from the preceding stage along with the clock pulse φc is transferred to the current stage. The first main pass transistor 812 experiences small influence of threshold voltage Vt drop because the gate voltage of the first main pass transistor 812 is much lower than its drain and source voltages. In the mean time, the voltage difference between the body, source, and drain is close to zero during the charge transfer which minimizes body effects and maximizes the gain from each stage of the dual pumping circuit of the present invention because the voltage level of the body of the transistors in the first pumping unit 802 is at the highest.
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In contrast to the prior art, the present invention provides a dual pumping circuit that can be implemented in either positive or negative with provides good pumping performance at low supply voltage (1V to 2V) using the popular triple-well technology. The dual pumping circuit uses four-phase clocks that has one pair of identical but out of phase clocks. The other two of the clocks may be chosen to be generated by a high voltage circuit to provide better pumping at low voltage. The positive dual pumping circuit uses PMOS transistors and the negative pumping circuit uses NMOS transistors where the transistors have special substrate connection to avoid body effect and p-n junction conduction.
Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A method for operating a dual pumping circuit comprising at least one stage, each stage comprising a first pumping unit and a second pumping unit mirrored to the first pumping unit to provide a common output, the first pumping unit comprising:
- a main pass transistor with gate, source, and drain terminals and a body, each main pass transistor of each stage being connected in series with main pass transistors of a preceding and a subsequent stage, and the body of the main pass transistor being electrically coupled to a main pass transistor of the second pumping unit;
- a boosting transistor with gate, source, and drain terminals and a body, the drain terminal of the boosting transistor being electrically coupled to the gate terminal of the main pass transistor, the source of the boosting transistor being electrically coupled to the drain of the main pass transistor, and the gate of the boosting transistor being electrically coupled to the source of the main pass transistor;
- a substrate transistor with gate, source, and drain terminals and a body, the gate terminal of the substrate transistor being electrically coupled to the source terminal of the boosting transistor, the drain terminal of the main pass transistor, and the source of a substrate transistor of the second pumping unit, the drain terminal of the substrate transistor being electrically coupled to the body of each main pass transistor of the first and second pumping units and the boosting transistor, the source terminal of the substrate transistor being electrically coupled to a gate terminal of a substrate transistor and a drain terminal of a main pass transistor and a source terminal of a boosting transistor of the second pumping unit, and the body of the substrate transistor being electrically coupled to a main pass transistor in the subsequent stage;
- two small charge storing devices respectively electrically coupled to the gate of the main pass transistor of the first pumping unit and the second pumping unit; and
- two large charge storing devices respectively electrically coupled to the drains of the main pass transistors of the first pumping unit and the second pumping unit;
- the method comprising, for a first stage:
- supplying an input voltage to the source terminals of the main pass transistors of the first pumping unit and the second pumping unit;
- in interval one, rendering the main pass transistor of the second pumping unit, the substrate transistor of the second pumping unit, and the boosting transistors of the first pumping unit and the main pass transistor of the first pumping unit off, and the substrate transistor of the first pumping unit and the boosting transistor of the second pumping unit on;
- in interval two, rendering the main pass transistor of the first pumping unit, the substrate transistor of the first pumping unit, and the boosting transistor of the second pumping unit on, and the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off;
- in interval three, rendering the main pass transistor of the first pumping unit, the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off, the boosting transistor of the second pumping unit, and the substrate transistor of the first pumping unit on;
- in interval four, rendering the substrate transistor of first pumping unit, the main pass transistor of the first pumping unit, the main pass transistor of the second pumping unit, and the boosting transistor of the second pumping unit off, the boosting transistor of the first pumping unit and the substrate transistor of the second pumping unit on;
- in interval five, rendering the main pass transistor of the second pumping unit, the substrate transistor of the second pumping unit, and the boosting transistor of the first pumping unit on, and the substrate transistor of the first pumping unit, the main pass transistor of the first pumping unit, and the boosting transistor of the second pumping unit off; and
- in interval six, rendering the main pass transistor of the second pumping unit, the substrate transistor of the first pumping unit, the main pass transistor of the first pumping unit, and the boosting transistor of the second pumping unit off, and the substrate transistor of the second pumping unit and the boosting transistor of the first pumping unit on.
2. The method in claim 1 further comprising, for each even stage of the dual pumping circuit:
- in interval one, rendering the substrate transistor or the first pumping unit and the boosting transistor of the second pumping unit on, the main pass transistor of the first pumping unit, the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off;
- in interval two, rendering the main pass transistor of the first pumping unit, the substrate transistor of the first pumping unit, and the boosting transistor of the second pumping unit on, and the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off;
- in interval three, rendering the substrate transistor of the first pumping unit and the boosting transistor of the second pumping unit on, and the main pass transistor of the first pumping unit, the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit being kept off;
- in interval four, rendering the substrate transistor of first pumping unit, the boosting transistor of the second pumping unit, the main pass transistor of the first pumping unit, and the main pass transistor of the second pumping unit off, the substrate transistor of the second pumping unit and the boosting transistor of the first pumping unit on;
- in interval five, rendering the substrate transistor of first pumping unit, the boosting transistor of the second pumping unit, and the main pass transistor of the first pumping unit off, the substrate transistor of the second pumping unit, the boosting transistor of the first pumping unit, and the main pass transistor of the second pumping unit on; and
- in interval six, rendering the substrate transistor of first pumping unit, the boosting transistor of the second pumping unit, the main pass transistor of the first pumping unit, and the main pass transistor of the second pumping unit off, and the substrate transistor of the second pumping unit and the boosting transistor of the first pumping unit on.
3. The method in claim 2 further comprising, for each odd stage of the dual pumping circuit except the first stage:
- in interval one, rendering the substrate transistor of first pumping unit, the boosting transistor of the second pumping unit, the main pass transistor of the first pumping unit, and the main pass transistor of the second pumping unit off, and the substrate transistor of the second pumping unit and the boosting transistor of the first pumping unit on;
- in interval two, rendering the substrate transistor of first pumping unit, the boosting transistor of the second pumping unit, and the main pass transistor of the first pumping unit off, the substrate transistor of the second pumping unit, the boosting transistor of the first pumping unit, and the main pass transistor of the second pumping unit on;
- in interval three, rendering the substrate transistor of first pumping unit, the boosting transistor of the second pumping unit, the main pass transistor of the first pumping unit, and the main pass transistor of the second pumping unit off, and the substrate transistor of the second pumping unit and the boosting transistor of the first pumping unit on;
- in interval four, rendering the substrate transistor of the first pumping unit and the boosting transistor of the second pumping unit on, the main pass transistor of the first pumping unit, the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off;
- in interval five, rendering the main pass transistor of the first pumping unit, the substrate transistor of the first pumping unit, and the boosting transistor of the second pumping unit on, the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off; and
- in interval six, rendering the substrate transistor of the first pumping unit and the boosting transistor of the second pumping unit on, and the main pass transistor of the first pumping unit, the boosting transistor of the first pumping unit, the substrate transistor of the second pumping unit, and the main pass transistor of the second pumping unit off.
4. The method in claim 1, wherein the intervals one, two, three, four, five, and six are consecutive and in sequence.
5. The method in claim 1, wherein the dual pumping circuit further comprises:
- first and second output transistors each with source, drain, and gate terminals and a body, the first output transistor mirroring the second output transistor, the source terminal of the first output transistor being electrically coupled to the drain terminal of the main pass transistor of the first pumping unit in a last stage, the gate terminal of the first output transistor being electrically coupled to the drain terminal of the substrate transistor of the second pumping unit in the last stage, and the body of the first output transistor being electrically coupled to the drain terminal of the substrate transistor of the second pumping unit in the last stage; the method further comprising:
- rendering the first output transistor on when the substrate transistor of the second pumping unit in the last stage is rendered on and rendering the second output transistor off when the substrate transistor of the first pumping unit of the last stage is rendered off.
6. The method in claim 1, wherein supplying a voltage to the sources of the main pass transistors of the first stage is controlled by an inverter.
7. The method in claim 1, wherein the body of the main pass transistor of the first pumping unit and the body of the main pass transistor of the second pumping unit in each stage of the dual pumping circuit are preset to an appropriate bias voltage before pumping.
8. The method in claim 7, wherein the additional input voltage is controlled by a transistor that is electrically coupled to a capacitor.
9. A dual pumping circuit comprising at least one stage, each stage comprising a first pumping unit and a second pumping unit which are mirrored to each other to provide a common output, and each first pumping unit comprising:
- a main pass transistor with gate, source, and drain terminals and a body, each main pass transistor of each stage being connected in series with main pass transistors of a preceding and a subsequent stage, and the body of the main pass transistor being electrically coupled to a main pass transistor of the second pumping unit;
- a boosting transistor with gate, source, and drain terminals and a body, the drain terminal of the boosting transistor being electrically coupled to the gate terminal of the main pass transistor, the source of the boosting transistor being electrically coupled to the drain of the main pass transistor, and the gate of the boosting transistor being electrically coupled to the source of the main pass transistor;
- a substrate transistor with gate, source, and drain terminals and a body, the gate terminal of the substrate transistor being electrically coupled to the source terminal of the boosting transistor, the drain terminal of the main pass transistor, and the source of a substrate transistor of the second pumping unit, the drain terminal of the substrate transistor being electrically coupled to the body of each main pass transistor of the first and second pumping units and the boosting transistor, the source terminal of the substrate transistor being electrically coupled to a gate terminal of a substrate transistor and a drain terminal of a main pass transistor and a source terminal of a boosting-transistor of the second pumping unit, and the body of the substrate transistor being electrically coupled to a main pass transistor in the subsequent stage;
- two small charge storing devices respectively electrically coupled to the gate of the main pass transistor of the first pumping unit and the second pumping unit; and
- two large charge storing devices respectively electrically coupled to the drain of the main pass transistor of the first pumping unit and the second pumping unit.
10. The dual pumping circuit in claim 9 further comprising a diode that is electrically coupled to each of the small charge storing devices and the large charge storing devices.
11. The dual pumping circuit in claim 9 wherein the gate terminal of the boosting transistor of the first and the second pumping units in the first stage is electrically coupled to a supply voltage, and the gate terminals of the boosting transistors of the first and the second pumping units in a stage other than the first stage is electrically coupled to the source terminals of the boosting transistors of the first and the second pumping units in the previous stage, respectively.
12. The dual pumping circuit in claim 9 further comprising a high voltage circuit applying to the two small charge storing devices for increasing a voltage level of clock pulses.
13. The method in claim 9, wherein the dual pumping circuit further comprises:
- first and second output transistors each with source, drain, and gate terminals and a body, the first output transistor mirroring the second output transistor, the source terminal of the first output transistor being electrically coupled to the drain terminal of the main pass transistor of the first pumping unit in a last stage and the gate terminal of the second output transistor, the gate terminal of the first output transistor being electrically coupled to the drain terminal of the main pass transistor of the second pumping unit in the last stage, and the body of the first output transistor being electrically coupled to the drain terminal of the substrate transistor of the second pumping unit in the last stage.
14. The dual pumping circuit in claim 9, wherein the main pass transistor, the boosting transistor, and the substrate transistor are NMOSFETs for negative pumping.
15. The dual pumping circuit in claim 9, wherein the main pass transistor, the boosting transistor, and the substrate-transistor are PMOSFETs for positive pumping.
16. The dual pumping circuit in claim 9, wherein a first clock pulse is sent to the gate of the first substrate transistor of the first pumping unit, a second clock pulse is sent to the gate of the main pass transistor of the first pumping unit, a third clock pulse is sent to the gate of the substrate transistor of the second pumping unit, and a fourth clock pulse is sent to the gate of the main pass transistor of the second pumping unit where the first and third clock pulses are out of phase and the second clock pulse turns on the main pass transistor of the first pumping unit for a shorter time than the first clock pulse does; and the fourth clock pulse turns on the main pass transistor of the second pumping unit for a shorter time than the third clock pulse does.
Type: Application
Filed: Jan 12, 2004
Publication Date: Jul 14, 2005
Patent Grant number: 6952129
Inventors: Hong-chin Lin (Taipei City), Ming-Chih Hsieh (Taipei City), Jain-Hao Lu (Taipei City), Chien-Hung Ho (Hsin-Chu City)
Application Number: 10/707,786