Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture
A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover or enclosure disposed around at least a portion of the substrate and the conductive link. The package can be filled with a liquid or a pressurized gas to transfer heat away from the conductive link. In one embodiment, the enclosure can have a composition substantially identical to the composition of the conductive links and the enclosure can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.
The present application is a continuation-in-part of U.S. Application No. 09/640,149, filed Aug. 16, 2000 (attorney docket number 10829.8512US) and U.S. application Ser. No. 09/382,929, filed Aug. 25, 1999 (attorney docket number 00303.603US1), both incorporated herein in their entireties by reference.
TECHNICAL FIELDThis invention relates to microelectronic device packages filled with liquid or pressurized gas, and methods for manufacturing and processing such packages.
BACKGROUND OF THE INVENTIONPackaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic substrate die encased in a plastic, ceramic, or metal protective covering. The die includes functional devices or features, such as memory cells, processor circuits, and interconnecting wiring. The die also typically includes bond pads electrically coupled to the functional devices. The bond pads can be coupled to pins or other types of terminals that extend outside the protective covering for connecting to busses, circuits and/or other microelectronic assemblies.
As the size of microelectronic device packages decreases to allow the packages to fit into more compact electronic products (such as mobile phones and laptop computers), the distances between adjacent functional devices and between adjacent interconnecting wires decreases. As these distances decrease, the likelihood for capacitive coupling between adjacent structures increases, which can impair or reduce the maximum performance of the packaged microelectronic device.
One approach to decreasing the capacitance between neighboring wires within the die is to reduce the dielectric constant of the solid material between the wires. For example, polyimides (having a dielectric constant of 3.5) have been used to replace silicon dioxide (having a dielectric constant of 4). A more substantial reduction in the dielectric constant is obtained by replacing the solid insulating material typically positioned between layers of the wiring with a gas, such as air. For example, U.S. Pat. No. 5,891,797 to Farrar and U.S. Pat. No. 5,324,683 to Fitch et al. disclose a process for building successive layers of wiring on a semiconductor substrate by temporarily supporting the wires with sacrificial filler material, and then removing the filler material from around the wires by etching or a plasma process to form suspended “air bridges” that conduct electrical signals from one part of the device package to another. The wires can be formed in the filler material using a dual damascene process, such as is disclosed in U.S. Pat. No. 4,962,058 to Cronin et al. The support material can include a resist material, as disclosed in U.S. Pat. No. 5,593,926 to Fujihiri, that can be removed by etching processes (such as the processes disclosed in U.S. Pat. No. 4,561,173 to Te Velde) or evaporative processes (such as the processes disclosed in U.S. Pat. No. 5,408,742 to Zaidel et al.). U.S. Pat. Nos. 5,891,797; 5,324,683; 4,962,058; 5,593,926; 4,561,173; and 5,408,742 are herein incorporated in their entirety by reference.
It can be shown that the maximum unsupported link of an air bridge in an integrated circuit is governed by the following equation:
L=4{square root}{square root over (32Eδh2/5p)} or ≈1.6(Eδ/p)1/4h1/2
where
-
- L=the unsupported bridge length
- E=the modular elasticity of the bridge material
- δ=the maximum allowable deflection of the bridge
- η=the density of the bridge material
- h=the vertical thickness of the bridge
As microelectronic devices become smaller, the thicknesses of the bridges and the distances between adjacent bridges also become smaller. To prevent the bridges from sagging into each other, the maximum unsupported length of each bridge decreases. For example, if the bridge is made of an aluminum copper silicon alloy (which has a module of elasticity of 71 GPa and a density of 2.79 Mg/m3), has a maximum allowable deflection of 5,000 angstroms (including a safety factor), and a thickness of 10,000 angstroms, the maximum unsupported bridge length is approximately 1.6 millimeters. If the maximum allowable deflection is decreased to 2,500 angstroms, and the bridge thickness is reduced to 5,000 angstroms, the maximum unsupported bridge length is approximately 1 millimeter. If the maximum allowable deflection is further decreased to 1,500 angstroms, the maximum allowable unsupported length is approximately 0.6 millimeters. Because current chips typically measure over 1 centimeter along an edge, it becomes increasingly difficult to reduce the thickness of the bridges and the spacing between bridges without supporting the bridges at such frequent intervals that the benefits of unsupported bridge segments (e.g., the reduced dielectric constant of the material adjacent to the bridge) are lost.
Furthermore, as the bridge thickness (and therefore the cross-section of the conductive line forming the bridge) decreases, the resistivity of the wire forming the bridge increases. One approach to addressing this drawback is to reduce the bulk resistivity of the wire, for example, by replacing aluminum alloy wires with copper wires. However, copper has a significantly greater density than aluminum and aluminum alloys, and therefore has only 85% of the unsupported bridge length of an aluminum or aluminum alloy conductor.
Another problem with conventional air bridge designs is that the air adjacent to the wires typically has a lower thermal conductivity than the solid material it replaced. Accordingly, it can be more difficult to transfer heat from the packaged microelectronic device. As a result, the microelectronic device may be more likely to overheat, which can reduce the life expectancy and/or performance level of the device.
SUMMARYThe present invention is directed toward microelectronic device packages and methods for forming such packages. A package in accordance with one aspect of the invention includes a microelectronic substrate having at least one microelectronic device feature. The package can further include a conductive link that includes a conductive material and is coupled to the at least one microelectronic device feature. An enclosure is sealably disposed around at least a portion of the microelectronic substrate and the conductive link, with the enclosure being configured to contain a gas in contact with the conductive link at a pressure at least one atmosphere greater than a pressure external to the enclosure.
In one aspect of the invention, the package can include helium and/or hydrogen at a pressure of from about five atmospheres to about 50 atmospheres above atmospheric pressure. The conductive link can include a wirebond or solder ball coupled between the microelectronic substrate and a substrate support. In another aspect of the invention, the conductive link can be coupled between two microelectronic device features and at least a portion of the conductive link can be suspended between first and second points between the two microelectronic device features.
The invention is also directed toward a method for manufacturing a microelectronic device package. In one aspect of the invention, the method can include forming at least one microelectronic device feature at least proximate to a surface of a microelectronic substrate, coupling a conductive link to the at least one microelectronic device feature, and disposing an enclosure around at least a portion of the microelectronic substrate. The method can further include sealing a gas within the enclosure, with the gas being in contact with the conductive link and at a pressure of at least one atmosphere above atmospheric pressure. The method can further include exposing the enclosure to atmospheric pressure while the gas remains sealed within the enclosure.
In a further aspect of the invention, the method can include placing the microelectronic substrate, the enclosure and the conductive link in a controlled pressure environment and reducing a pressure within the controlled pressure environment to withdraw gas from the enclosure while the enclosure remains open to the controlled pressure environment. The method can further include elevating the pressure within the controlled pressure environment to be at least one atmosphere greater than atmospheric pressure while the enclosure remains open to the controlled pressure environment. The method can still further include sealing the enclosure while the enclosure remains in the controlled pressure environment and removing the enclosure, the microelectronic substrate, and the conductive link as a unit from the controlled pressure environment.
BRIEF DESCRIPTION OF THE DRAWINGSFIGS. 1A-G are partially schematic, cross-sectional side elevational views depicting a process for forming a packaged microelectronic device having a first level of conductive structures in accordance with an embodiment of the invention.
FIGS. 6A-F are partially schematic, cross-sectional side elevational views depicting a process for filling a microelectronic device package with liquid or pressurized gas in accordance with an embodiment of the invention.
The present disclosure describes packaged microelectronic devices and methods for manufacturing such devices. The packages can have a microelectronic substrate positioned in a sealed enclosure. Conductive links within the enclosure can be in contact with a liquid or a pressurized gas to transfer heat from the conductive links to the surfaces of the enclosure. Many specific details of certain embodiments of the invention are set forth in the following description and in
In one aspect of this embodiment, the first level 46 is initially filled with a sacrificial support structure or mandrel 30. The sacrificial support structure 30 can include a lower level portion 30a disposed on the substrate upper surface 22 and an upper level portion 30b disposed on the lower level portion 30a. Each level portion 30a, 30b can include a bulk support material 32 (shown as a lower support layer 32a and an upper support layer 32b) and an etch stop material 31 (shown as a lower etch stop layer 31a and an upper etch stop layer 31b). The etch stop material 31 can include an oxide (such as silicon dioxide), a nitride (such as silicon nitride) or other selectively removable materials. The bulk support material 32 can include carbon or a polymer (such as a photoresist material, a polyimide, parylene or parylene-C) so long as the bulk support material 32 is rigid enough to support the conductive links, but can also be easily removed from adjacent to the conductive links without damaging the conductive links, as described in greater detail below.
In another aspect of this embodiment, the lower support layer 32a and the lower etch stop layer 31a have a combined height or thickness H1 that corresponds to the height of the gap beneath the suspended portions of the conductive links in the first level 46. The upper support layer 32b and upper etch stop layer 31b have a combined height or thickness H2 that corresponds to the thickness of the suspended portions of the conductive links in the first level 46.
In one embodiment, the conductive links and other conductive components are formed in the first level 46 using a dual damascene process. For example (referring now to
Referring now to
The conductive structures 80 can further include an internal conductive support 83 with a first level portion 43 that extends transversely to the upper surface 22 within the package 60. The internal conductive support 83 can include a rib that extends a substantial distance transverse to the plane of
Both the internal conductive support 83 and the external wall 85 can support other structures in levels above the first level 46. Alternatively, (for example, when the package 60 is a “flip chip”), the internal conductive supports 83 and the external wall 85 can be sized to support the substrate 20 when the package 60 is inverted. When several packages 60 are initially formed on the same substrate 20, the external walls 85 can also be sized to account for the width of a blade or other cutting medium that singulates adjacent completed packages 60 from each other.
In one aspect of an embodiment shown in
In one aspect of this embodiment, the third level portion 241 of one or more of the conductive links 81 can extend through the internal support 83. Accordingly, the internal support 83 can have an aperture 247 through which the bridge portion 241b of the conductive link 81 passes, with the bridge portion 241b separated from the walls of the aperture 247. The walls of the aperture 247 are defined in part by the upper surface of the second level portion 143 of the internal conductive support 83 and the lower surface of the third level portion, described below with reference to
In one aspect of this embodiment, a very thin layer of an adhesive material, such as zirconium, titanium, and/or chromium can be applied to the upper surface of the fourth level 346 to improve adhesion between the insulating layer 453 and the metal components of the fourth level 346. In another aspect of this embodiment, the mechanical stress of the insulating layer 453 can be reduced by implanting a small dose of inert or other ions into the insulating layer 453. Alternatively, a metal strengthener can be deposited on the insulator (rather than reducing mechanical stress of the insulator itself). The metal can include a material such as titanium, which has a high elastic modulus, low density, and high resistivity. The stress in the metal layer can be reduced by implanting a small dose of inert or other ions into the metal layer, or (when the metal layer is sputtered), by controlling the sputtering parameters.
In any of the embodiments described above for forming the connecting structure 450, bond pads 451 are connected through the insulating layer 453 (and the metal strengthening layer, if present) to the conductive links 81. For example, vias 452 can extend between the bond pads 451 and the fourth level portions 341 of the conductive links 81. The bond pads 451 and vias 452 can be formed by conventional processes, such as photolithography in combination with reactive ion etching. When reactive ion etching is used and the fourth level portions 341 include copper, the copper can provide an etch stop. When the fourth level portions 341 include other materials, other processes (such as other etching processes) can be used to form the vias 452 and the bond pads 451.
In one embodiment, access openings 454 are formed in the insulating layer 453 and penetrate through the insulating layer 453 to the fourth level 346. The access openings 454 allow the sacrificial support structure 30 (
The resulting package 60 (shown in
FIGS. 6A-F illustrate an embodiment of a method for disposing a pressurized gas, or a liquid, in the package 60 described above with reference to
Turning now to
Referring now to
After the sacrificial support structure has been removed from the enclosure 60, any gaseous byproducts can be removed from the package 60, for example by placing the package 60 in a pressure chamber 419 (shown in
In one embodiment, the relative amounts of helium and hydrogen selected for the package 60 may depend upon the application for which the package is intended. For example, when the package 60 is to be placed in an environment demanding a high heat transfer rate, the gas 418 can be primarily or entirely hydrogen because hydrogen is more thermally conductive than helium at the same pressure. Conversely, when the package 60 is to be placed in an environment where the heat transfer requirements are lower and/or the gas 418 is subject to certain handling constraints, the gas 418 can be primarily or entirely helium. In other embodiments, the gas 418 can have other compositions.
In any of the foregoing embodiments, the pressure of the gas 418 within the pressure chamber 419 (and therefore within the package 60) can be elevated to be at least one atmosphere above atmospheric pressure. In a further aspect of this embodiment, the pressure of the gas 418 can be elevated to be from about 5 atmospheres to about 50 atmospheres above atmospheric pressure. Accordingly, the package 60 will become filled with the gas 418 at a pressure elevated will beyond atmospheric pressure.
Once the package 60 has been filled with the gas 418, the access openings 454 can be sealed to prevent or at least restrict the gas 418 from escaping when the package 60 is exposed to atmospheric pressure. In one embodiment, a seal lid 414 can be positioned on the solder ring 413, and the temperature of the pressure chamber 419 can be elevated until the solder ring 413 melts and bonds the seal lid 414 to the seal bond ring 411. After the solder ring 413 has cooled, the package 60 can be removed from the pressure chamber 419, as shown in
In any of the foregoing embodiments described above with reference to
A further advantage of an embodiment of the package and process described above is that the package can be initially pressurized to levels substantially above atmospheric pressure, for example, from about 5 to about 50 atmospheres above ambient pressure. Accordingly, even if the gas slowly leaks from the package, the pressure within the package can remain well above atmospheric pressure over the expected life of the package. This is unlike some conventional devices which are pressurized to a level just high enough to balance the amount of gas expected to leak from the package over the life of the package. Such conventional devices are configured to have an internal pressure just above atmospheric pressure by the end of the expected life span of the package, due to gas leakage from the package, and accordingly may be more likely to overheat as the package ages.
Another feature of an embodiment of the process described above with reference to
Yet another advantage of this feature is that a greater portion of the package 60 is formed from materials having relatively high heat conductivity. Accordingly, it can be easier to transfer heat away from the package 60 and reduce the temperature at which the package operates, which is expected to increase the operating life and/or the performance characteristics of the package 60.
Once the package 60 is complete, it can be singulated from adjacent packages (not shown) and joined to a support substrate for coupling to other electronic components. For example, in one embodiment, the package can be attached to a printed circuit board 490 or other substrate by adhesively bonding the microelectronic substrate 20 to the printed circuit board and attaching wire bonds 492 between the bond pads 451 of the package 60 and corresponding contacts 491 on a printed circuit board 490. When the package 60 is configured to be positioned uprightly on the support substrate, the external walls 85 and the internal structures 83 are sized to support only the connection structure 450 and the forces resulting from connecting wire bonds to the connection structure 450.
Alternatively, the package 60 can be configured as a “flip chip” by attaching the solder balls 493 to the bond pads 451 and inverting the package 60 so that the solder balls 493 contact corresponding ball pads on the printed circuit board 490 or other support substrate. When the package 60 is configured as a flip chip, the external walls 85 and internal support structures 83 are sized to support the microelectronic substrate 20.
In another aspect of this embodiment, the package 60 can be inverted, placed on the supporting substrate 490, and bonded to the substrate 490, all before removing the sacrificial support structure 30 from the package 60. An advantage of this method is that the sacrificial support structure 30 remains in place during more processing steps than it does with conventional techniques, reducing the likelihood for portions of the package 60 to collapse during these process steps.
In other embodiments, the process described above with reference to
When the sacrificial support structure 30 includes carbon, the cavities 35 can also be formed with a dual damascene process. The carbon can be exposed to a high temperature oxygen atmosphere to reduce the carbon to CO2, again leaving the conductive structures 80 in place. In other embodiments, the sacrificial support structure 30 can include other materials, so long as these materials can be removed from the package 60, for example, using a wet etch, plasma etch, or oxidation process.
In still further embodiments, processes other than a dual damascene process can be used to form the cavities in the sacrificial support structure 30. For example, two single damascene processes can be used to first form those portions of the conductive structures 80 that contact the level below, and then form the portions of the conductive structures 80 that are suspended above the level below. An advantage of the dual damascene process is that the conductive material forming both portions of the conductive structures 80 are disposed in a single step, reducing the likelihood for physical and/or electrical disconnects between portions of the conductive structures within a single level.
In yet another embodiment, at least some of the structures 80 described above with reference to
In yet another embodiment, the external wall 85 can be initially formed on the substrate 20 simultaneously with the conductive internal structures (such as the conductive links 81 and the internal support structure 83), and can subsequently be further processed. For example, the external wall 85 can be plated or otherwise treated to reduce the likelihood for corrosion of the external wall or other detrimental environmental effects.
In still another embodiment, an initially separate heat sink (not shown) can be attached to the package 60 after the package 60 has been formed. For example, when the package 60 has a flip chip configuration, the heat sink can be attached to the lower surface 23 (
In yet another embodiment, the package 60 described above with reference to
In other embodiments, the package 60 can have other arrangements that include suspended conductive links. For example, as shown in
One feature of an embodiment of the package 660 shown in
In yet another embodiment, the conductive structures in contact with the pressurized gas within the enclosure 660 need not be suspended between two points. For example, the enclosure 660 can include a foam 687 that partially fills the volume between the conductive links 681 and the external walls 685 and the ribs 686. The pores within the foam 687 can be charged with pressurized gas, in a manner generally similar to that described above. In other embodiments, the enclosure 660 can have other arrangements, so long as the pressurized gas is in contact with the conductive links 681 for transferring heat away from the conductive links 681.
In any of the foregoing embodiments described above with reference to
In any of the foregoing embodiments described above with reference to
One feature of an embodiment of the package 960 described above with reference to
In one aspect of an embodiment of the package 1060 shown in
From the foregoing, it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Claims
1-62. (canceled)
63. A method for manufacturing a microelectronic device package, comprising:
- forming at least one microelectronic device feature at least proximate to a surface of a microelectronic substrate;
- coupling a conductive link to the at least one microelectronic device feature of the microelectronic substrate;
- disposing an enclosure around at least a portion of the microelectronic substrate;
- sealing a gas within the enclosure and in contact with the conductive link with the gas at a pressure of at least one atmosphere above atmospheric pressure; and
- exposing the enclosure to atmospheric pressure while the gas remains sealed within the enclosure.
64. The method of claim 63, further comprising:
- placing the microelectronic substrate, the enclosure, and the conductive link in an controlled pressure environment;
- reducing a pressure within the controlled pressure environment to withdraw gas from the enclosure while the enclosure remains open to the controlled pressure environment;
- elevating a pressure within the controlled pressure environment to be at least one atmosphere greater than atmospheric pressure while the enclosure remains open to the controlled pressure environment;
- sealing the enclosure while the enclosure remains in the controlled pressure environment; and
- removing the enclosure, the microelectronic substrate and the conductive link as a unit from the controlled pressure environment.
65. The method of claim 63 wherein the enclosure includes a contact structure having contacts with solder balls for electrically coupling the microelectronic substrate to other devices, and wherein the method further comprises bonding the solder balls to another device after sealing an aperture in the enclosure to seal the gas in the enclosure.
66. The method of claim 63 wherein the enclosure includes an aperture and sealing a gas within the enclosure includes disposing solder on a metallic ring disposed around the aperture, disposing a metallic lid on the solder, and elevating a temperature of the enclosure to bond the metallic lid to the metallic ring.
67. The method of claim 63, further comprising selecting the gas disposed within the enclosure to include at least one of hydrogen and helium.
68. The method of claim 63 wherein placing the microelectronic substrate, the enclosure, and the conductive link in an elevated pressure environment includes placing the microelectronic substrate, the enclosure, and the conductive link in an elevated pressure environment having a pressure of from about 5 atmospheres to about 50 atmospheres above atmospheric pressure.
69. The method of claim 63 wherein the enclosure includes an aperture positioned to allow the gas to enter the enclosure and contact the conductive link, and wherein the method further comprises sealing the aperture before removing the enclosure from the elevated pressure environment.
70. The method of claim 63 wherein disposing the enclosure around the microelectronic substrate includes:
- forming walls extending away from the microelectronic substrate;
- forming a contact structure adjacent to the walls, the contact structure having at least one contact electrically coupled to the conductive link and configured to couple the microelectronic substrate to other components, the contact structure further having an aperture for receiving the gas in the enclosure; and
- sealing the aperture in the contact structure after the gas enters the enclosure and before removing the enclosure from the elevated pressure environment.
71. The method of claim 63 wherein the enclosure includes a contact structure having electrical contacts for coupling the microelectronic package to other components, the enclosure further including walls between the contact structure and the microelectronic substrate, and wherein the method includes forming the walls to support a weight of the microelectronic substrate when the contact structure faces downwardly.
72. The method of claim 63, further comprising disposing a foam material between the conductive link and an interior surface of the enclosure.
73. The method of claim 63, further comprising selecting the gas to include a reducing agent.
74. The method of claim 63, further comprising selecting the enclosure to include an electrically insulative material sealed to the microelectronic substrate.
75. The method of claim 63 wherein the microelectronic device feature is a first microelectronic device feature and the microelectronic substrate includes a second microelectronic device feature, and wherein the method further comprises suspending at least a portion of the conductive link between two points positioned between the first and second microelectronic device features.
76. The method of claim 63, further comprising selecting the enclosure to include an electrically conductive material.
77. The method of claim 63, further comprising selecting the enclosure to include at least one of copper, a copper alloy, aluminum and an aluminum alloy.
78. The method of claim 63, further comprising selecting the enclosure to include at least one of silicon dioxide and silicon nitride.
79. The method of claim 63, further comprising selecting the enclosure to include the same conductive as is included in the conductive link.
80. The method of claim 63, further comprising forming at least a portion of the enclosure simultaneously with forming the conductive link.
81. The method of claim 63 wherein the at least one microelectronic device feature is coupled to a first bond site, and wherein the method further comprises:
- supporting the microelectronic substrate with a support substrate; and
- connecting the conductive link between the first bond site and a second bond site positioned on the support substrate.
82. A method for manufacturing a microelectronic device package, comprising:
- forming first and second microelectronic device features at least proximate to a surface of a microelectronic substrate;
- coupling a conductive link between the first and second microelectronic device features of the microelectronic substrate;
- removing a sacrificial material adjacent to the conductive link to suspend at least a portion of the conductive link between two points;
- disposing an enclosure around at least a portion of the microelectronic substrate;
- sealing a gas within the enclosure and adjacent to the conductive link; and
- exposing the enclosure to a pressure at least five atmospheres less than a pressure within the enclosure while the gas remains sealed within the enclosure.
83. The method of claim 82, further comprising:
- disposing the sacrificial material on the microelectronic substrate;
- forming a void in the sacrificial material, with a location of the void coinciding with a location of the conductive link; and
- filling the void with conductive material to form the conductive link.
84. The method of claim 82, further comprising forming at least a portion of the enclosure simultaneously with forming the conductive link by:
- disposing the sacrificial material on the microelectronic substrate;
- forming first and second voids in the sacrificial material with the first void corresponding a portion of the enclosure and the second void corresponding to the conductive link; and
- filling the first and second voids to simultaneously form the external wall portion of the package and the conductive link.
85. The method of claim 82, further comprising forming at least a portion of the enclosure and the conductive link simultaneously by:
- disposing a first layer of a first component of the sacrificial material on the microelectronic substrate;
- disposing a first layer of a second component of the sacrificial material on the first layer of the first component to form a first etch stop layer;
- disposing a second layer of the first component on the first etch stop layer;
- disposing a second layer of the second component on the second layer of the first component to form a second etch stop layer;
- forming a first void in first layer of the first component with the first void corresponding to a portion of the enclosure and extending transverse to the surface of the microelectronic substrate;
- forming a second void in the second layer of the first component with the second void corresponding to a portion of the enclosure extending transverse to the surface of the microelectronic substrate and a portion of the conductive link extending along an axis generally aligned with the surface of the microelectronic substrate; and
- filling the first and second voids to simultaneously form the external wall portion of the package and the conductive link.
86. The method of claim 82, further comprising selecting the sacrificial material to include at least one of a carbonaceous material, a polymer, a polyimide, a photoresist material, parylene, and parylene-C.
87. The method of claim 82, further comprising selecting a material for the enclosure to be the same as a material for the conductive link.
88. The method of claim 82, further comprising:
- forming an internal support member inward from the enclosure and simultaneously with forming at least a portion of the enclosure; and
- supporting the conductive link with the internal support member.
89. The method of claim 82, further comprising selecting a thickness of the enclosure to support a weight of the package when the package is inverted with the microelectronic substrate facing upwardly.
90. The method of claim 82 wherein the enclosure includes an aperture positioned to allow the gas to enter the enclosure and contact the conductive link, and wherein the method further comprises sealing the aperture before removing the enclosure from the elevated pressure environment.
91. The method of claim 82 wherein sealing a gas within the enclosure includes disposing a metallic ring about an aperture in the enclosure, disposing a solder ring on the metallic ring, and soldering a metallic lid on the solder ring to at least restrict a flow of gas outwardly from the enclosure.
92. The method of claim 82, further comprising forming the enclosure to include a contact structure having electrical contacts for coupling the microelectronic package to other components.
93. A method for manufacturing a microelectronic device package, comprising:
- forming first and second microelectronic device features at least proximate to a surface of a microelectronic substrate;
- coupling a conductive link between the first and second microelectronic device features of the microelectronic substrate;
- removing a sacrificial material adjacent to the conductive link to suspend at least a portion of the conductive link between two points;
- disposing an enclosure around at least a portion of the microelectronic substrate; and
- sealing a liquid within the enclosure and adjacent to the conductive link.
94. The method of claim 93, further comprising selecting the liquid to include carbon tetrachloride.
95. The method of claim 93, further comprising selecting the liquid to be generally electrically non-conductive.
96. The method of claim 93, further comprising selecting the liquid to be an organic liquid.
97. The method of claim 93 wherein sealing the liquid within the enclosure includes disposing a metallic ring about an aperture in the enclosure, disposing a solder ring on the metallic ring, and soldering a metallic lid on the solder ring.
98. The method of claim 93, further comprising forming the enclosure to include a contact structure having electrical contacts for coupling the microelectronic package to other components.
99-107. (canceled)
108. A microelectronic device package formed by a process that comprises:
- forming first and second microelectronic device features at least proximate to a surface of a microelectronic substrate;
- coupling a conductive link between the first and second microelectronic device features of the microelectronic substrate;
- removing a sacrificial material adjacent to the conductive link to suspend at least a portion of the conductive link between two points;
- disposing an enclosure around the microelectronic substrate;
- placing the microelectronic substrate, the conductive link and the enclosure in an elevated pressure environment having a gas that includes hydrogen and/or helium at a pressure of from about 5 to about 50 atmospheres above atmospheric pressure while an interior of the enclosure remains in fluid communication with the elevated pressure environment;
- sealing the gas within the enclosure and in thermal contact with the conductive link;
- removing the microelectronic substrate, the conductive link and the enclosure as a unit from the elevated pressure environment and exposing the enclosure to atmospheric pressure.
109. The package of claim 108, wherein the process further comprises forming at least a portion of the enclosure simultaneously with forming the conductive link by:
- disposing the sacrificial material on the microelectronic substrate;
- forming first and second voids in the sacrificial material with the first void corresponding to a portion of the enclosure and the second void corresponding to the conductive link; and
- filling the first and second voids to simultaneously form the portion of the enclosure and the conductive link.
110. A method for manufacturing a microelectronic device package, comprising:
- forming at least one microelectronic device feature at least proximate to a surface of a microelectronic substrate;
- electrically coupling the at least one microelectronic device feature to a first bond site;
- engaging the microelectronic substrate with a support substrate having a second bond site;
- coupling a conductive link between the first bond site and the second bond site;
- disposing an enclosure around at least a portion of the microelectronic substrate;
- sealing a gas within the enclosure and in contact with the conductive link with the gas at a pressure at least one atmosphere above atmospheric pressure; and
- exposing the enclosure to atmospheric pressure while the gas remains sealed within the enclosure.
111. The method of claim 110 wherein sealing a gas includes sealing a gas at a pressure of from about 5 atmospheres to about 50 atmospheres above atmospheric pressure.
112. The method of claim 110, further comprising:
- placing the microelectronic substrate, the enclosure and the conductive link in an elevated pressure environment having a pressure at least one atmosphere greater than atmospheric pressure while the enclosure remains open to the elevated pressure environment;
- sealing the enclosure while the enclosure remains in the elevated pressure environment; and
- removing the enclosure, the microelectronic substrate and the conductive link as a unit from the elevated pressure environment.
113. The method of claim 110 wherein coupling the conductive link includes connecting a wire bond between the first bond site and the second bond site.
114. The method of claim 110 wherein coupling the conductive link includes connecting a solder ball between the first bond site and the second bond site.
115. The method of claim 110, further comprising sealably attaching the enclosure to the support substrate.
116. The method of claim 110 wherein the conductive link is a first conductive link and the microelectronic device feature is a first microelectronic device feature, and wherein the method further comprises coupling a second conductive link between the first and second microelectronic device features.
117. The method of claim 110 wherein the conductive link is a first conductive link and the microelectronic device feature is a first microelectronic device feature, and wherein the method further comprises coupling a second conductive link between the first and second microelectronic device features, with at least a portion of the second conductive link between the first and second microelectronic device features being suspended between a first point and a second point.
118. The method of claim 110, further comprising selecting the enclosure to include a metallic material.
119. The method of claim 110 wherein the enclosure is a first enclosure and wherein the method further comprises disposing a second enclosure within the first enclosure and adjacent to the microelectronic substrate.
120. The method of claim 110 wherein the enclosure is a first enclosure, the conductive link is a first conductive link, and the at least one microelectronic device feature includes a first microelectronic device feature, and wherein the microelectronic substrate has a second microelectronic device features, and wherein the method further comprises:
- coupling a second conductive link between the first and second microelectronic device features;
- disposing a second enclosure adjacent to the microelectronic substrate before disposing the first enclosure, the second enclosure having the first bond site positioned within the first enclosure; and
- providing fluid communication between an interior region of the first enclosure and an interior region of the second enclosure to place the interior regions of the first and second enclosures at approximately the same pressure.
121. A method for manufacturing a microelectronic device package, comprising:
- forming microelectronic device features in a microelectronic substrate;
- forming a sacrificial support structure by depositing a first polymer material on a surface of the microelectronic substrate, depositing a first oxide layer on the first polymer material, depositing a second polymer material on the first oxide and depositing a second oxide layer on the second polymer material;
- selectively masking portions of the second oxide layer and selectively removing portions of the second oxide layer and the second polymer material to form first voids corresponding to locations of an external wall of the package and simultaneously form second voids corresponding to conductive links extending in a direction aligned with the surface of the microelectronic substrate;
- selectively masking portions of the first oxide layer and selectively removing portions of the first oxide layer and the first polymer material to form third voids coupled to the first voids and simultaneously form fourth voids coupled to the second voids and extending in a direction transverse to the surface of the microelectronic substrate;
- disposing a conductive material in the first and third voids to form a conductive link and simultaneously disposing the conductive material in the second and fourth voids to form a conductive external wall portion for the package;
- planarizing the package to remove a portion of the conductive material; and
- removing the sacrificial support structure adjacent to the conductive link to suspend a portion of the conductive link between two points.
122. The method of claim 121, further comprising selecting the oxide to include silicon dioxide.
123. The method of claim 121 wherein removing the sacrificial support structure includes exposing the structure to a plasma.
124. The method of claim 121, further comprising selecting the sacrificial material to include at least one of a polyimide and a photoresist material.
125. The method of claim 121, further comprising selecting a material of the external wall portion and the conductive link to include at least one of copper and aluminum.
126. The method of claim 121 wherein the external wall portion is a first external wall portion and the conductive link is a first conductive link, and wherein the method further comprises:
- simultaneously forming a second external wall portion of the package above the first external wall portion and a second conductive link above the first conductive link, the second external wall portion attached to the first external wall portion; and
- removing material adjacent to the second conductive link simultaneously with removing material adjacent to the first conductive link to suspend at least a portion of the second conductive link.
127. The method of claim 121, further comprising forming an internal heat transfer member inward from the external wall of the package and simultaneously with forming the external wall portion of the package.
Type: Application
Filed: May 23, 2005
Publication Date: Sep 29, 2005
Inventors: Jerome Eldridge (Los Gatos, CA), Paul Farrar (South Burlington, VT)
Application Number: 11/134,987