Patents by Inventor Yee-Chia Yeo

Yee-Chia Yeo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384437
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
  • Publication number: 20220384436
    Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220367215
    Abstract: A method of forming a semiconductor device includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. A push pin is extended through the first wafer chuck to distort the first wafer. A surface profile distortion of the first wafer is measured with a first surface profiler. A vacuum pressure of a vacuum zone on the first wafer chuck is adjusted using a measurement of the surface profile distortion. The first wafer chuck is moved towards the second wafer chuck so that the first wafer physically contacts the second wafer, and the first wafer is bonded to the second wafer.
    Type: Application
    Filed: November 22, 2021
    Publication date: November 17, 2022
    Inventors: Chieh Chang, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220367690
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Publication number: 20220367686
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.
    Type: Application
    Filed: November 18, 2021
    Publication date: November 17, 2022
    Inventors: Yu-Chang Lin, Liang-Yin Chen, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220367249
    Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 17, 2022
    Inventors: Chieh Chang, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220367410
    Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.
    Type: Application
    Filed: October 8, 2021
    Publication date: November 17, 2022
    Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
  • Publication number: 20220367717
    Abstract: A device includes a fin extending from a substrate; a gate stack over and along sidewalls of the fin; a gate spacer along a sidewall of the gate stack; an epitaxial source/drain region in the fin and adjacent the gate spacer, the epitaxial source/drain region including a first epitaxial layer on the fin, the first epitaxial layer including silicon and arsenic; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin; and a contact plug on the second epitaxial layer.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Li-Li Su, Wei-Min Liu, Wei Hao Lu, Chien-I Kuo, Yee-Chia Yeo
  • Publication number: 20220367625
    Abstract: In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.
    Type: Application
    Filed: December 30, 2021
    Publication date: November 17, 2022
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Patent number: 11502000
    Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220359311
    Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 10, 2022
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220359369
    Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 10, 2022
    Inventors: Chen-Fong Tsai, Cheng-I Chu, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220359742
    Abstract: A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Publication number: 20220359755
    Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jiang, Meng-Han Chou
  • Publication number: 20220359286
    Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220359653
    Abstract: A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.
    Type: Application
    Filed: December 14, 2021
    Publication date: November 10, 2022
    Inventors: Wei-Min Liu, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20220359517
    Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.
    Type: Application
    Filed: July 9, 2021
    Publication date: November 10, 2022
    Inventors: Po-Kang Ho, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220359301
    Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220359679
    Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.
    Type: Application
    Filed: December 21, 2021
    Publication date: November 10, 2022
    Inventors: Wei Hao Lu, Li-Li Su, Chien-I Kuo, Yee-Chia Yeo, Wei-Yang Lee, Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20220352321
    Abstract: A method of forming a semiconductor device includes implanting dopants of a first conductivity type into a semiconductor substrate to form a first well, epitaxially growing a channel layer over the semiconductor substrate, forming a fin from the second semiconductor material, and forming a gate structure over a channel region of the fin. The semiconductor substrate includes a first semiconductor material. Implanting the dopants may be performed at a temperature in a range of 150° C. to 500° C. The channel layer may include a second semiconductor material. The channel layer may be doped with dopants of the first conductivity type.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 3, 2022
    Inventors: Bau-Ming Wang, Che-Fu Chiu, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo