Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

Abstract: A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10?2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

Abstract: A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a liner layer and an isolation structure surrounding the fin structure. The structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. The structure also includes a gate structure formed over the gate dielectric layer. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The fin structure includes a protruding portion laterally extending over the liner layer.

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

Abstract: A method includes forming a plurality of semiconductor regions on a wafer, placing the wafer in an etching chamber, globally heating the wafer using a heating source, and projecting a laser beam on the wafer. When the wafer is heated by both of the heating source and the laser beam, the plurality of semiconductor regions on the wafer are etched.

Abstract: The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.

Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.