Semiconductor device and method of manufacturing same
A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.
1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device comprising a metal oxide semiconductor (MOS) transistor and a method of manufacturing the same.
A claim of priority is made to Korean Patent Application No. 10-2004-0049004 filed on Jun. 28, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Fully depleted silicon-on-insulator (FD-SOI) technology has been widely used to create high speed, low power logic circuits. Using FD-SOI technology reduces parasitic capacitances associated with source, drain, and channel regions of semiconductor circuits, thereby allowing the circuits to operate at higher speeds. In addition, FD-SOI technology reduces the amount of leakage current occurring at source and drain junctions of the circuits, thereby lowering associated power consumption. Furthermore, shallow source/drain regions are readily implemented using FD-SOI technology, thus allowing the short channel effect to be readily constrained and thereby improving the scalability of the circuits.
Unfortunately, however, a substrate floating effect may occur in MOS transistors formed on an SOI substrate where an element in a channel region assumes a floating state electric potential. Furthermore, where a buried oxide layer (BOX) is formed below a silicon substrate, a self-heating problem often occurs in devices formed on the silicon layer. As a result, the range of applications where SOI technology can be used is restricted by the kinds of circuits to be formed.
As complementary metal-oxide semiconductor (CMOS) technology has continued to shrink in size, a variety of attempts to improve the performance of transistors with short channel lengths have been made. Among these attempts, a mechanical stress engineering technique has been proposed. According to the mechanical stress engineering technique, a local stress is applied to a channel region so as to control the carrier (electron or hole) mobility (μ) within a semiconductor material. Where the carrier mobility increases, the switching characteristics of the device are improved, thus enabling the manufacture of higher-speed devices.
Unfortunately, it is difficult to apply local stress to SOI devices because the silicon layer formed on the buried oxide layer (BOX) is too thin. In addition, cost poses an obstacle to the manufacture of devices using SOI technology because SOI wafers are extremely expensive.
SUMMARY OF THE INVENTIONThe present invention provides a semiconductor device capable of improving carrier mobility by applying a local stress to a channel region while maintaining advantages of an SOI device, such as the ability to constrain short channel effects and reduce junction resistance.
In addition, the present invention provides a method of manufacturing a semiconductor device in which a highly integrated semiconductor device having an improved short channel effect and reduced junction capacitance, as well as a device being capable of constraining a substrate floating effect may be implemented at a relatively low cost.
According to one embodiment of the present invention, a semiconductor device is provided. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on both sides of the gate electrode within the active region.
According to another embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method comprises forming a gate electrode on a semiconductor substrate, forming spaces in an active region below the gate electrode, forming a channel region between the gate electrode and the spaces, and forming source and gate regions on both sides of the gate electrode within the active region.
According to the present invention, the short channel effect is constrained and junction resistance is reduced by forming the spaces in the active region below the gate electrode. Furthermore, it effectively addresses the substrate floating effect which occurs in devices using SOI technology. Furthermore, the invention makes it possible to implement the mechanical stress engineering technique to the channel region to increase carrier mobility.
BRIEF DESCRIPTION OF THE DRAWINGSThe invention is described below in relation to several embodiments illustrated in the accompanying drawings. Throughout the drawings like reference numbers indicate like exemplary elements, components, or steps and the thickness of various layers has been exaggerated for clarity. In the drawings:
Exemplary embodiments of the invention are described below with reference to the corresponding drawings. These embodiments are presented as teaching examples. The actual scope of the invention is defined by the claims that follow.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Semiconductor layer 134 is formed to a thickness sufficient to completely fill recess region 120. As shown in
Referring to
Referring to
Referring to
Referring to
Referring to
Source and drain regions 158 are then formed in semiconductor layer 134 and Si layer 104. Source and drain regions 158 are typically formed using a conventional ion implantation process using hard mask 116 and third insulating spacers 156 as an ion implantation mask.
Referring to
According to selected embodiments of the present invention, spaces 140 are extended to completely overlap the channel region and source and drain regions 158. Accordingly, as in the case where a SOI substrate is used, the short channel effect is readily constrained and junction capacitance is reduced.
The embodiment illustrated in
Referring to
Referring to
Referring to
According to selected embodiments of the present invention, insulating layer 240 is extended to completely overlap the channel region and source and drain regions 158. Accordingly, as in the case where a SOI substrate is used, the short channel effect is readily constrained and junction capacitance is reduced.
The method illustrated in
Referring to
Referring to
Referring to
According to selected embodiments of the present invention, spaces 340 are extended to completely overlap the channel region and to partially overlap source and drain regions 158. In other words, spaces 340 formed in the active region below gate electrode 114 are extended cover only a portion of the active region. A portion of second SiGe layer 132 adjacent to second insulating spacers 122 still remains between semiconductor substrate 100 and semiconductor layer 134. Accordingly, the length of spaces 340 is limited by the portion of second SiGe layer 132 remaining between semiconductor substrate 100 and source and drain regions 158. Due to second SiGe layer 132, a substrate floating effect is prevented from occurring in a MOS transistor.
The method illustrated in
Referring to
Referring to
Referring to
The method illustrated in
Referring to
Semiconductor layer 534 is formed to a thickness sufficient to fill recess region 120. As shown in
Referring to
Referring to
Referring to
Referring to
The method illustrated in
Referring to
Referring to
Referring to
According to the present invention, the short channel effect is constrained and junction resistance is reduced by forming spaces in the active region below the gate electrode of a MOS transistor. In addition, the present invention avoids the problem of the substrate floating effect that occurs in the SOI substrate. Further, it is possible to implement the technique whereby local stress is applied to the channel region. Accordingly, where the present invention is applied to the manufacture of very large scale integrated semiconductor devices, the performance of the device is improved by employing a structure which increases carrier mobility. In addition, the highly-integrated semiconductor devices can be manufactured at a low cost relative to those using SOI technology.
The exemplary embodiments of the present invention described herein are teaching examples. Those of ordinary skill will understand that various changes in form and details may be made thereto without departing from the scope of the present invention as defined by the following claims.
Claims
1. A semiconductor device, comprising:
- a gate electrode formed on a semiconductor substrate;
- an active region comprising spaces formed below the gate electrode;
- a channel region formed between the gate electrode and the spaces; and,
- source and drain regions respectively formed within the active region on opposite sides of the gate electrode.
2. The semiconductor device of claim 1, wherein the channel region comprises a silicon (Si) layer; and,
- wherein the source and drain regions are formed of a Si layer, a silicon carbide (SiC) layer, or a silicon germanium (SiGe) layer.
3. The semiconductor device of claim 1, wherein the spaces extend to completely overlap the channel region and at least one of the source and drain regions.
4. The semiconductor device of claim 1, wherein the spaces extend to completely overlap the channel region, and at least partially overlap at least one of the source and drain regions.
5. The semiconductor device of claim 4, further comprising:
- a semiconductor layer formed between the semiconductor substrate and the source and drain regions to define a length of the spaces.
6. The semiconductor device of claim 5, wherein the semiconductor layer comprises a SiGe layer.
7. The semiconductor device of claim 1, further comprising an insulating layer filling the spaces.
8. The semiconductor device of claim 7, wherein the insulating layer is formed of an oxide layer or a nitride layer.
9. A method of manufacturing a semiconductor device, comprising:
- forming a first silicon germanium (SiGe) layer formed on a bulk semiconductor substrate;
- forming a silicon (Si) layer on the first SiGe layer;
- defining an active region on the semiconductor substrate;
- sequentially forming a gate insulating layer and a gate electrode on the Si layer;
- selectively removing portions of the Si layer and the first SiGe layer to form a recess region exposing the semiconductor substrate, the recess region being formed in the active region near the gate electrode;
- forming a semiconductor layer within the recess region;
- selectively removing the first SiGe layer to form spaces below the Si layer in the active region;
- epitaxially growing Si, such that the Si layer and the semiconductor layer are joined; and,
- forming source and drain regions in the semiconductor layer.
10. The method of claim 9, wherein the semiconductor layer comprises:
- a first semiconductor layer formed from a second SiGe layer, and a second semiconductor layer formed from a Si layer or a SiC layer.
11. The method of claim 10, wherein Ge concentration in the second SiGe layer is substantially equal to Ge concentration in the first SiGe layer.
12. The method of claim 10, wherein the first semiconductor layer is selectively and simultaneously removed with the selective removal of the first SiGe layer; and
- wherein the spaces extended from a lower portion of the Si layer to a lower portion of the second semiconductor layer.
13. The method of claim 12, wherein the first semiconductor layer is completely and simultaneously removed.
14. The method of claim 12, wherein the first semiconductor layer is partially simultaneously removed.
15. The method of claim 9, wherein the semiconductor layer is formed from a single layer comprising a Si layer, a SiC layer, or a SiGe layer.
16. The method of claim 15, wherein the semiconductor layer is not removed with the first SiGe layer.
17. The method of claim 9, wherein the spaces are formed only below the Si layer.
18. The method of claim 15, wherein the semiconductor layer is formed from a SiGe layer having a concentration of Ge which is lower than a concentration of Ge in the first SiGe layer.
19. The method of claim 9, further comprising:
- forming an insulating layer to fill the spaces.
20. The method of claim 19, wherein the insulating layer is formed from an oxide layer or a nitride layer.
21. A method of manufacturing a semiconductor device, comprising:
- forming a gate electrode on a semiconductor substrate;
- forming spaces in an active region below the gate electrode;
- forming a channel region between the gate electrode and the spaces; and,
- forming source and gate regions on opposite sides of the gate electrode within the active region.
Type: Application
Filed: Mar 17, 2005
Publication Date: Dec 29, 2005
Inventors: Sung-young Lee (Suwon-si), Dong-suk Shin (Yongin-si)
Application Number: 11/081,538