Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

Abstract: An apparatus includes a transistor and a controller. The transistor has a first terminal, a second terminal, and a control terminal. The controller has an output coupled to the control terminal of the transistor, and an input coupled to the second terminal of the transistor. The controller is capable of turning the transistor on responsive to an enable signal. The controller is also capable of comparing a voltage at the input of the controller to a threshold. The controller is further capable of, responsive to a result of the comparing, either latching the transistor off or turning the transistor off for a time and then turning the transistor back on.

Abstract: An apparatus includes a strain gauge and an analog-to-digital converter (ADC). The strain gauge includes a first resistor and a second resistor. The first resistor has a first terminal coupled to a power supply terminal and a second terminal. The second resistor has a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a reference terminal. The ADC has a signal input coupled to the second terminal of the first resistor, and a reference input coupled to the power supply terminal.

Abstract: A circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a collector, an emitter, and a base. The second transistor has a collector coupled to the emitter of the first transistor, an emitter coupled to the collector of the first transistor, and a base. The third transistor has a first terminal coupled to the base of the first transistor and a second terminal coupled to the collector of the first transistor and to the emitter of the second transistor. The fourth transistor has a first terminal coupled to the base of the second transistor and a second terminal coupled to the collector of the second transistor and to the emitter of the first transistor.

Abstract: An integrated circuit comprises a transistor extending into a semiconductor substrate and having a gate structure having major and minor axes parallel to a surface of the semiconductor substrate, and a UV-opaque sheet structure vertically spaced apart from a top surface of the gate structure by a first distance and including an opening, the opening having first and second sides about parallel to the major axis, at least one of the first and second sides laterally spaced apart from a corresponding side of the gate structure by a second distance that is less than or equal to the first distance.

Abstract: An example apparatus includes a buffer configured to, when enabled: obtain an input voltage; and provide the input voltage to a first boundary cell; and a second boundary cell configured to, when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

Abstract: A method for encoding a picture of a video sequence in a bit stream that reduces slice header parsing overhead is provided. The method includes determining weighting factors that may be used for weighted prediction in encoding at least one slice of the picture, wherein a total number of the weighting factors is constrained to not exceed a predetermined threshold number of weighting factors, wherein the threshold number is less than a maximum possible number of weighting factors, and signaling weighted prediction parameters including the weighting factors in a slice header in the bit stream.

Abstract: Systems and methods for controlling a charge pump current in response to a control voltage provided to a voltage-controlled oscillator (VCO) are disclosed. An example system includes a phase-locked loop including a charge pump and a VCO coupled to the charge pump. Current adjusting circuitry receives the control voltage and controls the charge pump current. The current adjusting circuitry is configurable to cause the charge pump current to increase by a first amount responsive to the control voltage being in a first range, and cause the charge pump current to decrease by a second amount responsive to the control voltage being in a second range. A chirp signal output by the phase-locked loop has a bandwidth defined by a first bandwidth segment that corresponds to the control voltage being in the first range and a second bandwidth segment that corresponds to the control voltage being in the second range.

Abstract: Non-transitory computer-readable mediums and systems are provided in which a portion of each chirp of a series of chirps is held at an offset frequency for a period of time, and in which the offset frequency, the period of time or both is varied or dithered across the chirps of the series of chirps. The portion of a chirp that is held at an offset frequency for a period of time may be a non-active portion of the chirp, during which the chirp is not sampled. In some implementations, the portion of a chirp that is held at an offset frequency for a period of time is during a falling portion of the chirp, which may be at the beginning of the falling portion, or at the end of the falling portion immediately before a rise portion of a succeeding chirp.

Abstract: A communication circuit includes network formation circuitry configured to establish a wireless network between a primary wireless transceiver and a secondary wireless transceiver. The communication circuit also includes data transfer circuitry configured to perform data transfers between the primary wireless transceiver and the secondary wireless transceiver. The communication circuit further includes resynchronization circuitry configured to resynchronize the secondary wireless transceiver with the established wireless network within a target time interval.

Abstract: Virtual boundary processing in adaptive loop filtering (ALF) requires that padded values be substituted for unavailable pixel rows outside the virtual boundaries. Methods and apparatus are provided for virtual boundary processing in ALF that allow the use of more actual pixel values for padding than in the prior art.

Abstract: Various systems and methods are provided. One such system includes first and second inputs of first and second types, respectively; a data controller, including a context mapper coupled to the first and second inputs. The data controller includes a context mapper that provides a processing identifier and a storage identifier to each item of data received from the first and second inputs; and a set of processing components, each coupled to the context mapper, and each associated with a respective processing identifier for processing each item of data having the corresponding processing identifier. The system further includes a memory coupled to the context mapper, the memory having multiple storage locations each associated with a respective storage identifier for storing each item of data having the corresponding storage identifier; and first and second outputs of the first and second types, respectively, coupled to the data controller.

Abstract: In one example embodiment, a technique for performing a data integrity process is provided. The technique first includes accessing address data stored in a first location in memory such that the address data is indicative of a second location in memory. The technique then includes accessing data stored in the second location in memory and generating a data integrity value based on the accessed data. Once generated, the technique includes performing a comparison between the data integrity value and a reference value associated with the accessed data. If the comparison shows the data integrity value matches the reference value, then the technique includes outputting a positive indication. Else, the technique includes outputting a negative indication.

Abstract: In some examples, a device includes a substrate, an oxide layer, and a resonator structure. The substrate is configured in a released-resonator architecture. The substrate has a first surface that is a roughened first surface and a second surface opposite to the first surface. The second surface exposed to a cavity of the released-resonator architecture.

Abstract: A system includes a battery pack having a first battery module, a second battery module, and a busbar that couples the first and second battery modules; a battery management controller having a first wireless transceiver; and a battery monitor coupled to the first battery module and to the busbar. The battery monitor includes monitoring circuitry configured to receive a first indication of a parameter of the first battery module; a second wireless transceiver configured to provide the first indication to the battery management controller via a wireless connection to the first wireless transceiver; and a busbar voltage circuit configured to receive a second indication of a voltage across the busbar, and, responsive to the second indication being greater than a voltage threshold, provide a first signal to the second wireless transceiver to cause the second wireless transceiver to be in a higher-power state.

Abstract: A system for decoding a scalable bitstream is provided that includes a receiver for receiving a bit stream including a coded representation of a picture. The system also includes a decoder for decoding a first syntax element in the bit stream, where the first syntax element specifies a number of layers including a first layer. The decoder can also decode a second syntax element in the bit stream, where the second syntax element specifies a buffer size when the first layer is not a target layer.

Abstract: A power converter includes an isolator having a first terminal, a second terminal, a third terminal, and a fourth terminal. A first circuit has a first terminal coupled to the first terminal of the isolator and has a second terminal coupled to the second terminal of the isolator. A second circuit has a first terminal coupled to the third terminal of the isolator and has a second terminal coupled to the fourth terminal of the isolator. The second circuit includes a controller configured to transmit a control signal through the isolator to the first circuit. The control signal includes a first indication to turn on power transmission through the isolator from the first circuit to the second circuit, a second indication of a status, and a third indication to turn off power transmission.

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Abstract: An integrated circuit is provided which comprises a transistor and a driver coupled to a gate of the transistor. In at least one example, the driver controls an operation of the transistor, wherein the driver is operable in a first configuration as a low-side gate driver for a voltage regulator, and wherein the transistor is operable in the first configuration as a low-side switch for the voltage regulator. In at least one example, the driver is operable in a second configuration as a high-side gate driver for the voltage regulator, and wherein the transistor is operable in the second configuration as a high-side switch for the voltage regulator.