Patents Assigned to Texas Instruments Incorporated
  • Patent number: 11915431
    Abstract: A method for sparse optical flow based tracking in a computer vision system is provided that includes detecting feature points in a frame captured by a monocular camera in the computer vision system to generate a plurality of detected feature points, generating a binary image indicating locations of the detected feature points with a bit value of one, wherein all other locations in the binary image have a bit value of zero, generating another binary image indicating neighborhoods of currently tracked points, wherein locations of the neighborhoods in the binary image have a bit value of zero and all other locations in the binary image have a bit value of one, and performing a binary AND of the two binary images to generate another binary image, wherein locations in the binary image having a bit value of one indicate new feature points detected in the frame.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Deepak Kumar Poddar, Anshu Jain, Desappan Kumar, Pramod Kumar Swami
  • Patent number: 11915117
    Abstract: A method for convolution in a convolutional neural network (CNN) is provided that includes accessing a coefficient value of a filter corresponding to an input feature map of a convolution layer of the CNN, and performing a block multiply accumulation operation on a block of data elements of the input feature map, the block of data elements corresponding to the coefficient value, wherein, for each data element of the block of data elements, a value of the data element is multiplied by the coefficient value and a result of the multiply is added to a corresponding data element in a corresponding output block of data elements comprised in an output feature map.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Manu Mathew, Kumar Desappan, Pramod Kumar Swami
  • Patent number: 11914411
    Abstract: A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Shylaja Krishnan, Tallam Vishwanath, Akshay Yashwant Jadhav
  • Patent number: 11914412
    Abstract: In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sanjeev Praphulla Chandra Nyshadham, Subrato Roy
  • Patent number: 11916426
    Abstract: A system includes: a switching converter circuit adapted to be coupled between an input voltage source and a load; and an integrated circuit adapted to be coupled between the input voltage source and a battery and configured to charge the battery. The integrated circuit has: a monitoring circuitry adapted to be coupled to the battery and configured to detect a transient fault condition of the integrated circuit; a power stage adapted to be coupled between the input voltage source and the battery, the power stage having a power switch; and a control circuit coupled between the monitoring circuitry and the power stage, the control circuit configured to provide a control signal to adjust a conductivity of the power switch responsive to a detected transient fault condition.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hakan Oner, Kevin Scoones
  • Patent number: 11916495
    Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Hrishikesh Ratnakar Nene, Salil Chellappan, Zhong Ye
  • Patent number: 11915442
    Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Patent number: 11916142
    Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Ming-Yeh Chuang
  • Patent number: 11916152
    Abstract: A semiconductor device includes a Schottky diode on a silicon-on-insulator (SOI) substrate. The Schottky diode includes a guard ring with a first guard ring segment contacting a barrier region on a first lateral side of the barrier region, and a second guard ring segment contacting the barrier region on a second, opposite, lateral side of the barrier region. The first and second guard ring segments extend deeper in the semiconductor layer than the barrier region. The Schottky diode further includes a drift region contacting the barrier region, and may include a buried layer having the same conductivity type as the barrier region, extending at least partway under the drift region. The barrier region is isolated from the substrate dielectric layer of the SOI substrate by an isolation region having the same conductivity type as the guard ring. A metal containing layer is formed on the barrier region.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Zachary K. Lee
  • Patent number: 11916486
    Abstract: A compensation circuit includes a tail current source, an error amplifier; a compensation resistor, and a voltage-to-current converter circuit. The tail current source is configured to generate a tail current. The error amplifier is coupled to the tail current source and biased by the tail current. The compensation resistor is coupled to the error amplifier. The voltage-to-current converter circuit is coupled to the error amplifier. The compensation resistor is configured to vary in resistance responsive to a change in the tail current, or the voltage-to-current converter circuit is configured to vary in transconductance responsive to the change in the tail current.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Anmol Sharma
  • Patent number: 11914410
    Abstract: Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajat Chauhan
  • Patent number: 11914545
    Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Andreas Waechter, Mark Jung, Steven Craig Bartling, Sudhanshu Khanna
  • Patent number: 11916479
    Abstract: A system includes: 1) a battery configured to provide an input voltage (VIN); 2) switching converter circuitry coupled to the battery, wherein the switching converter circuitry includes a power switch; 3) a load coupled to an output of the switching converter circuitry; and 4) a control circuit coupled to the power switch. The control circuit includes: 1) a switch driver circuit coupled to the power switch; 2) a summing comparator circuit configured to output a first control signal that indicates when to turn the power switch on; and 3) an analog on-time extension circuit configured to extend an on-time of the power switch by gating a second control signal with the first control signal, wherein the second control signal indicates when to turn the power switch off.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zejing Wang, Zhujun Li, Songming Zhou, Yu Wang
  • Patent number: 11916516
    Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Kunal Karanjkar, Venkata Ramanan
  • Patent number: 11916496
    Abstract: A motor controller is operable to control a motor. The motor has a first terminal and the motor controller includes an angular velocity transmission path having an input and an output. A current generator includes a velocity-torque input, an angular position input, and a motor drive output. The velocity-torque input is coupled to the output of the angular velocity transmission path. An angular velocity feedback path is coupled between a first terminal and a first location on the angular velocity transmission path. The first location is between the input and the output of the angular velocity transmission path. A current feedback path is coupled between the first terminal and a second location on the angular velocity transmission path. The second location is disposed between the first location on the angular velocity transmission path and the velocity-torque input of the current generator.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prasad Kulkarni, Venkata Pavan Mahankali
  • Patent number: 11916555
    Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arnab Khawas, Badarish Subbannavar, Gokul Sabada
  • Patent number: 11916567
    Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sai Aditya Krishnaswamy Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Appala Pentakota, Shagun Dusad
  • Patent number: 11916062
    Abstract: A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Xianzhi Dai, Rajkumar Sankaralingam
  • Patent number: 11916570
    Abstract: The present disclosure generally relates to a codeword format for data storage and to methods and circuits for generating a codeword based on data to be written in memory and extracting data from a codeword read from memory. In an example, an integrated circuit includes a memory system and a controller circuit. The controller circuit is communicatively coupled to the memory system and is configured to: receive multi-bit data; generate a codeword based on the multi-bit data; and transmit to the memory system the codeword for writing to memory. The codeword has a format that includes first bit positions for the multi-bit data, second bit positions for a bitwise inversion of the multi-bit data, a third bit position for an odd parity value, and a fourth bit position for an even parity value. The odd and even parity values indicate an odd and even parity, respectively, of the multi-bit data.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Dominik Stefan Gerl, Annabelle Arnold
  • Patent number: 11916067
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee