Patents Assigned to Texas Instruments Incorporated
  • Publication number: 20220149186
    Abstract: A semiconductor device including a substrate having a semiconductor layer containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A drain-tied field plate on the field relief dielectric, the drain-tied field plate extending from the drain region toward the gate with an electrical connection between the drain-tied field plate and the drain region.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Gang Xue
  • Patent number: 11329693
    Abstract: An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second transceiver capable of a bi-directional communication session on a second communication medium; and a control logic coupled to the first transceiver and the second transceiver and capable of implementing a convergence layer, wherein the control logic is configured to receive, from the first transceiver, a first signal; and cause, in response to the first signal, data received and transmitted by the first transceiver on the first communication medium as part of a communication session to be received and transmitted instead by the second transceiver on the second communication medium.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yanjun Sun, Gang Xu, Soon-Hyeok Choi, Bhadra Sandeep, Xiaolin Lu, Ariton E. Xhafa, Minghua Fu, Robert W. Liang, Susan Yim
  • Patent number: 11329687
    Abstract: A system includes: a host processor; a transceiver coupled to the host processor; and a power amplifier coupled to an output of the transceiver. The transceiver includes a transmit chain with digital pre-distortion (DPD) logic configured to: perform DPD correction operations on transmit data received by the transmit chain; and output corrected transmit data based on the performed DPD correction operations, wherein the output corrected transmit data is provided to the power amplifier.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Francesco Dantoni, Jawaharlal Tangudu, Sarma Sundareswara Gunturi, Robert Clair Keller
  • Patent number: 11329025
    Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vivek Arora, Woochan Kim
  • Patent number: 11327328
    Abstract: Described examples include a beam spreader having a first beam splitter arranged to receive light from a light source, the first beam splitter arranged to pass a first portion of the light in a first direction and reflect a second portion of the light; a second beam splitter arranged to receive the second portion of the light and reflect a third portion of the light in a second direction parallel to the first direction and arranged to pass a fourth portion of the light; and a mirror arranged to receive the fourth portion of the light and reflect the fourth portion of the light in a third direction parallel to the first direction, wherein the third portion and the fourth portion of the light reflected from the mirror is separated from the first portion of the light in the spreading direction.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Alexander Lyubarsky
  • Patent number: 11329844
    Abstract: In described examples, a circuit is adapted to receive an input signal at a local port or a first system port. A transceiver is configured to enter a first mode in response to a local wakeup signal and is configured to transmit a system wakeup signal at a second system port in response to the local wakeup signal. A controller is configured to generate the local wakeup signal in response to an energy detected signal. An energy detector is coupled to the first system port and the local port and is configured to generate the energy detected signal in response to a detection of energy of one of the first system input signal and the local input signal received by the transceiver in the second mode.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vijaya Ceekala, Xin Liu
  • Patent number: 11327166
    Abstract: In the proposed low complexity technique a hierarchical approach is created. An initial FFT based detection and range estimation gives a coarse range estimate of a group of objects within the Rayleigh limit or with varying sizes resulting from widely varying reflection strengths. For each group of detected peaks, demodulate the input to near DC, filter out other peaks (or other object groups) and decimate the signal to reduce the data size. Then perform super-resolution methods on this limited data size. The resulting distance estimations provide distance relative to the coarse estimation from the FFT processing.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 10, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Murtaza Ali, Dan Wang, Muhammad Zubair Ikram
  • Patent number: 11329472
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over current protection. An example apparatus includes an output terminal; a voltage detection device coupled to a voltage detection input terminal and the output terminal and including a voltage detection output coupled to a logic gate first input terminal; a pulse extender coupled between a logic gate output and a selecting node; a multiplexer coupled to the selecting node and configured to be coupled to a first protection circuit, a second protection circuit, and a driver; and a switch coupled between an input terminal and the output terminal and including a switch gate terminal coupled to the driver.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subrato Roy, Ankur Chauhan, Vishal Gupta
  • Patent number: 11328984
    Abstract: Multi-die integrated circuit packages and methods of manufacturing the same are disclosed. An example integrated circuit package includes a first leadframe, a first die on a first side of the first leadframe, and a second die on a second side of the first leadframe opposite the first side. The example integrated circuit package further includes external second leadframe separate from the first leadframe.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: You Chye How, Huay Yann Tay, Franklin Santos Marcelino
  • Patent number: 11329661
    Abstract: A buffer circuit includes a first differential signal input, a second differential signal input, a first source follower circuit, and a second source follower circuit. The first source follower circuit includes a first signal output, and a first input transistor. The first input transistor is coupled to the first differential signal input, and is configured to drive the first signal output. The second source follower circuit includes a second signal output, a second input transistor, and a cascode transistor. The second input transistor is coupled to the second differential signal input, and is configured to drive the second signal output. The cascode transistor is coupled to the second input transistor and the first signal output, and is configured to compensate for non-linearity of the second input transistor based on an output signal provided at the first signal output.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jafar Sadique Kaviladath
  • Patent number: 11325154
    Abstract: For a resonator system such as a (haptic) LRA, a methodology for resonant frequency (F0) tracking/control with continuous resonator drive, based on estimating back-emf, including estimating resonator resistance based at least in part on the sensed resonator drive signals, with back-emf estimated based at least in part on the sensed resonator drive signals and the estimated resonator resistance. A phase difference is detected between the resonator drive signals, and the estimated back-emf signals, generating control for resonator drive frequency, which can be used to iteratively adjust the resonator drive frequency until phase coherent with the estimated back-emf signals (F0 lock), such as for driving the resonator at or near a resonant frequency. An amplitude control loop can be used to iteratively adjust resonator drive amplitude based on a difference between estimated back-emf and a target back-emf derived from a rated back-emf and the resonator frequency resonant frequency.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Supriyo Palit
  • Patent number: 11329677
    Abstract: A wireless wake-up receiver includes multiple signal chains each signal chain being coupled to continuously receive a signal from a respective antenna and to provide a respective detected pattern at a signal chain output. Each signal chain includes a first path having a mixer-first architecture and operates in a bandpass-mode using differential signals. The wireless wake-up receiver also includes a digital correlator operable to receive the respective detected patterns and to determine whether one of the respective detected patterns is equal to a desired pattern.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudipto Chakraborty, Jens Graul, Ram Pratap Aditham
  • Patent number: 11327761
    Abstract: An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mujibur Rahman, Timothy David Anderson, Joseph Zbiciak
  • Publication number: 20220140116
    Abstract: A semiconductor device includes a junction field effect transistor (JFET) on a silicon-on-insulator (SOI) substrate. The JFET includes a gate with a first gate segment contacting the channel on a first lateral side of the channel, and a second gate segment contacting the channel on a second, opposite, lateral side of the channel. The first gate segment and the second gate segment extend deeper in the semiconductor layer than the channel. The JFET further includes a drift region contacting the channel, and may include a buried layer having the same conductivity type as the channel, extending at least partway under the drift region.
    Type: Application
    Filed: November 2, 2020
    Publication date: May 5, 2022
    Applicant: Texas Instruments Incorporated
    Inventor: Zachary Ka Fai Lee
  • Publication number: 20220140087
    Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Qhalid RS Fareed, Dong Seup Lee, Nicholas S. Dellas
  • Publication number: 20220139907
    Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.
    Type: Application
    Filed: November 1, 2020
    Publication date: May 5, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Yanbiao Pan
  • Patent number: 11322610
    Abstract: A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sunglyong Kim, Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 11320478
    Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
  • Patent number: 11320488
    Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sundarrajan Rangachari, Saket Jalan
  • Patent number: 11323106
    Abstract: One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijit Kumar Das, Ryan Alexander Smith