Patents Assigned to Texas Instruments Incorporated
  • Patent number: 10270239
    Abstract: Disclosed examples include methods, integrated circuits and switch circuits including a driver circuit and a silicon transistor or other current source circuit coupled with a gallium nitride or other high electron mobility first transistor, where the driver operatives in a first mode to deliver a control voltage signal to the first transistor, and in a second mode in response to a detected overvoltage condition associated with the first transistor to control the current source circuit to conduct a sink current from the first transistor to affect a control voltage to at least partially turn on the first transistor.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Sandeep R. Bahl
  • Patent number: 10269898
    Abstract: A surrounded emitter bipolar device includes a substrate having a p-epitaxial (p-epi) layer thereon, and a p-base in the p-epi layer. A two dimensional (2D) array of p-base contacts (base units) include the p-base, wherein each base unit includes an outer dielectric structure surrounding an inner dielectric isolation ring. The inner dielectric isolation ring surrounds an n region (n+moat). A first portion of the n+moats are collector (C) units, and a second portion of the n+moats are emitter (E) units. Each of the E units is separated from a nearest neighbor E unit by a C unit.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Akram A. Salman
  • Patent number: 10270346
    Abstract: A multiphase power regulator includes a plurality of phases coupled in parallel to provide a load current as a combination of phase currents at an output voltage, each phase including at least one power transistor switched to provide a respective phase current based at least in part on a comparator output signal, and a current-sense low pass filter to sense the phase current. The regulator further includes a gm stage to generate the current set point voltage based at least in part on the output voltage, a comparator to compare a voltage from the current-sense low pass filters to the current set point voltage and a current set point adjustment circuit to provide an auxiliary control signal to decrease the current set point voltage responsive to a change in comparator output and then to increase the current set point voltage responsive to another change in comparator output.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Antonio Priego, Neil Gibson, Syed Wasif Mehdi
  • Patent number: 10270354
    Abstract: A synchronous rectifier controller integrated circuit. The synchronous rectifier controller integrated circuit comprises a continuous current mode (CCM) detection circuit configured to detect CCM operation based on sensing a voltage at a pre-defined point in a rectification cycle; a multiplexer having a first reference voltage signal input, a second reference voltage signal input, an output, and a selector input coupled to the CCM detection circuit; and a gate voltage driver circuit coupled to the output of the multiplexer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Bing Lu, Bharath Balaji Kannan
  • Patent number: 10266950
    Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona M. Eissa, Yousong Zhang, Mark Jenson
  • Patent number: 10270492
    Abstract: In accordance with disclosed embodiments, a first power line communication (PLC) device connected to a PLC network includes channel control logic that assigns a first channel of the PLC network for transmission on a power line of PLC data packets between the first PLC device and a second PLC device connected to the PLC network and assigns a second channel of the PLC network for transmission on the power line of PLC data packets between the first PLC device and the third PLC device connected to the PLC network. The PLC device includes a transceiver that receives and transmits PLC data packets on the PLC network and which operates as a bridge device that communicates on both the first and second channels to pass PLC data packets between the second PLC device and the third PLC device.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yanjun Sun, Minghua Fu, Xiaolin Lu
  • Patent number: 10269895
    Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 10267854
    Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10268901
    Abstract: An image processing system includes a processor and optical flow (OF) determination logic for quantifying relative motion of a feature present in a first frame of video and a second frame of video that provide at least one of temporally and spatially ordered images with respect to the two frames of video. The OF determination logic configures the processor to implement performing OF estimation between the first frame and second frame using a pyramidal block matching (PBM) method to generate an initial optical flow (OF) estimate at a base pyramid level having integer pixel resolution, and refining the initial OF estimate using at least one pass of a modified Lucas-Kanade (LK) method to provide a revised OF estimate having fractional pixel resolution.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hrushikesh Tukaram Garud, Manu Mathew, Soyeb Noormohammed Nagori
  • Patent number: 10267851
    Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10267852
    Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10270338
    Abstract: In some examples, a shunt regulator includes a plurality of selection pins configured to receive a digital signal. The shunt regulator also includes an internal reference voltage selection circuit coupled to the plurality of selection pins, the internal reference voltage selection circuit configured to select a first internal reference voltage of the shunt regulator based on the digital signal. The shunt regulator further includes a soft ramp control circuit coupled to the internal reference voltage selection circuit and to a soft ramp control pin that is configured to carry a second internal reference voltage, the soft ramp control circuit configured to compare the first and the second internal reference voltages to generate a soft ramp control output signal.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Kumar G. Santhosh, Xiadong Cai, Aditya Ambardar, Rahul Mishra
  • Patent number: 10267855
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Patent number: 10270336
    Abstract: A circuit includes a current sensor to sense a switching current flowing at input side of a switching DC-DC converter. An output capacitor filters an output voltage at an output side of the switching DC-DC converter. A feed-forward circuit passes a portion of the sensed switching current to a feedback path on the output side of the switching DC-DC converter simulating a changing effective series resistance (ESR) of the output capacitor to facilitate operating stability in the switching DC-DC converter.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Erick Omar Torres
  • Patent number: 10267856
    Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun
  • Patent number: 10268448
    Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Shailesh Ganapat Ghotgalkar
  • Publication number: 20190115835
    Abstract: Control circuits and methods to operate a switch of a DC-DC converter, including an output circuit to turn the switch off to control a peak inductor current in a given switching control cycle, and a modulation circuit to implement transition mode (TM) or continuous conduction mode (CCM) operation for a given switching control cycle by causing the output circuit to turn the switch on in response to an earlier one of a first signal, that represents an inductor current of the DC-DC converter, decreasing to a reference voltage that represents a zero crossing of the inductor current for the TM operation or the first signal decreasing to a valley reference signal that represents a non-zero value of the inductor current for the CCM operation.
    Type: Application
    Filed: June 19, 2018
    Publication date: April 18, 2019
    Applicant: Texas Instruments Incorporated
    Inventor: Isaac Cohen
  • Patent number: 10262957
    Abstract: An integrated circuit (IC) package includes an IC die and a wave channel that electrically couples the IC die to a solder ball array. The wave channel is configured to resonate at an operating frequency band of the IC die.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: April 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajen Manicon Murugan, Minhong Mi, Gary Paul Morrison, Jie Chen, Kenneth Robert Rhyner, Stanley Craig Beddingfield, Chittranjan Mohan Gupta, Django Earl Trombley
  • Patent number: 10262722
    Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: April 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prajkta Vyavahare, Rajat Chauhan, Siva Srinivas Kothamasu
  • Patent number: 10263638
    Abstract: To enable lossless compression, an auxiliary bitmap is used to provide side information about the graph bitmap. Each bit in the auxiliary bitmap represents a word in the graph bitmap. A zero bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is not transmitted. Therefore, it is set to the default value, ?, during decompression. This default value could be either an all-zeros word, or all-ones word depending on the BFS step. A one bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is transmitted.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mohamed Farouk Mansour