Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

Abstract: An example apparatus includes first interpolation circuitry; second interpolation circuitry; first frequency band envelope determination circuitry having an input coupled to the first interpolation circuitry, and having an output; second frequency band envelope determination circuitry having an input coupled to the second interpolation circuitry, and having an output; combiner circuitry having a first input coupled to the output of the first frequency band envelope determination circuitry, having a second input coupled to the output of the second frequency band envelope determination circuitry, and having an output; and signal monitor circuitry having an input coupled to the output of the combiner circuitry.

Abstract: A circuit includes an amplifier, a first transistor, a second transistor, and a third transistor. The amplifier has a first amplifier input coupled to a voltage reference terminal; a second amplifier input, and an amplifier output. The first transistor has a first terminal coupled to a power terminal, a second terminal coupled to the second amplifier input, a body terminal coupled to a reference terminal, and a control terminal coupled to the amplifier output. The second transistor has a first terminal coupled to the power terminal, a second terminal, a body terminal coupled to the second terminal of the second transistor, and a control terminal coupled to the amplifier output. The third transistor has a first terminal coupled to the second amplifier input, a second terminal coupled to the reference terminal, and a control terminal coupled to the second terminal of the second transistor.

Abstract: Techniques for a machine learning model including the steps of summing values of a set of non-binary input feature values with bias values of a first set of bias values to generate first summed values; binarizing the first summed values; receiving a set of binary weights; performing a convolution operation on the binarized summed values and the set of binary weights to generate convolved output feature values; summing feature values of the convolved output feature values with bias values of a second set of bias values and applying a scale value of a first set of scale values to generate a first set of normalized feature values; summing the first set of normalized feature values with the non-binary input feature values to generate second summed values; and outputting a set of output feature values based on the second summed normalized feature values and non-binary input feature values.

Abstract: A circuit includes a memory array including memory bit cells arranged in rows and columns. A row includes differential reference bit cells and single-ended bit cells, and the reference bit cells include a first set configured to store a first binary value and a second set configured to store a second binary value different from the first binary value. The circuit also includes a control module configured to generate a first reference current and to select the given row for a read operation. The circuit additionally includes an input/output module configured to compare a sensed current of a respective single-ended bit cell of the single-ended bit cells for the read operation to a second reference current. The second reference current is based on the first reference current and respective currents of the first set of reference bit cells and the second set of reference bit cells.

Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

Abstract: Systems and methods for updating firmware may include using wait states to reduce or eliminate polling by an executing firmware component. An example includes dedicated firmware update hardware logic components, including a firmware update processing unit that executes firmware update code. The firmware update code may be paused between request of a hardware event and completion of a hardware event and under control of one or more of the hardware logic components. Once a hardware event has been completed, a hardware logic component may determine completion and, in response, restart execution of the firmware update code.

Abstract: An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

Abstract: A control circuit for an inverter. The control circuit includes a first pulse width modulation (PWM) module configured to produce first and second complementary PWM signals, and a second PWM module configured to produce a third and fourth complementary PWM signals. PWM switching logic is coupled to the first and second PWM modules and is adapted to be coupled to a switch network. The switch network includes first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal. The PWM switching logic is configured to produce control signals for each of the first, second, third, and fourth switches in response to the first and second complementary PWM signals and to the third and fourth complementary PWM signals.

Abstract: Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.

Abstract: In one example, a method performed by electronic circuitry comprises: causing a transducer to transmit a first signal; receiving a second signal from the transducer; computing distances responsive to a time between the first and second signals; determining a vibration characteristic based on the distances; reading reference vibration characteristics from data in a memory; comparing the input vibration characteristic to the reference vibration characteristics; and responsive to the comparing, performing at least one of: providing a signal representing a status of the comparing; or updating the data in the memory.

Abstract: A bandgap current reference circuit includes a bandgap core circuit and an error amplifier. The bandgap core circuit is configured to generate a zero temperature coefficient bandgap current. The bandgap core circuit includes a bipolar transistor. The bipolar transistor is configured to pass a current that is proportional to absolute temperature (PTAT current). The error amplifier is coupled to the bandgap core circuit and includes a bipolar differential input pair. The bipolar differential input pair is configured to ensure that the PTAT current is flowing in the bipolar transistor.

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

Abstract: An example circuit includes a rising edge detection circuit including an input and an output. The circuit also includes a falling edge detection circuit including an input and an output. The circuit also includes a power supply compensation circuit including a first input coupled to the output of the rising edge detection circuit and a second input coupled to the output of the falling edge detection circuit, a first output, and a second output. The circuit also includes a first power supply having a first terminal and a second terminal, the first terminal coupled to the first output of the power supply compensation circuit, and a second power supply having a first terminal and a second terminal, the first terminal coupled to the second output of the power supply compensation circuit.

Abstract: An integrated circuit (IC) includes a semiconductor substrate and an interconnect region. The semiconductor substrate has a first surface and a second surface opposite the first surface. The semiconductor substrate has a first region with a passive component. The semiconductor substrate has a second region outside the first region. The resistance of the second region is smaller than the resistance of the first region. The interconnection region is on the second surface of the semiconductor substrate.

Abstract: In some aspects, an integrated circuit comprises an input voltage terminal, a capacitor terminal, a first NMOS transistor connected to the input voltage terminal, a first PMOS transistor connected to a first NMOS gate terminal of the first NMOS transistor and connected to the capacitor terminal, the first PMOS transistor having a first PMOS gate terminal, a second PMOS transistor connected to the first NMOS gate terminal of the first NMOS transistor, the second PMOS transistor having a second PMOS gate terminal, a switched output terminal, a second NMOS transistor connected to the switched output terminal, a third NMOS transistor connected to the switched output terminal, an inverter, and a complementary metal oxide semiconductor (CMOS) transistor pair, the CMOS transistor pair having an input connected to the third NMOS transistor and an output connected to a second PMOS gate terminal of the second PMOS transistor.

Abstract: An example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.

Abstract: A test system includes a test instrument with a signal terminal, a splitter having a splitter input connected to the signal terminal and multiple splitter outputs, multiple test channels, each including a socket with a socket terminal connected to a respective one of the splitter outputs to couple a transceiver terminal of an installed electronic device under test (DUT) to the respective splitter output, and a controller configured to operate the test instrument to concurrently test transceiver circuits of the installed DUTs at respective unique subcarriers of an OFDM signal at the signal terminal.

Abstract: In an example, a system includes a loop filter including one or more integrators. The system includes a ramp generator. The system includes a comparator having a first input coupled to an output of the loop filter, a second input coupled to an output of the ramp generator, and having an output. The system includes a mute loop coupled to an input of the loop filter and the output of the comparator. The system includes a power stage having an input coupled to the output of the comparator, and having an output. The system includes a main loop coupled to the output of the power stage and the input of the loop filter. The system includes an integrated error detector having an input coupled to the loop filter, and having an output. The system includes a dual comparator having an input coupled to the output of the integrated error detector.