Abstract: A circuit includes a resonator, a transistor pair, and a common-mode feedback circuit. The transistor pair is cross-coupled across the resonator. The common-mode feedback circuit is coupled to the transistor pair. The common-mode feedback circuit includes first and second degeneration cells. The second degeneration cell is connected in parallel with the first degeneration cell. The second degeneration cell is configured to switchably vary a current flow through the transistor pair.

Abstract: A method for automatic generation of calibration parameters for a surround view (SV) camera system is provided that includes capturing a video stream from each camera comprised in the SV camera system, wherein each video stream captures two calibration charts in a field of view of the camera generating the video stream; displaying the video streams in a calibration screen on a display device coupled to the SV camera system, wherein a bounding box is overlaid on each calibration chart, detecting feature points of the calibration charts, displaying the video streams in the calibration screen with the bounding box overlaid on each calibration chart and detected features points overlaid on respective calibration charts, computing calibration parameters based on the feature points and platform dependent parameters comprising data regarding size and placement of the calibration charts, and storing the calibration parameters in the SV camera system.

Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of the bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.

Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B?), and concatenate M2(A) and M2(B?) to obtain an aggregate velocity matrix M2(A&B?). The processor cores perform a second FT on each row of M2(A&B?) to obtain a range and velocity matrix M3(A&B?).

Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

Abstract: A radar system is provided that includes a compression component configured to compress blocks of range values to generate compressed blocks of range values, and a radar data memory configured to store compressed blocks of range values generated by the compression component.

Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.

Abstract: Techniques for determining an angle-of-arrival of a wireless transmission are provided, including receiving, with a first antenna, at least a first portion of a wireless transmission, determining when a second portion of the wireless transmission will be received, switching to the second antenna to receive the second portion of the wireless transmission, determining an angle of arrival of the wireless transmission based on the first portion and the second portion of the wireless transmission, and outputting the angle of arrival of the wireless transmission.

Abstract: In some examples, an apparatus comprises a chopper, a first microelectromechanical system (MEMS) device, a second MEMS device, and a processing circuit. The chopper configured is to repeatedly switch states to enable and disable provision of a light signal. The first MEMS device is configured to provide first and second irradiance signals when the chopper is in, respectively, first and second states The second MEMS device is configured to provide first and second reference signals when the chopper is in, respectively, the first and second states. The processing circuit is configured to generate a first signal based on the first irradiance signal and the first reference signal, generate a second signal based on the second irradiance signal and the second reference signal, and provide a third signal at the processing output representing an irradiance measurement of the light source based on a difference between the first and second signals.

Abstract: In some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. The substrate includes a semiconductor material and has opposing first and second surfaces. The trench extends between the first surface and the second surface, the trench having the dielectric material. The layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: In one example, an apparatus comprises a substrate, a first piezoelectric flap, and a second piezoelectric flap. The substrate has an opening. The first piezoelectric flap has a first end on the substrate and has a first portion extending over a first part of the opening, the first piezoelectric flap including first electrodes, in which the first electrodes extend no more than half of a first length of the first portion. The second piezoelectric flap has a second end on the substrate and has a second portion extending over a second part of the opening, the second piezoelectric flap including second electrodes, in which the second electrodes extend no more than half of a second length of the second portion.

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

Abstract: Various embodiments of the present technology relate to using neural networks to detect objects in images. More specifically, some embodiments relate to the reduction of computational analysis regarding object detection via neural networks. In an embodiment, a method of performing object detection is provided. The method comprises determining, via a convolution neural network, at least a classification of an image, wherein the classification corresponds to an object in the image and comprises location vectors corresponding to pixels of the image. The method also comprises, for at least a location vector of the location vectors, obtaining a confidence level, wherein the confidence level represents a probability of the object being present at the location vector, and calculating an upper-bound score based at least on the confidence level.

Abstract: An apparatus includes a light source configured to produce light and a prism. The apparatus also includes freeform optics optically coupled between the light source and the prism, the freeform optics configured to direct the light towards the prism and eyepiece optics optically coupled to the prism. Additionally, the apparatus includes a spatial light modulator (SLM) optically coupled to the prism, the prism configured to direct the light towards the SLM, the SLM configured to modulate the light to produce modulated light, and the prism configured to direct the modulated light towards the eyepiece optics.

Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.