Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a receiver path including a transimpedance amplifier having an output coupled to the ADC; and a controller coupled to the receiver path and configured to, upon detection of a jamming event of the receiver path, cause an increase in a transconductance of the transimpedance amplifier from a first transconductance value to a second transconductance value.

Abstract: In an embodiment, a system includes: an analog-to-digital converter (ADC); a transmitter path; a receiver path including a first amplifier including: an output coupled to the ADC, and a first high-pass filter; and a controller coupled to the transmitter path and to the receiver path, where the controller is configured to: cause a corner frequency of the first high-pass filter to increase from a first value to a second value, simultaneously or after causing the corner frequency of the first high-pass filter to increase, cause the transmitter path to be enabled, and after a first signal begins transmission in the enabled transmitter path, and during transmission of the first signal in the enabled transmitter path, cause the corner frequency of the first high-pass filter to decrease from the second value to the first value.

Abstract: A system includes a spatial light modulator (SLM) and a circuit including a processor. The SLM includes pixel elements. The circuit is configured to convert M primary video signals to N multi-primary video signals. The circuit is configured to use a first multi-primary video signal to derive a first additive offset to a first primary video signal, to use the first multi-primary video signal to derive a second additive offset to a second primary video signal of the M primary video signals, to add the first additive offset to the first primary video signal, to add the second additive offset to the second primary video signal, and to derive a bit plane based on the first primary signal having the first additive offset added thereto and to transmit the bit plane to the SLM to selectively control on and off states of the pixel elements of the SLM.

Abstract: A probe card with a voltage terminal configured to be coupled to a voltage supply and a current terminal configured to be coupled to a current supply. The voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles. The probe card has an overlap resistor capacitor (RC) element coupled to the input node. The probe card includes an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles. The probe card has a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node and an ADC current capture module coupled in parallel to the resistive element.

Abstract: Disclosed examples include heart rate monitor systems and methods to estimate a patient heart rate or rate of another pulsed signal, in which rate hypotheses or states, are identified for a current time window according to digital sample values of the pulsed signal for a current sample time window, and a rate change value is computed for potential rate transitions between states of the current and previous time windows. Transition pair branch metric values are computed as a function of the rate change value and a frequency domain amplitude of the corresponding rate hypothesis for the current time window, and the pulsed signal rate estimate is determined according to a maximum path metric computed according to the branch metric value and a corresponding path metric value for the previous time window.

Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

Abstract: A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

Abstract: An exhaust stream monitoring system for a photolithography track of an IC fabrication process comprises a reaction chamber including a housing, an inflow port and an outflow port, the housing containing a thermal plate for heating a semiconductor process wafer for a predetermined amount of time. An influent pipe coupled to the inflow port supplies a photoresist adhesion promoter in a gaseous form to the reaction chamber. An effluent pipe coupled to the outflow port is operative to remove byproducts from the reaction chamber as an exhaust stream. At least one gas sensor manifold assembly is coupled to the effluent pipe for monitoring the exhaust stream from the reaction chamber to detect presence of one or more byproducts of a reaction between the photoresist adhesion promoter and the semiconductor process wafer.

Abstract: A bandgap voltage reference circuit includes: a bandgap voltage reference (VBG) core having a power input and first and second terminals; a bandgap operational amplifier (BGOA) having an operational amplifier output and first and second terminals, the first terminal of the BGOA coupled to the first terminal of the VBG core, and the second terminal of the BGOA coupled to the second terminal of the VBG core; and a feedback circuit having a feedback input and a feedback output, the feedback input coupled to the operational amplifier output, and the feedback output coupled to the power input. The feedback circuit includes a scaling amplifier having an inverting input, a non-inverting input, and a scaling amplifier output.

Abstract: In some examples, a circuit includes an interface configured to couple to a memory that includes a set of outputs to provide a set of data from the memory. The circuit further includes a rotator coupled to the interface that includes a first set of multiplexors that each include a set of inputs coupled to the set of outputs of the interface and an output. The circuit further includes a storage circuit coupled to the rotator that includes a register file coupled to the outputs of the first set of multiplexors an alignment network. The alignment network includes a second set of multiplexors that each include a set of inputs coupled to the register file and an output.

Abstract: For surface wetting control, an apparatus can expel fluid from a droplet on a surface using a transducer mechanically coupled to the surface. A first area of the surface can have a first wettability for the fluid, and a second area of the surface can have a second wettability for the fluid. The first wettability of the first area of the surface can be greater than the second wettability of the second area of the surface. The first area and the second area can have a patterned arrangement.

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for two selected dimensions of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When either selected dimension in the stream of vectors exceeds a respective specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

Abstract: A method and apparatus for sample adaptive offset without sign coding. The method includes selecting an edge offset type for at least a portion of an image, classifying at least one pixel of at least the portion of the image into edge shape category, calculating an offset of the pixel, determining the offset is larger or smaller than a predetermined threshold, changing a sign of the offset based on the threshold determination; and performing entropy coding accounting for the sign of the offset and the value of the offset.

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

Abstract: A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.

Abstract: Aspects of this description provide for a computer program product comprising computer executable instructions. In at least some examples, the instructions are executable by a controller to cause the controller to broadcast, in a data frame, a scan request to a node, the scan request including a certificate of the controller and a public authentication key of the controller, receive, in the data frame, a scan response from the node, the scan response including a certificate of the node and a public authentication key of the node, and perform pairing between the controller and the node based on the public authentication key of the node and a private authentication key of the controller.

Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.