Patents Assigned to Texas Instruments Incorporated
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Publication number: 20240088647Abstract: In one example, an apparatus comprises: a first switch and a second switch coupled between a fuse terminal and a ground terminal, the first switch having a first switch control terminal, the second switch having a second switch control terminal; and a driver circuit having a control input, a first control output, and a second control output, the control input coupled to the fuse terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: Texas Instruments IncorporatedInventors: Yogesh Kumar Ramadass, Ujwal Radhakrishna, Jeffrey Morroni
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Publication number: 20240088878Abstract: In one example, an apparatus comprises a power stage having a first power stage input, a second power stage input, and a power stage output. The apparatus also comprises a modulator circuit having a first ramp input, a second ramp input, a modulator input, a first modulator output, and a second modulator output, the first modulator output coupled to the first power stage input, and the second modulator output coupled to the second power stage input. The apparatus also comprises a multi-level ramp generator having a first ramp output and a second ramp output, the first ramp output coupled to the first ramp input, and the second ramp output coupled the second ramp input.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: Texas Instruments IncorporatedInventors: Yinglai Xia, Shailendra Kumar Baranwal, Yogesh Kumar Ramadass, Junmin Jiang
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Patent number: 11927624Abstract: One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current.Type: GrantFiled: June 22, 2022Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Harsh Patel, Aalok Dyuti Saha, Sanjeev Praphulla Chandra Nyshadham, Subrato Roy, Gaurav Kumar Mittal
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Patent number: 11927604Abstract: A wafer probe test system having a probe card with a probe head, a rotary magnet, a magnetic sensor positioned to sense the magnetic field of the rotary magnet and a controller coupled to the probe card, where the probe head has probe needles to engage features of test sites of a wafer in a wafer plane of orthogonal first and second directions, and the rotary magnet is rotatable around an axis of a third direction to provide a magnetic field to the wafer, in which the controller includes a model of magnetic flux density in the first, second and third directions at the respective test sites of the wafer as a function of a rotational angle of the rotary magnet, a probe needle height along the third direction and a measured magnetic flux density of the magnetic sensor.Type: GrantFiled: May 6, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xinkun Huang, Dok Won Lee, Christopher Michael Ledbetter, Bret Alan Dahl, Roy Deidrick Solomon
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Patent number: 11929308Abstract: In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.Type: GrantFiled: October 29, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steffany Ann Lacierda Moreno, John Carlo Cruz Molina, Rafael Jose Lizares Guevara
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Patent number: 11929744Abstract: An apparatus includes a moveable electrode which moves along an interstitial pathway defined by four fixed electrodes. The first and second fixed electrodes are separated by a first distance. The third and fourth fixed electrodes are separated by a second distance and adjacent to the first and second fixed electrodes, respectively. A capacitance sensing circuit coupled to the four fixed electrodes determines a first capacitance using the first and second fixed electrodes and a second capacitance using the third and fourth fixed electrodes. In some examples, the apparatus also comprises fifth and sixth fixed electrodes separated by a third distance and orthogonal to the first and second fixed electrodes and seventh and eighth fixed electrodes separated by a fourth distance and orthogonal to the third and fourth fixed electrodes. The fifth and seventh fixed electrodes are adjacent, and the sixth and eighth fixed electrodes are adjacent.Type: GrantFiled: February 6, 2020Date of Patent: March 12, 2024Assignee: Texas Instruments IncorporatedInventor: Peter Spevak
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Patent number: 11927689Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.Type: GrantFiled: June 18, 2021Date of Patent: March 12, 2024Assignee: Texas Instruments IncorporatedInventors: Sujaata Ramalingam, Karthik Subburaj, Pankaj Gupta, Anil Varghese Mani, Karthik Ramasubramanian, Indu Prathapan
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Patent number: 11927633Abstract: A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.Type: GrantFiled: September 23, 2022Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mudasir Kawoosa, Pervez Garg, Prateek Giri
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Patent number: 11929311Abstract: A power converter package includes a leadframe including first and second die pads, and supports connected to first leads, and second leads. A first semiconductor die including first bond pads is on the first die pad, and a second semiconductor die including second bond pads is on the second die pad. A transformer stack includes a top magnetic sheet and a bottom magnetic sheet on respective sides of a laminate substrate that includes a coil within, and coil contacts. A silicon block is attached to the bottom magnetic sheet and edges of the laminate substrate are attached to the supports. Bond wires are between the first bond pads and the second leads, the second bond pads and the second leads, and the first and second bond pads and the coil contacts. Mold encapsulates the respective semiconductor and the transformer stack. A bottom of the silicon block is exposed from the mold.Type: GrantFiled: October 15, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vivek K Arora, Woochan Kim
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Patent number: 11930590Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.Type: GrantFiled: March 31, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
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Patent number: 11930194Abstract: Systems, methods and computer readable mediums are presented for encoding a stream of input video frames, in which the input video frames are down sampled and the down sampled frames are encoded in a first encoding pass to generate a set of first pass coded frames forming a single first pass I frame and a plurality of first pass P frames formed into first pass sub-groups of pictures (SUB-GOPs). First pass encoding statistics are generated for individual first pass SUB-GOPs, and the statistics are used to encode the input video frames in a second encoding pass to generate a set of second pass coded frames.Type: GrantFiled: August 30, 2021Date of Patent: March 12, 2024Assignee: Texas Instruments IncorporatedInventors: Arun Shankar Kudana, Soyeb Nagori
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Patent number: 11927690Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.Type: GrantFiled: January 13, 2022Date of Patent: March 12, 2024Assignee: Texas Instruments IncorporatedInventors: Tom Altus, Jasbir Singh Nayyar, Karthik Ramasubramanian, Brian Paul Ginsburg
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Patent number: 11927629Abstract: Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.Type: GrantFiled: September 27, 2021Date of Patent: March 12, 2024Assignee: Texas Instruments IncorporatedInventors: Pandy Kalimuthu, Anthony Joseph Lell
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Patent number: 11929423Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.Type: GrantFiled: June 15, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Patent number: 11929765Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.Type: GrantFiled: July 20, 2021Date of Patent: March 12, 2024Assignee: Texas Instruments IncorporatedInventor: Meghna Agrawal
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Patent number: 11929717Abstract: An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.Type: GrantFiled: January 24, 2022Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mahadevan Shankara Venkiteswaran, Arun Singh, Jofin Vadakkeparasseril Joseph
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Patent number: 11929751Abstract: A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.Type: GrantFiled: December 30, 2022Date of Patent: March 12, 2024Assignee: Texas Instruments IncorporatedInventors: Ankit Garg, Abhijit Patki
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Patent number: 11929755Abstract: This description relates generally to piecewise temperature compensation. In an example, a circuit includes a knee code selector that can be configured to set a knee point temperature for a correction current responsive to a respective knee point temperature code of knee point temperature codes and a respective temperature sense signal of temperature sense signals. The circuit includes an output circuit that can be configured to provide the correction current responsive to the respective temperature sense signal and temperature voltages, and a trim digital to analog converter (DAC) that can be configured to provide a piecewise compensation current responsive to the correction current and a respective trim code of trim codes.Type: GrantFiled: October 29, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tallam Vishwanath, Sandeep Shylaja Krishnan
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Publication number: 20240079958Abstract: In one example, an apparatus comprises: a primary side bridge coupled between a power input and a first ground terminal, the primary side bridge having first switching terminals coupled to first capacitor terminals; and a secondary side bridge coupled between a power output and a second ground terminal, the secondary side bridge having second switching terminals coupled to second capacitor terminals.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Applicant: Texas Instruments IncorporatedInventors: Ashish Kumar, Haoquan Zhang, Yogesh Kumar Ramadass
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Publication number: 20240077514Abstract: A method comprises receiving a signal from a piezoelectric device and receiving a measurement of a temperature of the piezoelectric device. The method further comprises reading a first parameter from a memory, in which the first parameter depends on the temperature and relates the signal to an acceleration value and reading a second parameter from the memory, in which the second parameter represents a degree of drift of the piezoelectric device at the temperature. The method further comprises determining an acceleration of the piezoelectric device based on the signal, the first parameter, and the second parameter.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Applicant: Texas Instruments IncorporatedInventors: Scott Robert SUMMERFELT, Benjamin Stassen COOK