Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.

Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.

Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.

Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.

Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.

Abstract: In described examples, a system (e.g., a projection system) can include a diffractive optical element adapted to be illuminated by at least one coherent light beam. A lens array is coupled to receive a diffracted beam of light from the diffractive optical element. The lens array includes a first and a second array lens. The first array lens is coupled to receive a first sector of a pattern of illumination of the diffracted beam of light, and the second array lens is coupled to receive a second sector of the pattern of illumination of the diffracted beam of light. A spatial light modulator is coupled to receive overlapping diffracted beams of light from the first and second array lenses to form an image beam.

Abstract: An integrated circuit includes a semiconductor substrate and a metallization structure over the semiconductor substrate. The metallization structure includes: a dielectric layer having a surface; a conductive routing structure; and an electronic circuit. Over the surface of the dielectric layer, a material is configured to set or adjust the electronic circuit.

Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

Abstract: A method for encoding a picture of a video sequence in a bit stream that reduces slice header parsing overhead is provided. The method includes determining weighting factors that may be used for weighted prediction in encoding at least one slice of the picture, wherein a total number of the weighting factors is constrained to not exceed a predetermined threshold number of weighting factors, wherein the threshold number is less than a maximum possible number of weighting factors, and signaling weighted prediction parameters including the weighting factors in a slice header in the bit stream.

Abstract: A method includes generating a reference voltage by periodically switching direction of current flow in a diagnostic sensor, where the reference voltage is a non-sinusoidal differential voltage of which an amplitude alternates between minimum and maximum values, and where the reference voltage includes a diagnostic sensor output voltage component responsive to an external magnetic field and a diagnostic sensor offset voltage component responsive to a mismatch of the diagnostic sensor. The method also includes amplifying the reference voltage to produce an amplified reference voltage, where the amplified reference voltage is a differential voltage having an amplifier offset voltage component. Additionally, the method includes demodulating the amplified reference voltage by filtering the diagnostic sensor offset voltage component and the amplifier offset voltage component to produce a demodulated voltage. Also, the method includes digitizing the demodulated voltage to produce a digitized voltage.

Abstract: A lens structure system with a lens structure and a multi-segmented transducer coupled to the lens structure. Each segment in the plurality of segments has a first conductor and a second conductor, wherein the first conductor and the second conductor are electrically coupled to the segment. The system also has circuitry for applying a voltage to selected segments in the plurality of segments with standing wave signals and traveling wave signals.

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

Abstract: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.

Abstract: A processor includes a central processing unit (CPU) and diagnostic monitoring circuitry. The diagnostic monitoring circuitry is coupled to the CPU. The diagnostic monitoring circuitry includes a monitoring and cyclic redundancy check (CRC) computation unit. The monitoring and CRC computation unit is configured to detect execution of a diagnostic program by the CPU, and to compute a plurality of CRC values. Each of CRC values corresponds to processor values retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystem while the CPU executes the diagnostic program.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

Abstract: A light emitting diode (LED) matrix driver includes a scan line switch coupled to a scan line of an LED matrix and adapted to be coupled to a signal ground; a first voltage clamp coupled to the scan line switch and the scan line; and a second voltage clamp coupled to the scan line.

Abstract: A two-stage differential amplifier with cross-coupled compensation capacitors. The differential amplifier includes first amplifier circuitry receiving a differential input voltage and presenting first and second intermediate outputs. The amplifier further includes a second amplifier stage with a first leg having an input coupled to the second intermediate output of the first amplifier circuitry, and a second leg having an input coupled to the first intermediate output of the first amplifier circuitry. A compensation capacitor is provided for each leg of the second amplifier stage, each coupled between the output of that amplifier leg and its input. A first cross-coupled capacitor is coupled between the output of the first amplifier leg to the input of the second amplifier leg, and a second cross-coupled capacitor is coupled between the output of the second amplifier leg and the input of the first amplifier leg.

Abstract: A method to compress an image includes assigning each pixel of the image to a cluster based on a red-green-blue (RGB) location of the pixel. The method also includes updating a centroid of the cluster after each pixel is assigned, based at least in part on the RGB location of the pixel, where the centroid is an RGB location. The method includes replacing each pixel in the image with an RGB value of the centroid of the cluster to which the pixel is assigned. The method also includes instructing a display to display a compressed image where, in the compressed image, each pixel in the image is replaced with the RGB value of the centroid of the cluster to which the pixel is assigned.

Abstract: Example power factor correction circuits to correct the power factor of power converters are disclosed. An example power factor correction controller circuit includes a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter and further includes a compensating current determiner to determine, based on the phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter. The power factor correction controller circuit further includes a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted by the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of the an input current drawn at an input of the power converter.

Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.