Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

Abstract: An electronic device, in disclosed embodiments, includes an antenna, transceiver circuitry coupled to the antenna, a memory configured to store a first operation key and instructions, and a processor coupled to the transceiver and to the memory. The processor is configured to execute the instructions stored in the memory to cause the electronic device to, in response to receiving a first transmission containing an encrypted version of a second operation key that is encrypted by the first operation key, decrypt the encrypted version of the second operation key using the first operation key to recover the second operation key, store the second operation key in the memory, transmitting, by a transmitter of the electronic device, a second transmission that contains the first operation key and a command.

Abstract: An integrated circuit testing assembly that includes: (i) a first slug configured to contact a first surface of a first set of pins of an integrated circuit; (ii) a second slug configured to contact a second surface of the first set of pins of the integrated circuit; (iii) a third slug configured to contact a first surface of a second set of pins of the integrated circuit; and (iv) a fourth slug configured to contact a second surface of the second set of pins of the integrated circuit.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

Abstract: In examples, a package comprises a semiconductor die, a gullwing conductive terminal coupled to the semiconductor die, and a mold compound covering the semiconductor die and the conductive terminal. The conductive terminal extends outward from the mold compound. The conductive terminal includes a top surface and a bottom surface opposing the top surface, the conductive terminal includes a first bend and a second bend more distal from the mold compound than the first bend, and the bottom surface includes a first cavity extending along a width of the conductive terminal at the first bend. The top surface includes a second cavity extending along the width of the conductive terminal at the second bend.

Abstract: In a described example, an example no-lead semiconductor device package includes: a die pad in a central portion of a partially etched leadframe and terminals. The terminals include a device side surface formed in an upper layer of the partially etched leadframe, and a first exterior end in the upper layer; a board side surface formed in a lower layer of the partially etched leadframe extending from the upper layer; a second exterior end in the lower layer, the second exterior end inset from the first exterior end, and an inset portion extending from the first exterior end to the second exterior end. A semiconductor die is mounted to the die pad. Mold compound covers the semiconductor die, the second exterior end of the terminals and the inset portion of the terminals are exposed from the mold compound, with the mold compound extending along sides of the terminals.

Abstract: A circuit includes: a driver circuit; a sense resistor; a test circuit; a current sense circuit; a calibration controller; and a switch controller. The current sense circuit is configured to: obtain first sense signals responsive to a test voltage applied to the sense resistor by the test circuit, the test voltage being a direct-circuit voltage; and obtain second sense signals responsive a supply voltage applied to the sense resistor by the driver circuit, the supply voltage including a common-mode voltage. The calibration controller is configured to calibrate the current sense circuit responsive to the first sense signals and the second sense signals. The switch controller is configured to update switch control signals provided to the driver circuit responsive to current sense signals obtained by the calibrated current sense circuit.

Abstract: A circuit includes a first wireless radio frequency (RF) transceiver and a time-of-flight estimator included with or coupled to the first wireless RF transceiver. The time-of-flight estimator estimates a time-of-flight between the first wireless RF transceiver and a second wireless RF transceiver using: a first interval value that indicates an amount of time between when the second wireless RF transceiver received the message and when the second wireless RF transceiver transmitted the response; a first error value that indicates an offset between when the second wireless RF transceiver sampled the message and a target sampling point for the message; a second interval value that indicates an amount of time between when the TX chain sent the message and when the RX chain received the response; and a second error value that indicates an offset between when the RX chain sampled the response and a target sampling point for the response.

Abstract: In a described example, an apparatus includes: a package substrate having a die mount surface; semiconductor die flip chip mounted to the package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the active surface of the semiconductor die and connected to the package substrate by solder joints; a thermal interposer comprising a thermally conductive material positioned over and in thermal contact with a backside surface of the semiconductor die; and mold compound covering a portion of the package substrate, a portion of the thermal interposer, the semiconductor die, and the post connects, the thermal interposer having a surface exposed from the mold compound.

Abstract: A test structure for testing the on-die-parametric (ODP) measurements of circuit devices on a die. When no circuit devices are connected to the test structure, the test structure is configured to supply an input voltage at an input node of the test structure. While supplying the input voltage, the test structure determines a first measure of current at the input node and a first measure of voltage at an output node of the test structure. Next, while a single circuit device is connected to the test structure, the test structure is configured to adjust the input voltage until a second measure of voltage at the output node substantially matches the first measure of voltage. Next, the test structure determines a second measure of current at the input node. Finally, the test structure determines a parametric measurement of the device based on a difference between the first and second current measurements.

Abstract: An oscillator apparatus, including a first node adapted to be coupled to a first terminal of a crystal oscillator; a second node adapted to be coupled to a second terminal of the crystal oscillator; a transconductance circuit; a first switch coupled between the first node and the second node; and a second switch coupled between the transconductance circuit and the second node.

Abstract: A transistor is coupled between a first voltage input and a voltage output in a first current path. First circuitry is coupled to a second voltage input, a control terminal of the transistor, and the voltage output. Second circuitry is coupled between the control terminal and ground in a second current path and between the control terminal and ground in a third current path parallel to the second current path. The second current path includes the control terminal, first and second terminals of the second circuitry, and ground. The third current path includes the control terminal, a second and the third terminal of the second circuitry, and ground. Third circuitry is coupled between the control terminal and the voltage output in a fourth current path. The fourth current path includes the control terminal, first and second terminals of the third circuitry, and the voltage output.

Abstract: In described examples, an integrated circuit includes first and second transistors, a switch, a capacitor, a resistor, and first and second comparators. A first terminal of the switch is coupled to a first terminal of the resistor. A second terminal of the switch is coupled to a second terminal of the resistor, a first terminal of the capacitor, and a gate of the first transistor. The first comparator is configured to receive at the first input a first reference voltage, and an output of the first comparator is coupled to a gate of the second transistor. The second comparator is configured to receive at the first input a second reference voltage. A second input of the second comparator is coupled to a second input of the first comparator. An output of the second comparator is coupled to a control input of the switch.

Abstract: A method includes receiving a first measurement signal representing a first time between transitions of a motor commutation state. The method further includes receiving a second measurement signal representing a second time between transitions of a motor floating terminal voltage. The method further includes determining a motor speed state based on a combination of the first and second measurement signals, determining a motor commutation state based on the motor speed state and the motor floating terminal voltage; and providing a control signal to a motor inverter based on the motor commutations state.

Abstract: An example apparatus includes: first oscillator circuitry; second oscillator circuitry; period calculator circuitry coupled to the first oscillator circuitry and coupled to the second oscillator circuitry; averaging circuitry coupled to the period calculator circuitry; and coefficient filter circuitry coupled to the averaging circuitry.

Abstract: A peripheral proxy subsystem provides routing mechanisms to allow multiple hosts to communicate with multiple functions, physical and virtual, of a single root I/O virtualization (SR-IOV) peripheral, which may include a physical function and a plurality of virtual functions associated with the physical function. The peripheral proxy subsystem, which may be embodied as a controller, includes a first endpoint interface; a second endpoint interface; and a single root controller interface configured to couple to the SR-IOV peripheral. The controller is configured to be able to present through the single root controller interface: a first subset of the plurality of virtual functions through a first cloned instance of the physical function at the first endpoint interface; and a second subset of the plurality of virtual functions through a second cloned instance of the physical function at the second endpoint interface.

Abstract: Methods of separating semiconductor dies are described. The method can separate individual semiconductor dies from a semiconductor wafer without using a blade. The methods include a plasma etch process utilizing metal structures formed on a back side of the wafer as masks to remove a portion of the semiconductor wafer from the back side. The portion removed by the plasma etch process corresponds to the scribe lines between the semiconductor dies. The plasma etch process terminates at a dielectric layer formed on a front side of the wafer. The dielectric layer may be severed to complete the separation process. Moreover, an ultrasonic water jet process may be utilized to remove burrs of the dielectric layer that has been severed.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A method includes performing a fabrication process that fabricates a wafer having an upper region and unit areas arranged in rows along a first direction and columns along an orthogonal second direction and respective scribe streets between adjacent unit areas to: form first and second electrical components on or in the upper region in respective unit areas or scribe streets, the first and second electrical components spaced apart from one another and including structural features with different respective first and second spacing distances along the first direction.

Abstract: A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.