Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.

Abstract: An example apparatus includes: pass gate circuitry having a first terminal and a second terminal; process tracker circuitry having a first terminal and a second terminal, the first terminal of the process tracker circuitry coupled to the first terminal of the pass gate circuitry; and temperature compensation circuitry having a first terminal and a second terminal, the first terminal of the temperature compensation circuitry coupled to the second terminal of the process tracker circuitry, and the second terminal of the temperature compensation circuitry coupled to the second terminal of the pass gate circuitry.

Abstract: A method for decoding encoded blocks of pixels from an encoded video bit stream is provided that includes decoding a block vector corresponding to an encoded block of pixels from the encoded bit stream, verifying that the block vector indicates a block of reconstructed pixels in a search area including reconstructed pixels of a largest coding unit (LCU) including the encoded block of pixels and N left neighboring reconstructed LCUs of the LCU, and decoding the encoded block of pixels, wherein the block of reconstructed pixels is used as a predictor for the encoded block of pixels.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

Abstract: A method for automatic exposure (AE) control is provided that includes receiving statistics for AE control for an image from an image signal processor (ISP) coupled to an image sensor generating the image, computing an exposure value at a current time t (EV(t)) using a cost function based on target characteristics of an image, wherein computation of the cost function uses the statistics, and computing AE settings for the image sensor based on EV(t).

Abstract: A circuit includes a capture subsystem and digital pre-distortion (DPD) circuitry. The capture subsystem is configured to capture a set of signal samples responsive to a capture enable signal. The DPD circuitry is configured to generate a signal statistics signal based on an input signal, generate a set of DPD coefficients based on the set of signal samples, and apply DPD correction to the input signal to produce an output signal based on the signal statistics signal and the set of DPD coefficients. The set of signal samples includes samples of the signal statistics signal.

Abstract: A circuit includes a first transistor coupled between a discharge terminal and a ground terminal. The first transistor has a first control terminal. A resistor is coupled between a power terminal and the first control terminal. A second transistor has a second control terminal coupled to the discharge terminal. A rectifying device is coupled between the resistor and the second transistor.

Abstract: A method and apparatus for a low complexity transform unit partitioning structure for High Efficiency Video Coding (HEVC). The method includes determining prediction unit size of a coding unit, and setting the size of transform unit size of Y, U and V according to the prediction unit size of the coding unit.

Abstract: A switching converter controller includes: mode control logic; and a pulse-frequency modulation (PFM) timer circuit coupled to the mode control logic. The PFM timer circuit includes: a first terminal; a second terminal; a digital-to-analog converter (DAC); a current source; a capacitor; and a comparator. A first terminal of the DAC is coupled to the first terminal of the PFM timer circuit. The current source has a first terminal, a second terminal, and a third terminal. The second terminal of the current source is coupled to a second terminal of the DAC. A first terminal of the capacitor is coupled to the first terminal of the current source. The comparator has first, second, and third terminals. The first terminal of the comparator is coupled to the first terminal of the capacitor. The third terminal of the comparator is coupled to the second terminal of the PFM timer circuit.

Abstract: An example transceiver includes a resistor having a first terminal and a second terminal coupled to a communication bus terminal. The transceiver includes a first transistor having a control terminal, a first terminal coupled to the first terminal of the resistor, and a second terminal coupled to a common mode voltage terminal. The transceiver includes a second transistor having a control terminal, a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to the common mode voltage terminal. The transceiver includes a first driver having a first terminal coupled to a ground terminal, a second terminal coupled to the second terminal of the first transistor and the second terminal of the second transistor, a third terminal coupled to the control terminal of the first transistor, and a fourth terminal coupled to the control terminal of the second transistor.

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

Abstract: A circuit includes a capacitive isolator, a rectifier circuit, first and second receivers, and a switch. The capacitive isolator has first and second inputs, and first and second outputs. The rectifier circuit has first and second terminals respectively coupled to the first and second outputs of the capacitive isolator, a third terminal, and a fourth terminal. The first receiver has a first input coupled to the first output of the capacitive isolator, a second input coupled to second output of the capacitive isolator, and an output. The second receiver has a first input coupled to the third terminal of the rectifier circuit, a second input coupled to the fourth terminal of the rectifier circuit, an enable input coupled to the output of the first receiver, and an output. The switch has a control input coupled to the output of the second receiver.

Abstract: A system is provided. The system generally includes a first processor configured to receive image input data from a red-green-blue infrared (RGBIR) sensor. The first processor of the system is configured to generate a first intermediate image data from the image input data. The system generally includes a second processor. The second processor of the system is configured to generate a second intermediate image data that includes red-green-blue (RGB) image data from the first intermediate image data, and to generate a third intermediate image data that includes infrared (IR) image data from the first intermediate image data. The system generally includes a third processor. The third processor of the system is configured to process the third intermediate image data. The system generally includes a fourth processor. The fourth processor of the system is configured to process the second image data.

Abstract: An apparatus includes a semiconductor structure having a cavity. The apparatus also includes a first electrical terminal on a first cavity side, a second electrical terminal on a second cavity side, and the second electrical terminal including an extension that overlaps part of the cavity. The apparatus also includes a bendable beam extending from the first cavity side and overlapping at least part of the extension. The apparatus also includes an actuator in a periphery of the beam, the actuator configured to generate a fringing electric field that causes the second beam side to move towards the extension in a direction different from the fringing electric field and bend the beam.

Abstract: An optical position sensing system is disclosed. The system includes a substrate having a surface. A plurality of photodetectors are at multiple locations across the surface, each of the plurality of photodetectors providing detector pulse signals in response to receiving the light. The system further includes a processor that determines a phase shift between the transmitted light pulse signals and the respective detector pulse signals and applies a multi-path resolution operation to distinguish between the detector pulse signals representing the transmitted light pulse signals and those representing reflected light pulse signals. The processor also calculates a distance of a transmitting device from each of the photodetectors based on the determined phase shift and the multi-path resolution operation and calculates a multi-dimensional position of the transmitting device relative to the substrate based on the calculated distances.

Abstract: An apparatus includes a first primary coil, a second primary coil, and a secondary coil. The first and second primary coils each include a first, second, and third portion. The secondary coil includes a first and second portion in a first wafer layer, which are coupled together by a bridge in a second wafer layer. The second portion of the first primary coil is nested inside the first portion of the secondary coil in the first wafer layer. The second portion of the second primary coil is nested inside the second portion of the secondary coil in the first wafer layer. At least parts of the first and third portions of the first primary coil are adjacent the second portion of the secondary coil, and at least parts of the first and third portions of the second primary coil are adjacent the first portion of the secondary coil.

Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: An integrated circuit device is provided. In some examples, an integrated circuit die of the device includes a first capacitor arranged such that when the integrated circuit die is coupled to a package, the package affects a capacitance of the first capacitor, a second capacitor disposed directly underneath the first capacitor, and a capacitance measurement circuit coupled to the first capacitor and the second capacitor to determine the capacitance of the first capacitor and a capacitance of the second capacitor. The integrated circuit device may detect tampering with the die and/or the package based on the capacitances of the first capacitor and the second capacitor.