Abstract: A transducer system with transducer and circuitry for applying a pulse train at a single frequency to excite the transducer. The transducer is operable to receive an echo waveform in response to the pulse train. The system also comprises circuitry for determining a time of flight as between a first reference time associated with the pulse train and a second reference time associated with the echo waveform.

Abstract: A “weak” undriven state is defined as a signal state, distinguished from conventional unknown and high impedance states, and methods of representing this “weak” undriven state in circuit modelling and power aware digital/mixed-signal simulations for comprehensive and complete RTL-level design verification. The conventional unknown state refers to a circuit element that is powered but has an unknown value, a circuit element that is not powered, or a circuit element having an undriven, floating signal. The unknown state is modified, and the “weak” undriven state refers to a circuit element that is not powered and has an unknown value. The “weak” undriven state can have an electrically high impedance to known supply or ground when no other circuit element is active. The “weak” undriven state distinction is particularly useful to model and verify circuit designs known to be resilient to “weak” undriven states, using event driven logic circuit simulators.

Abstract: An example apparatus includes a termination network having a first input terminal coupled to a first input/output terminal and a second input terminal coupled to a second input/output terminal. The apparatus includes transmitter circuitry having a first output terminal coupled to the first input/output terminal and a second output terminal coupled to the second input/output terminal. The apparatus includes receiver circuitry having a first input terminal coupled to a first output terminal of the termination network and a second input terminal coupled to a second output terminal of the termination network. The apparatus includes control circuitry coupled to a third input terminal of the termination network, the control circuitry to: change an impedance of the termination network to compensate for a transient in a common mode voltage; and based on the common mode voltage reaching a steady state value, change the impedance of the termination network for steady state operation.

Abstract: An integrated circuit includes a semiconductor substrate that has a top surface. A trench is formed within the substrate, and a conductive filler structure fills the trench. An insulator is located between the semiconductor substrate and the conductive filler. The insulator has a top portion with a top surface at the top surface of the substrate, The insulator further has a bottom portion that forms a corner with the top portion and extends from the corner to a bottom of the trench.

Abstract: A method includes receiving, by a microcontroller, a live firmware update (LFU) command from an external host; and downloading, by the microcontroller, an image of a new version of firmware responsive to the LFU command. During a first time period, the method includes initializing only variables contained in the new version that are not contained in an old version of firmware. During a second time period, the method includes updating one or more of an interrupt vector table, a function pointer, and/or a stack pointer responsive to the new version. The second time period begins responsive to completing initialization of the variables.

Abstract: Signal processing comprising, first, determining a plurality of fast Fourier transform (FFT) values corresponding to each sample in a plurality of signal samples, second, variably compressing ones of the FFT values at different non-zero levels of compression, and third, storing the variably compressed ones of the FFT values.

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

Abstract: A semiconductor package includes a base insulating layer; a semiconductor die attached to a portion of the base insulating layer; and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates through the base insulating layer.

Abstract: In a memory device, a static random access memory (SRAM) circuit includes an array of SRAM cells arranged in rows and columns and configured to store data. The SRAM array is configured to: store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells. A memory controller circuit is configured to select the set of the SRAM cells based on a second set of information for the ML process.

Abstract: Systems and methods enable the classification of each value of multiple floating-point values stored in a first vector register, and storage in a second vector register multiple elements that each indicate a respective classification of a respective value of the multiple floating-point values. A system includes a functional unit, first and second vector registers coupled to the functional unit, and processing circuitry. The processing circuitry is configurable, e.g., via an instruction, to cause the functional unit to perform the classification and storage operations.

Abstract: A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning order within sub-pictures, wherein from core to core, coding of the sub-picture is independent around sub-picture boundaries, and wherein within a core, coding of a sub-picture is at least one of dependent or independent around sub-picture boundaries.

Abstract: Described embodiments include a circuit having a comparator with first and second comparator inputs and a comparator output. The second comparator input is coupled to a ripple reference voltage terminal. A switch is coupled between the first comparator input and a ground terminal, and has a switch control terminal that is coupled to the comparator output. A capacitor is coupled between the first comparator input and the ground terminal. A first current source is coupled between a supply terminal and the first comparator input, and has a first current control terminal. A second current source is coupled between a current output terminal and the ground terminal, and has a second current control terminal.

Abstract: An electronic device includes conductive leads, a conductive crossbar, and first and second bond wires. The conductive leads are arranged in a row along a side of a package structure and include a conductive first lead, a conductive second lead, and a conductive third lead. The first and second leads are non-adjacent, the third lead is between the first and second leads in the row, and the crossbar electrically connects the first and second leads. The first bond wire electrically connects a first conductive feature of a semiconductor die to one of the crossbar, the first lead, and the second lead, and the second bond wire electrically connects a second conductive feature of the semiconductor die to the third lead.

Abstract: Various embodiments include systems and methods to provide deterministic execution times for computer processors. In one example, a hardware module may include hardware logic, which is configured to track a value stored in a counter. The hardware module may detect a read or write access request from a processor, determine whether the value stored in the counter has reached a specified value, and then stall the processor using a hardware signal in response thereto. Once the counter reaches the specified value, the hardware logic may then un-stalls the processor using the hardware signal.

Abstract: An apparatus includes a substrate, a core, a primary side circuit, first and second secondary side circuits, a primary winding, and first and second secondary windings. The substrate includes first, second, and third metal layers. The core is in the substrate. The primary side circuit, and the first and second secondary side circuits are on the substrate. The primary winding is in the first metal layer of the substrate. The primary winding wraps around the core and is coupled to the primary side circuit. The first secondary winding is in the second metal layer of the substrate. The first secondary winding wraps around the core and is coupled to the first secondary side circuit. The second secondary winding is in the third metal layer of the substrate. The second secondary winding wraps around the core and is coupled to the second secondary side circuit.

Abstract: An example apparatus includes instructions and programmable circuitry configurable to at least one of instantiate or execute the instructions to authenticate a request to update a first trim value to a second trim value, wherein the first trim value is stored in a memory. The example apparatus also includes instructions to, in response to authentication of the request, store the second trim value to the memory while the first trim value remains stored in the memory.

Abstract: A voltage converter includes a power stage, a compensator circuit, and a modulator circuit. The power stage circuit has an input voltage terminal, an output voltage terminal, and a pulse width modulation (PWM) control input. The compensator circuit has a voltage input coupled to the output voltage terminal and has a compensation output. The modulator circuit has a compensation voltage input and a PWM control output. The compensation voltage input is coupled to the compensation output, and the PWM control output is coupled to the PWM control input. The modulator circuit includes a slope compensation ramp generator circuit that is configured to generate a slope compensation voltage ramp having a slope that decreases during at least a portion of a switching cycle.

Abstract: A multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to a third inductor terminal, a system voltage terminal, and a battery terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operation in a buck mode to operation in a buck-boost mode based on an off-time of the first half-bridge being less than a particular time.

Abstract: One example includes an antenna-on-package (AoP) system. The system includes a first transmission line patterned on a first metal layer. The first metal layer can be arranged to be coupled on a printed circuit board (PCB). The system also includes an antenna portion patterned on a second metal layer. The first and second metal layers can be separated by at least one dielectric layer. The system further includes a coaxial transition portion comprising a via configured to communicatively couple the first transmission line on the first metal layer to a second transmission line on the second metal layer. The second transmission line can be coupled to the antenna portion.

Abstract: An integrated circuit (IC) includes a semiconductor substrate having a first surface and a second surface opposite the first surface. A through wafer trench (TWT) extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate. Dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region has a conductive transmit patch. An antenna is formed, at least in part, by the dielectric material in the TWT and the transmit patch in the interconnect region. The antenna is configured to transmit or receive electromagnetic radiation between the transmit patch and the second surface of the semiconductor substrate through the dielectric material within the trench.