Low power dynamic logic gate with full voltage swing operation
Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the loic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.
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This application is related to U.S. patent application Ser. No. 09/967,189 entitled, R
This application is a continuation of U.S. application Ser. No. 10/895,193, filed Jul. 19, 2004, and titled L
This invention is related generally to reduced power logic and more specifically to reduced power logic having full voltage output swing and operating with recycled energy.
DESCRIPTION OF THE RELATED ART A previous application, U.S. patent application Ser. No. 09/967,189, entitled R
The precharge path 12, also connected between the output node 16 and the clock line 14, develops a conductive path, unconditionally, during a precharge phase or period. During this phase, the output node 16 is precharged to a voltage level related to the voltage level achieved by the clock line, which is a logic high during the precharge phase.
During the evaluation phase, the precharge path 12 is not conductive and during the precharge phase, the discharge path 10 is not conductive. Thus, in operation after the output node 16 is charged during the precharge phase, the logic function is evaluated during the evaluation phase, using the charge on the output node 16. If the inputs are such that the logic circuit stage is not conductive, then the output node 16 stays charged at the voltage level to which it was precharged. If the inputs are such that the logic circuit stage is conductive, then the output node 16 is discharged to approximately the low potential of the clock signal 14.
In the previous application, the precharge path 12 is implemented as a diode, as shown in
Therefore, there is a need the output of the logic circuit stage to achieve voltage levels substantially equal to the voltage levels of the clock signal carried on the clock line to which the logic circuit stage is connected.
BRIEF SUMMARY OF THE INVENTIONThe present invention is directed towards the above need. The present invention, in accordance with one embodiment of the present invention, includes a discharge path, a precharge path, and a control circuit. The discharge path is connected between a first node and a second node and is operative using energy flowing from the second node to the first node to evaluate a logic function of at least one input during an evaluation phase. The precharge path is connected between the first node and the second node and is conductive during a precharge phase so as to transfer energy from the first node to the second node. The control circuit has an output connected to the precharge path and is operative to establish and maintain the conductivity of the precharge path during the precharge phase independent of the states of the at least one input and the output node.
A method in accordance with one embodiment of the present invention is a method of evaluating a logic function. The method includes (i) providing a conductive path between a first node and a second node during a precharge phase to transfer energy between the first and second node, the first node being connected to energy storage circuitry that provides any energy to be transferred, the conductive path being established and maintained by a control circuit during the precharge phase, and (ii) evaluating a logic function of at least one input during an evaluation phase during which energy may flow between the second node and the first node, any said energy flowing being captured by the energy storage circuitry.
An advantage of the present invention is that the voltage range of the output node is approximately equal to the voltage range of the clock line, which is approximately a range from zero volts to the positive supply voltage.
Another advantage is that the output node can drive more logic inputs at a given clock cycle rate.
Yet another advantage is that the logic circuitry can operate at a higher clock cycle rate.
Yet another advantage is that lower power operation is achieved by removing a direct path between the output node and the clock line that consumes power during switching.
Yet another advantage is that low power operation is achieved because a portion of the energy used to precharge the output node and operate the discharge path is returned to the output node by the clock circuit.
BRIEF DESCRIPTION OF THE DRAWINGSThese and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
The clock line 14 carries a clock signal that has a first voltage and a second voltage. If the clock signal is a digital signal, the first voltage is a logic high and the second voltage is a logic low. During a precharge phase, while the clock signal is at a logic high, the output node 16 is precharged through transistor 40, whose channel is made conductive by either transistor 44 or transistor 42. During an evaluation phase, while the clock signal is at a logic low, transistor 40 is rendered non-conductive and transistor 46 is conditionally conductive depending on whether the input 48 is high or low. If the input 48 is high, then transistor 46 is conductive, thereby discharging the output node 16 to the clock line 14. If the input 48 is low, then transistor 46 is not conductive and the output node 16 is maintained at or near the voltage to which it was previously precharged.
As is apparent from the above description, output node 16 of the INVERTER circuit 38 has a voltage that is either close to the lower voltage on the clock line or close to the higher voltage on the clock line. Transistor 42 handles the case in which the voltage on the output node 16 is close to the lower voltage on the clock line 14, at the start of the precharge phase. Transistor 44 handles the case in which the voltage on the output node 16 is close to the higher voltage one clock line 14, at the start of the precharge phase.
If the voltage on the output node 16 is close to the lower voltage on the clock line, i.e., close to zero volts, at the start of the precharge phase, and the voltage on the clock line 14 during the precharge phase is a logic high, approximately equal to the positive supply voltage, then the channel of transistor 40 becomes conductive, because there is sufficient source-to-gate voltage Vsg, which is taken as positive in the direction of source to gate. The source node of transistor 40 is at a logic high, and the gate is approximately one threshold voltage, Vtn, above the voltage at the output node, i.e., Vout+Vtn, where Vtn is the threshold voltage for an NMOS transistor. For example, if the output node 16 is zero volts, then the voltage on the gate of 40 is approximately a threshold voltage Vtn for an n-channel device, because 44 is a diode-connected transistor. If, in one embodiment, Vtn for an NMOS transistor and Vtp are each about one volt, then the gate of 40 is approximately 1 volt. If, in this embodiment, the positive supply voltage is 5 volts, then the source-to-gate voltage for the PMOS transistor 40 is about +4 volts, which is greater than the threshold voltage Vtp. Thus, under the above conditions, transistor 40 has a conducting channel between the clock line 14 and the output node 16. This conducting channel allows the output node 16 to charge from clock line 14. As the output node rises towards the logic high voltage of the clock line 14, the channel of transistor 42 becomes less conductive and cuts off at the point when the output voltage is approximately an n-channel threshold voltage Vtn higher than the gate of 40. At this voltage, transistor 44 begins to help maintain the source-to-gate Vsg drive of transistor 40, by holding the gate voltage of transistor 40 at approximately Vtp below the output voltage Vout, i.e., at Vout−Vtp. Thus, transistor 44 helps to assure that the gate of transistor 40 cannot rise so far as to diminish the transistor 40's source-to-gate voltage, approximately Vout−Vtp, that is necessary for maintaining conduction of transistor 40.
It should be noted that if the output node 16 is charged to the logic high voltage of the clock line 14, then channel of transistor 46 cannot conduct during the precharge phase because there is insufficient gate-to-source voltage, no matter which terminal of transistor 46 is considered the source node and regardless of the state of the input 48 to transistor 46.
During the evaluation phase, transistor 40 is non-conducting regardless of the state of the output node 16. If the state of the output node stays charged during the evaluation phase, because the logic path is non-conducting, the drain-to-gate voltage Vdg of transistor 40 is V′out−Vg, where V″out is close to, but slightly less than, the logic high voltage of the clock line, and Vg is the gate voltage from the previous precharge cycle. Though the source terminal of transistor 40 has a voltage of approximately zero volts, the voltage Vdg=V′out−Vg between the drain and gate of transistor 40 is not sufficient to cause transistor 40 to conduct from output 16 to clock line 14, because it is less than the threshold voltage Vtp of transistor 40, i.e., Vdg=Vtp−(Vout−V′out), and V′out is slightly less than Vout.
If the output node was previously discharged, then the gate of transistor 40 is at approximately Vout+Vtn, where Vout is close to the logic low voltage of the clock line 14, and both the source-to-gate voltage and drain-to-gate voltage for transistor 40 have the incorrect polarity for conduction between the clock line 14 and the output node 16.
Thus, the device of
Compared to a traditional logic inverter, the circuit 38 of
In the energy storage circuitry 262, there are two capacitors Co′ 252a and C1 252b, where C1 is much smaller than Co′, The junction between the two provides a point of control for the initialization circuitry 264.
The initialization circuitry 264 includes an inverter circuit 254 that is connected to the output of the energy storage circuitry 262 and the junction of the C1 252b and Cc′ 252a capacitances. A reset line 202 controls whether the inverter 254 has a high-impedance output or a low impedance output, which is the inversion of the input. When the reset line 202 is active, the inverter 254 is in the low impedance output state, which causes the energy storage circuit 262 to oscillate. When the reset line 202 is deactivated, the inverter 254 changes to a high-impedance output and the resonant circuit continues to oscillate on its own with a frequency that is controlled by C1, Co′, Ceff and the output, Cx, of the tuning circuit.
As mentioned above, the control circuitry 260 includes a phase detector 256 and a tuning circuit 258 that together cause the frequency of the energy storage circuitry oscillations to be equal to the reference clock 274. Phase detector 256 receives the reference clock 274 and the output X2 of the energy storage circuitry 262, compares the two to control the tuning circuit 258 that modifies the frequency of the energy storage circuitry 262 to be the same as frequency of the reference clock 274.
Adaptive circuitry 266 is also connected to the output X2 of the energy storage circuitry 262 to replenish energy that is dissipated in the logic circuitry 268, modeled as an effective resistance Reff and effective capacitance Ceff.
In operation, the energy storage circuitry 262 begins oscillating at it natural resonant frequency after the deactivation of the reset line 202. The natural resonant frequency is related inversely to the square root of the product of L and the value of (Co′∥C1∥Ceff), where ‘x∥y’ is defined as the quantity xy/(x+y). If C1′ is much smaller than the other capacitances, then it is the capacitance that influences the natural resonant frequency the most (because (Co′∥C1∥Ceff) is approximately equal to C1′). Once started, the energy storage circuitry is then locked to the reference clock input by the phase detector 256 and tuning circuit 258. The phase detector 256 detects a phase difference between the energy storage circuitry frequency and the reference clock and converts this difference into a signal Z that controls the tuning circuit 258. The tuning circuit 258 then alters the oscillation frequency of the energy storage circuitry 262 by adding either inductance or capacitance into the energy storage circuitry 262 so as to drive the phase difference towards zero. If the amplitude of the oscillations of the energy storage circuit begin to diminish in amplitude, then adaptive circuitry 266 is activated to provide a synchronous energy boost to the oscillations, thereby restoring the amplitude.
Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.
Claims
1. A logic circuit comprising:
- a discharge path connected between a first node and a second node, the discharge path being operative using energy flowing from the second node to the first node to evaluate a logic function of at least one input during an evaluation phase;
- a precharge path connected between the first node and the second node and being conductive during a precharge phase so as to transfer energy from the first node to the second node; and
- a control circuit having an output connected to the precharge path, the control circuit being operative to establish and maintain the conductivity of the precharge path during the precharge phase independent of the states of the at least one input and the output node.
2. A logic circuit as recited in claim 1, wherein the evaluation phase occurs when a signal on the first node is at a first voltage and the precharge phase occurs when the signal on the first node is at a second voltage.
3. A logic circuit as recited in claim 2, wherein the first voltage is a logic low and the second voltage is a logic high.
4. A logic circuit as recited in claim 1, wherein a signal applied to the first node determines a time for the evaluation phase and a time for the precharge phase.
5. A logic circuit as recited in claim 1,
- wherein a signal applied to the first node is a periodic signal whose period includes a first phase and a second phase; and
- wherein the first phase is the evaluation phase and the second phase is the precharge phase.
6. A logic circuit as recited in claim 1, wherein the first node is connected to an energy storage circuit that captures any energy flowing from the second node to the first node during the evaluation phase and provides any energy that is transferred from the second node to the first node during the precharge phase.
7. A logic circuit as recited in claim 6,
- wherein the energy storage circuit is a resonant circuit; and
- wherein the resonant circuit oscillates with a period that defines the precharge phase and the discharge phase.
8. A logic circuit as recited in claim 7, wherein the resonant circuit period is synchronous to a reference clock period.
9. A logic circuit as recited in claim 1,
- wherein the precharge path is a PMOS transistor, said transistor having a gate, source and drain, and a channel defined between the source and drain, the channel of the PMOS transistor being connected between the first and second nodes and made conductive during the precharge phase; and
- wherein the control circuit includes a pair of complementary diode-connected transistors, each said transistor having a source, drain and channel defined therebetween, the sources of said transistors being connected to the second node and the drains being connected to the gate of the PMOS transistor of the precharge path.
10. A logic circuit as recited in claim 1,
- wherein the logic function is an AND function of two inputs; and
- wherein the discharge path includes a pair of NMOS transistors, each said transistor having a gate, source, and drain, and a channel between the source and drain, the channels of the NMOS transistors being connected in series, and the series connected channels being connected between the first and second nodes, each gate of said pair of transistors being connected to one of the two inputs, and
- wherein said discharge path is operative to transfer energy from the second node to the first node when the both inputs are at a logic high during the evaluation phase.
11. A logic circuit as recited in claim 1,
- wherein the logic function is an OR function of two inputs; and
- wherein the discharge path includes a pair of NMOS transistors, each said transistor having a gate, source, and drain, and a channel between the source and drain, the channels of the NMOS transistors being connected in parallel, and the parallel-connected channels being connected between the first and second nodes, each gate of said pair of transistors being connected to one of the two inputs, and
- wherein said discharge path is operative to transfer energy from the second node to the first node when either of the two inputs is at a logic high during the evaluation phase.
12. A method of evaluating a logic function, comprising:
- providing a conductive path between a first node and a second node during a precharge phase to transfer energy between the first and second node, the first node being connected to energy storage circuitry that provides any energy to be transferred, the conductive path being established and maintained by a control circuit during the precharge phase; and
- evaluating a logic function of at least one input during an evaluation phase during which energy may flow between the second node and the first node, any said energy flowing being captured by the energy storage circuitry.
13. A method of evaluating a logic function, as recited in claim 12, wherein the energy storage circuitry is a resonant circuit.
14. A method of evaluating a logic function, as recited in claim 12, wherein the first node oscillates with a period that defines the precharge phase and the discharge phase.
15. A method of evaluating a logic function, as recited in claim 12, wherein the first node oscillates with a period that defines the precharge phase and the discharge phase and the period is synchronous to a reference clock.
Type: Application
Filed: Nov 7, 2005
Publication Date: Mar 16, 2006
Applicant: PicoNetics, Inc. (Fremont, CA)
Inventors: Lei Wang (Sunnyvale, CA), Qiang Li (Fremont, CA), Jianbin Wu (Fremont, CA)
Application Number: 11/269,776
International Classification: H03K 19/096 (20060101);