CHEMICAL MECHANICAL POLISHING PROCESS

Abstract

A first substrate and second substrate both having thereon a top bulk metal layer and a lower barrier layer are prepared. The first substrate is first loaded onto a first platen of a CMP tool, and then an upper portion of the top bulk metal layer of the first substrate is removed by first platen and first slurry. The first substrate is then transferred to a second platen having second slurry. The second substrate is loaded onto the first platen. Simultaneously, the remaining top bulk metal layer of the first substrate and an upper portion of top bulk metal layer of the second substrate are removed at substantially the same copper removal rate until the lower barrier layer of the first substrate is exposed. The first substrate is transferred to a third platen having third slurry for polishing the exposed barrier layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 10/711,392 filed Sep. 16, 2004.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductor manufacturing, and more particularly, to a copper/barrier chemical mechanical polishing (CMP) process.

2. Description of the Prior Art

In the process of fabricating integrated circuits, it is necessary to periodically planarize the wafer surface. One technique for planarizing the surface of a wafer is chemical mechanical polishing (CMP). In CMP processing, a wafer is placed face down on a rotating platen. The wafer, held in place by a carrier or polishing head, independently rotates about its own axis on the platen. Typically, the head is a floating polishing head with a flexible membrane. On the surface of the platen is a polishing pad over which there is dispensed a layer of aqueous polishing slurry. Ordinarily, the slurry chemistry, which is essential to proper polishing, consists of a colloidal solution of silica particles in a carrier solution.

Copper damascene or copper dual damascene technique combined with copper CMP are known in the art. In a conventional copper dual damascene process, a dielectric layer is deposited onto a substrate, patterned, and etched back such that trenches, vias, and other recessed regions etched into the dielectric layer represent the desired metal interconnection pattern. Barriers and copper are then sequentially deposited/sputtered over the entire surface of the device, filling the recessed regions and blanketing the surface of the dielectric layer. The bulk copper layer and barrier layer are then polished back to a degree such that the Cu/barrier structure becomes electrically isolated within the recessed regions etched out of the dielectric material. For reliability concerns, the aforesaid bulk copper layer is not removed or buffed off in one step, but usually in two steps with different removal rates, according to the prior art.

FIG. 1 depicts a cross-sectional view of a semiconductor wafer 10 having a typical dual damascene structure therein. As shown in FIG. 1, the dual damascene structure formed within a dielectric layer 20 is composed of via hole 22 and trench 23. A conductive layer or an underlying device 14 is formed in a dielectric layer 12 beneath via hole 22. A chemical mechanical polished copper layer 24 fills the trench 23 and via hole 22. A barrier layer 25 is disposed on interior surface of the dual damascene structure to avoid copper diffusion, which usually causes a leakage current.

U.S. Pat. No. 6,573,173 to Farkas et al. discloses a method for forming a copper interconnection using a multi-platen CMP process. The method taught in this patent includes the steps of (1) forming an interconnect material comprising a top bulk metal layer and a lower barrier layer over a semiconductor substrate; (2) polishing an upper portion of the bulk metal layer at a first removal rate (at least 1000 angstroms per minute) using a first platen (ex. IC 1000 or IC 1010 from Rodel); (3) polishing remaining lower portion (<2000 angstroms) of the bulk metal layer using a second platen at a second removal rate that is smaller than the first removal rate; and (4) polishing the barrier layer using a third platen. According to this patent, the second platen is different from the first platen.

However, the above-described prior art copper CMP process has shortcomings. First, to avoid slurry cross-contamination, a wet cleaning process is recommended and is performed at a station located between the first platen and the second platen. Secondly, in order to maximize the throughput of the system, it is important to keep the polishing time of Step 1 approximately equal to the polishing time of Step 2. A computer coupled to the CMP tool for monitoring polishing times of Step 1 and Step 2 is thus required to achieve the purpose of balancing the polishing times between the two polishing steps. Further, the use of high down force in Step 1 might cause crushing or scratching of the underlying porous low-k dielectrics.

In light of the foregoing, there is a constant need in this industry to provide an improved copper CMP process with sufficient reliability and higher throughput.

SUMMARY OF INVENTION

It is a primary objective of the present invention to provide an improved copper/barrier CMP process to solve the above-described prior art problems.

According to the claimed invention, a high-throughput chemical mechanical polishing process utilizing a two-platen system is disclosed. A substrate having thereon a top bulk metal layer and a lower barrier layer is prepared. The top bulk metal layer is polished at a substantial constant removal rate to expose the barrier layer by utilizing a first platen and first slurry being selective to the barrier layer. The exposed barrier layer is then polished by a second platen and second slurry. The first slurry has a copper to barrier polishing selectivity of greater than 30, preferably above 100.

In accordance with another preferred embodiment of the present invention, a high-throughput chemical mechanical polishing process utilizing a three-platen system is disclosed. A first substrate and second substrate both having thereon a top bulk metal layer and a lower barrier layer are prepared. The first substrate is first loaded onto a first platen of a CMP tool, and then an upper portion of the top bulk metal layer of the first substrate is removed by first platen and first slurry. The first substrate is then transferred to a second platen having second slurry. The second substrate is loaded onto the first platen. Simultaneously, the remaining top bulk metal layer of the first substrate and an upper portion of top bulk metal layer of the second substrate are removed at substantially the same copper removal rate until the lower barrier layer of the first substrate is exposed. The first substrate is transferred to a third platen having third slurry for polishing the exposed barrier layer.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram illustrating an enlarged cross-sectional view of a portion of a semiconductor wafer having a typical dual damascene structure therein;

FIG. 2 is a schematic diagram illustrating a cross section of a substrate disposed thereon a top bulk copper layer and a lower barrier layer prior to the performance of the present invention CMP method;

FIG. 3 is a flow chart showing the salient steps of the CMP process in accordance with this invention;

FIG. 4 and FIG. 5 are schematic cross-sectional diagrams illustrating the interconnect structures represented at various stages of processing in accordance with FIG. 3; and

FIG. 6 is a flow chart showing the salient steps of the CMP process in accordance with another preferred embodiment of this invention.

DETAILED DESCRIPTION

The present invention is directed to a method of forming reliable interconnects of integrated circuits, more specifically to a copper/barrier chemical mechanical polishing process applied during the back end fabrication of integrated circuits with inlaid copper interconnects. It is to be understood that the term “copper” used hereinafter means copper or any suitable copper alloys known in the art unless otherwise indicated. The advantages of this invention at least include an improved throughput and relatively lower cost at the stage of CMP.

For the purpose of explanation, referring initially to FIG. 2, a cross section of a substrate or semiconductor wafer 100 is demonstrated. As indicated, a top bulk copper layer 240 and a lower barrier layer 210 are disposed thereon prior to the performance of the present invention CMP method. As shown in FIG. 2, the barrier layer 210 is formed on the interior surface of a recessed damascene region 250 and on the uppermost surface areas 260 of the dielectric layer 200. Examples of the barrier layer 210 include tantalum, tantalum nitride, titanium, titanium nitride, nickel nitride or the like. The dielectric layer 200 may comprise any suitable low-k dielectrics known in the art (dielectric constant k<3), and a layer of capping material 202 laminated at its top. The capping material 202 may be silicon carbide or silicon nitride, but not limited thereto. The thickness of the top bulk copper layer 240 is preferably greater than 2000 angstroms.

The recessed damascene region 250 includes but not limited to a trench 230 and via 220 communicating with the trench 230. It is understood that in another case a single damascene structure such as a single via or single trench may apply. Via 220 communicates with an underlying device 140 that is insulated by the dielectric layer 120. The underlying device 140 may be a metal interconnect. In another embodiment, the underlying device 140 may be, for example, a poly gate of a MOS device or a diffusion region implanted into a semiconductor body.

Please refer to FIG. 3 and briefly back to FIG. 2. FIG. 3 is a flow chart showing the salient steps of the CMP process according to one preferred embodiment of this invention. In Step 310, the substrate 100 to be polished as set forth in FIG. 2 is loaded onto a carrier of a CMP tool that may be commercial available from Applied Materials, Inc. For example, the CMP tool may be a Mirra CMP system. According to this embodiment, the CMP tool is equipped with two platens such as IC 1000 or IC 1010 CMP pad manufactured by Radel.

Next, in Step 320, the top bulk copper layer 240 of the substrate is polished using a first platen over which there is dispensed a first slurry that is selective to the underlying barrier layer 210. It is worthy noted that the copper removal rate in Step 320 is kept at a substantial constant in the range of about 3000 angstroms per minute to 12,000 angstroms per minute (high removal rate). By doing this, CMP throughput is improved. The first slurry may be alumina-based slurry or silica-based slurry. Most importantly, the first slurry has a “copper to barrier selectivity” that is greater than 30, more preferably greater than 100. The aforesaid “copper to barrier selectivity” is defined as a ratio of the removal rate of copper to that of barrier. A typical down force ranging between 2 and 6 pounds per inch (psi) is applied between the wafer and the first platen. However, since high-selectivity slurry is used in Step 320, a higher down force or polishing pressure may be applied.

FIG. 4 demonstrates a schematic cross sectional view of the substrate 100 after the polishing step 320. As shown in FIG. 4, the top bulk copper layer 240 and any remaining copper residue on the barrier layer 210 are selectively removed.

Still referring to FIG. 3, in Step 330, a subsequent wafer rinse process is optionally performed in order to avoid cross contamination. Upon removal from the first platen, the substrate or wafer 100 may be rinsed with deionized water or any suitable wet cleaning chemistry when in transfer between the first platen and the second platen.

In Step 340, the exposed barrier layer 210 is polished by using a second platen and second slurry. The second slurry is preferably comprised of compositions capable of efficiently removing the barrier layer 210 at a relatively lower pressure (˜1 psi). Such slurry may be available from Rodel. It would be advantageous to have selective removal of the barrier layer 210 to capping material 202 and to copper 240 in the second step polishing. FIG. 5 demonstrates a schematic cross sectional view of the substrate 100 after the second polishing step 340. The barrier layer 210 is selectively removed, while the dishing of copper is minimized. In Step 350, the wafer or substrate 100 is subjected to subsequent cleaning process.

FIG. 6 is a flow chart showing the steps of the CMP process according to another preferred embodiment of this invention. First, as indicated in Step 610, a first substrate to be polished as set forth in FIG. 2 is loaded onto a first platen of a CMP tool that may be commercial available from Applied Materials, Inc. equipped with three platens (the first and second platens are for copper polish, and the third platen is for barrier polish).

Next, in Step 620, the upper portion of the bulk copper layer (as indicated by numeral number 240 in FIG. 2) of the first substrate is removed by the first platen over which there is dispensed first slurry. Preferably, the copper removal rate in Step 620 is kept at a substantial constant in the range of about 3000 angstroms per minute to 12,000 angstroms per minute or so (high removal rate). The copper polish on the first platen is timed polish. Preferably, about half thickness of the bulk copper layer 240 is removed at the end point.

Next, in Step 630, the first substrate is transferred from the first platen to the second platen over which there is dispensed second slurry. Simultaneously, a second substrate as set forth in FIG. 2 is loaded onto the first platen. Between the first platen and the second platens, an optional rinse step may be provided. After the two substrates are both in position, polish of the remaining bulk copper (interfacial copper polish) of the first substrate (on the second platen) and polish of the upper portion of the bulk copper of the second substrate (on the first platen) begin. It is a salient feature of the present invention that the interfacial copper polish of the first substrate on the second platen and the bulk copper polish of the second substrate on the first platen are carried out at substantially the same copper removal rate within the high speed range as stated supra.

Preferably, the recipe of the first slurry and the recipe of the second slurry are substantially the same. The slurry on the first or second platen must have a “copper to barrier selectivity” that is greater than 30, more preferably greater than 100. As aforementioned, the “copper to barrier selectivity” is defined as a ratio of the removal rate of copper to that of barrier. Further, the first platen and the second platen are the same according to this embodiment.

In Step 640, the first substrate is polished on the second platen to a degree such that the barrier is exposed, and then the first substrate is transferred to the third platen over which there is dispensed third slurry that is different from the first or second slurry. At the same time, the second substrate is transferred to the second platen for interfacial copper polish following the previous steps of treating the first substrate, and a third substrate is now loaded onto the first platen. On the third platen, as indicated in Step 660, the barrier of the first substrate is removed. The interfacial copper polish of the second substrate on the second platen and the bulk copper polish of the third substrate on the first platen are carried out at substantially the same copper removal rate. Between the second platen and the third platens, an optional rinse step may be provided.

In accordance with another embodiment of this invention, a chemical mechanical polishing (CMP) process includes the following steps:

(1) Providing a first substrate and second substrate both having thereon a top bulk metal layer and a lower barrier layer.

(2) Loading the first substrate onto a first platen of a CMP tool, and polishing an upper portion of the top bulk metal layer of the first substrate on the first platen with a first polishing recipe setting a plurality of polishing conditions.

(3) Transferring the first substrate to a second platen and loading the second substrate onto the first platen.

(4) Simultaneously polishing remaining top bulk metal layer of the first substrate and polishing an upper portion of top bulk metal layer of the second substrate with a second polishing recipe substantially the same as the first polishing recipe until the lower barrier layer of the first substrate is exposed.

(5) Transferring the first substrate to a third platen having third slurry for polishing the exposed barrier layer.

The aforesaid polishing conditions include polishing pressure, flow rate of slurry, rotation rate of platen, and rotation rate of wafer. According to this invention, polishing conditions of the first polishing recipe are the same as those of the second polishing recipe.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A chemical mechanical polishing (CMP) process comprising:

providing a first substrate and second substrate both having thereon a top bulk metal layer and a lower barrier layer,

loading said first substrate onto a first platen of a CMP tool, and polishing an upper portion of said top bulk metal layer of said first substrate on said first platen and first slurry;

transferring said first substrate to a second platen having second slurry and loading said second substrate onto said first platen, wherein said second slurry has a copper to barrier polishing selectivity of greater than 30;

simultaneously polishing remaining top bulk metal layer of said first substrate and polishing an upper portion of top bulk metal layer of said second substrate at substantially the same copper removal rate until said lower barrier layer of said first substrate is exposed; and

transferring said first substrate to a third platen having third slurry for polishing said exposed barrier layer.

2. (canceled)

3. The chemical mechanical polishing process according to claim 1 wherein said second slurry has a copper to barrier polishing selectivity of above 100.

4. The chemical mechanical polishing process according to claim 1 wherein said second slurry contains alumina.

5. The chemical mechanical polishing process according to claim 1 wherein said third slurry contains alumina.

6. The chemical mechanical polishing process according to claim 1 wherein said second slurry contains silica.

7. The chemical mechanical polishing process according to claim 1 wherein said third slurry contains silica.

8. The chemical mechanical polishing process according to claim 1 wherein said first slurry and said second slurry have substantially the same recipe.

9. The chemical mechanical polishing process according to claim 1 wherein said first platen and said second platen are substantially the same.

10. The chemical mechanical polishing process according to claim 1 wherein said third slurry is different from said first slurry or second slurry.

11. A chemical mechanical polishing (CMP) process comprising:

providing a first substrate and second substrate both having thereon a top bulk metal layer and a lower barrier layer;

loading said first substrate onto a first platen of a CMP tool, and polishing an upper portion of said top bulk metal layer of said first substrate on said first platen with a first polishing recipe setting a plurality of polishing conditions;

transferring said first substrate to a second platen and loading said second substrate onto said first platen;

simultaneously polishing remaining top bulk metal layer of said first substrate and polishing an upper portion of top bulk metal layer of said second substrate with a second polishing recipe substantially the same as said first polishing recipe until said lower barrier layer of said first substrate is exposed; and

transferring said first substrate to a third platen having third slurry for polishing said exposed barrier layer.

12. The chemical mechanical polishing process according to claim 11 wherein said plurality of polishing conditions include a polishing pressure, a flow rate of slurry, a rotation rate of platen, and a rotation rate of wafer.

13. The chemical mechanical polishing process according to claim 12 wherein said plurality of polishing conditions of said first polishing recipe are the same as those of said second polishing recipe.