Inrush current control system with soft start circuit and method
A method of and system for controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain. The dV/dt at the drain of the MOSFET is controlled so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET so that the MOSFET can turn on and off more quickly.
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This application is a continuation-in-part of our previous application entitled HOT SWAP INPUT CURRENT CONTROL SYSTEM WITH SOFT START CIRCUIT AND METHOD, filed Apr. 11, 2005, and accorded U.S. Ser. No. 11/102,863.
FIELD OF THE INVENTIONThe present disclosure generally relates to circuits for limiting inrush current, and more particularly to an inrush current control system with a soft start circuit, and methods of controlling the inrush current of a control system as a function of the ramp rate of a soft start voltage.
BACKGROUND OF THE DISCLOSURE When circuit boards are inserted into live backplanes (typically at −48V), the input of a board's power module or switching power supply (or bypass capacitors if provided) can draw huge transient currents as they charge up. The transient currents can cause permanent damage to the board's components and glitches on the system power supply. By limiting inrush current caused by transient effects one protects the board from excessive current spikes. Three commercially available circuits for limiting inrush current are shown in
In
In a second controller shown in
A third circuit shown in
In accordance with one aspect of the current disclosure, the method of a system for and method of controlling the inrush current generated in a MOSFET of an inrush current control is disclosed. The method and system control the dV/dt at the drain of the MOSFET so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET.
In accordance with another aspect of the present disclosure a system for and method of controlling the turn on output current of an inrush current control system is disclosed. The system and method are designed to control the dV/dt at the drain of a FET so as to set the inrush current through the FET as a function of dV/dt; and control the dI/dt of the turn on output current as a function of the ramp rate of a soft start voltage produced at an input of the control system when the control system is turned on.
In accordance with one disclosed embodiment a ramp voltage is generated at the drain of the MOSFET when the voltage on the gate of the MOSFET is sufficient for the MOSFET to turn on.
In accordance with one disclosed embodiment the inrush current control system includes a component coupled to the drain of the MOSFET, such that a ramp voltage is generated at the drain of the MOSFET and the inrush current is limited. The component can include a capacitive or/and a resistive element coupled to the drain of the MOSFET.
In accordance with one disclosed embodiment wherein the current is limited through the MOSFET during an over current condition, and/or during an output short event.
In accordance with one disclosed embodiment the rate of rise of the inrush current, dI/dt is also controlled.
In accordance with one disclosed embodiment over current protection is provided without affecting the inrush current.
In accordance with one disclosed embodiment the inrush current control system includes a current input, and a ramp pin output, the ramp pin output being coupled to the drain of the MOSFET, and the voltage at the ramp pin is held during power up or power step conditions.
In accordance with another aspect of the present disclosure a system for and method of controlling the turn on output current of an inrush current control system is disclosed. The system and method are designed to control the dV/dt at the drain of a FET so as to set the inrush current level through the FET as a function of dV/dt; and control the dI/dt of the inrush current as a function of the ramp rate of a soft start voltage produced at an input of the control system when the control system is turned on.
In accordance with one disclosed embodiment the soft start voltage is clamped to a predetermined value.
In accordance with one disclosed embodiment the soft start voltage limit is established by a clamping circuit.
In accordance with one disclosed embodiment the inrush current control system includes a capacitor coupled to the drain, and a ramp current is generated through the capacitor to the drain of the FET as a function of the soft start voltage. In accordance with one disclosed embodiment, the capacitor is configured so that the FET can turn off independently of the value of the capacitor.
BRIEF DESCRIPTION OF THE DRAWINGSReference is made to the attached drawings, wherein elements having the same reference character designations represent like elements throughout, and wherein:
A preferred embodiment of the inrush current control system is shown in
The output of the amplifier 66 is connected to the base of the bipolar transistor (Q5) 72. The emitter of transistor (Q5) 72 is connected to the inverting input of the amplifier 66, and to the resistor (R5) 74. The latter in turn is connected to system ground (VEE) 58. The collector of the transistor (Q5) 72 is connected to the drain of MOSFET (MP1) 76, which forms a part of a current mirror, the latter preferably including MOSFETs (MP1) 76, (MP2) 78 and (MP3) 80. Each of the MOSFETs (MP1) 76, (MP2) 78 and (MP3) 80 has its source connected to the voltage rail 64, and its gates connected together. The gate of the MOSFET (MP1) 76 is connected to its drain and the collector of the transistor (Q5) 72. The MOSFET (MP2) 76 has its drain connected to the collector and base of the bipolar transistor (Q3) 82, which in turn has its emitter connected through the resistor (R3) 84 to the collector and base of the bipolar transistor (Q1) 86. The emitter of transistor (Q1) 86 is connected through resistor (R1) 88 to system ground (VEE) 58.
The drain of the MOSFET (MP3) 80 is connected to the (GATE) terminal 54 and to the collector of bipolar transistor (Q4) 90. The latter has its collector tied to the base and collector of the transistor (Q3) 82. The emitter of transistor (Q4) 90 is connected through resistor (R4) 92 to the (RAMP) terminal 56, and to the collector and base of the bipolar transistor (Q2) 94. The emitter of transistor (Q2) is connected to through the resistor (R2) 96 to system ground (VEE) 58. The (RAMP) terminal 56 is also connected to the cathode of the clamping circuit 98, which is illustrated as a Zener diode having its anode connected to system ground (VEE) 58. The clamping circuit 98 holds the (RAMP) terminal close to the regulated 1V level during input voltage step.
The (GATE) terminal 54 is connected to the gate of the MOSFET 100 of an external circuit (external to the integrated circuit) and through capacitor (CG) 102 to system ground (VEE) 58. The source of MOSFET 100 is connected through resistor (RS) 104 to system ground (VEE) 58. The drain of the MOSFET 100 is connected through capacitor (CL) 106 to a voltage source (RTN) 108, and to one plate of capacitor (CR) 110. The other plate of the capacitor (CR) 110 is connected through resistor (RR) 112 to the (RAMP) terminal 56. The (RAMP) terminal 56 is also connected through capacitor (CR2) 114 to system ground SEE) 58.
In addition to the foregoing the preferred inrush current control system includes two over-current protection components besides the inrush control circuits, both preferably provided as a part of the integrated circuit 50. The two over-current protection components preferably includes an active current limit (ACL) amplifier 116 having its inverting input connected to sense voltage from the source of the MOSFET 100, its output connected to the cathode of diode 120 (which in turn has its anode connected to the gate terminal 54) and its non-inverting input connected to a 50 mV source so that the amplifier serves as a circuit breaker comparator with an input threshold of 50 mV. The other over-current protection component preferably includes a fast pull down (FSTPULDN) comparator 118 having its inverting input also connected to receive the sensed voltage from the source of the MOSFET 100, its output connected to the cathode of diode 122 (which in turn has its anode connected to the gate terminal 54) and its non-inverting input connected to an input threshold of 150 mV.
In operation, FET 100 turn-on starts when the system is connected to a power supply and the switch (S) 62 is closed (at time to as shown in
The voltage applied across the capacitor (CSS) 70 will thus generate a GATE current (IGATE) at the terminal 54 for GATE pull-up. When the GATE voltage at (GATE) terminal 54 reaches the threshold voltage of the MOSFET 100 (at t1 in
IINRUSH=IRAMP·CL/CR (1)
The capacitor CR2 and the resistor RR are used to filter the noise at the RAMP terminal 56 and each are optional.
When'the DRAIN is ramped down to VEE, IRAMP drops to 0 (at t3 in
dVSS/dt=ISS/Css; (2)
dVSS/dt·1/R5=dIRAMP/dt=ISS/(CSS·R5); (3)
and
dIINRUSH/dt=(dIRAMP/dt)·(CL/CR)=(ISS·CL)/(CSS·R5·CR) (4)
The exemplary embodiment thus sets the IINRUSH current by a capacitor CR between the DRAIN and a dedicated RAMP terminal that is regulated separately from the GATE of the FET 100. The advantages of this approach include (1) it does not require a large CG that relates to CR so the turn-off of the FET 100 can be fast even for large load applications; and (2) it incorporates a soft start technique that controls the dI/dt of the IINRUSH current. Other advantages will be will be evident to those skilled in the art.
Used in conjunction with the over-current protection components (ACL amplifier 116 and FSTPULDN comparator 118) as shown in
It should be noted that the capacitor (CR) of the
Further, the component(s) connected between the RAMP terminal 56 and the DRAIN of the MOSFET 100 (shown as a capacitor CR 110 and resistor 112, although in some instances only one of those components are necessary) are used to generate a ramp signal (current) from the DRAIN of the MOSFET 100 (or output voltage) so as to limit the inrush current flowing through the MOSFET 100.
Thus, the method of and system for controlling the dI/dt of an inrush output current of a inrush current control system provided in accordance with the present disclosure have been described. The exemplary embodiment described in this specification have been presented by way of illustration rather than limitation, and various modifications, combinations and substitutions may be effected by those skilled in the art without departure either in spirit or scope from this disclosure in its broader aspects and as set forth in the appended claims.
The system and method of the present disclosure as disclosed herein, and all elements thereof, are contained within the scope of at least one of the following claims. No elements of the presently disclosed system and method are meant to be disclaimed, nor are they intended to necessarily restrict the interpretation of the claims.
Claims
1. A method of controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain, the method comprising:
- controlling the dV/dt at the drain of the MOSFET so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET.
2. A method according to claim 1, wherein the inrush current control system includes a current input, a gate pin output and a ramp pin output, the ramp pin output being coupled to the drain of the MOSFET, and the gate pin output being coupled to the gate of the MOSFET,
- wherein the method further comprises:
- forcing current out of the ramp pin when the MOSFET is turned on.
3. A method according to claim 1, wherein the inrush current control system includes a component coupled to the drain of the MOSFET, and
- the step of controlling the dV/dt at the drain of the MOSFET includes:
- generating a ramp current through the component so as to generate a ramp voltage at the drain of the MOSFET and limit the inrush current.
4. A method according to claim 3, wherein the step of generating a ramp current includes generating a ramp current through a capacitive element coupled to the drain of the MOSFET.
5. A method according to claim 3, wherein the step of generating a ramp current includes generating a ramp current through a resistive element coupled to the drain of the MOSFET.
6. A method according to claim 1, the method further comprising:
- limiting the current through the MOSFET during an over current condition.
7. A method according to claim 1, the method further comprising:
- limiting the current through the MOSFET during an output short event.
8. A method according to claim 1, wherein the step of controlling the dV/dt at the drain, also includes controlling the rate of rise of the inrush current, dI/dt.
9. A method according to claim 1, wherein the inrush current control system includes a current input, and a ramp pin output, the ramp pin output being coupled to the drain of the MOSFET,
- the method further comprising:
- holding the voltage at the ramp pin during power up or power step conditions.
10. A method of controlling the turn on output current of an inrush current control system, comprising:
- controlling the dV/dt at the drain of a FET so as to set the inrush current level of the FET as a function of dV/dt; and controlling the dI/dt of the turn on output current as a function of the ramp rate of a soft start voltage produced at an input of the control system when the control system is turned on.
11. A method according to claim 10, further including
- clamping the soft start voltage to a predetermined value.
12. A method according to claim 11, wherein
- clamping the soft start voltage to a limit includes establishing the limit by a clamping circuit.
13. A method according to claim 10, wherein the inrush current control system includes a capacitor connected in between a soft short input pin and a voltage level source VEE,
- wherein the method further includes
- generating a ramping current to turn on the FET as a function of the voltage at the soft short input pin.
14. A method according to claim 10, wherein the inrush current control system includes a capacitor coupled to the drain,
- wherein the method further includes
- generating the inrush output current through the FET,
- wherein the capacitor is configured so that the FET can turn off independently of the value of the capacitor.
15. A circuit configuration for controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain, the circuit configuration comprising:
- a control circuit configured and arranged so that the dV/dt at the drain of the MOSFET sets the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET.
16. A circuit configuration according to claim 15, wherein the control circuit includes a current input, a gate pin and a ramp pin output, wherein the ramp pin is coupled to the drain of the MOSFET, and wherein a ramp voltage is generated at the drain of the MOSFET when the voltage on the gate of the MOSFET is sufficient for the MOSFET to turn on.
17. A circuit configuration according to claim 15, wherein the inrush current control system includes a component coupled between the ramp pin and the drain of the MOSFET, and the control circuit generates a ramp current through the component so as to generate a ramp voltage at the drain of the MOSFET and limit the inrush current.
18. A circuit configuration according to claim 17, wherein the component is a capacitive element coupled to the drain of the MOSFET.
19. A circuit configuration according to claim 17, wherein the component is a resistive element coupled to the drain of the MOSFET.
20. A circuit configuration according to claim 15, further comprising:
- a current limiter coupled to the MOSFET and configured so as to limit the current through the MOSFET during an over current condition.
21. A circuit configuration according to claim 15, further comprising:
- a current limiter coupled to the MOSFET and configured so as to limit the current through the MOSFET during an output short event.
22. A circuit configuration according to claim 15, wherein the control circuit configured and arranged so that the dV/dt at the drain of the MOSFET sets the inrush current level as a function of dV/dt is further configured and arranged so as to control the rate of rise of the inrush current, dI/dt.
23. A circuit configuration according to claim 22, further including an over current protection subcomponent configured and arranged so as to provide over current protection with respect to the inrush current.
24. A circuit configuration according to claim 15, further including a current input, and a ramp pin output, the ramp pin output being coupled to the drain of the MOSFET such that the voltage at the ramp pin is held at a relatively constant value during power up or power step conditions.
25. A circuit configured and arranged so as to control the turn on output current of an inrush current control system, comprising:
- a control circuit configured and arranged so as to control the dV/dt at the drain of a FET so as to set the inrush current level through the FET as a function of dV/dt; and control the dI/dt of the turn on output current as a function of the ramp rate of a soft start voltage produced at an input of the control circuit when the control system is turned on.
26. A circuit according to claim 25, further including
- a voltage clamp configured and arranged so as to clamp the soft start voltage to a predetermined value.
27. A circuit according to claim 25, further including a soft start pin and a capacitor coupled between the soft start pin and a voltage source VEE, the circuit being configured and arranged so that a ramp current is generated through the capacitor as a function of the voltage at the soft start pin.
28. A method according to claim 25, wherein the inrush current control system includes a capacitor coupled to the drain, and the inrush control system is configured and arranged so that the FET can turn off independently of the value of the capacitor.
Type: Application
Filed: Jun 16, 2005
Publication Date: Oct 12, 2006
Applicant:
Inventors: James Herr (San Jose, CA), Zhizhong Hou (Fremont, CA), Christopher Umminger (Mountain View, CA)
Application Number: 11/153,680
International Classification: H02H 3/08 (20060101);