Apparatus for conducting heat in a flip-chip assembly
An apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein, is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond layer and to electrically communicate with the semiconductor device. The heat produced from the semiconductor device and thermally conducting through the conductive pads is thermally conducted to the heat sink or diamond layer and away from the interconnections, i.e., solder bump connections, between a semiconductor device and a carrier substrate in a flip-chip assembly. As a result, thermal fatigue is substantially prevented in a flip-chip assembly.
This application is a divisional of application Ser. No. 10/852,548, filed May 24, 2004, pending, which is a divisional of application Ser. No. 10/055,298, filed Jan. 23, 2002, now U.S. Pat. No. 6,861,745, issued Mar. 1, 2005, which is a divisional of application Ser. No. 09/885,615, filed Jun. 20, 2001, now U.S. Pat. No. 6,541,303, issued Apr. 1, 2003.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates generally to flip-chip semiconductor devices and, more specifically, the present invention relates to improved heat dissipation in flip-chip semiconductor devices.
2. State of the Art
Semiconductor devices inherently generate heat during operation which must be dissipated to maintain the semiconductor device at an acceptable operating temperature. As the operating speed of a semiconductor device increases, typically, the semiconductor device has increased power dissipation and increased heat generated. For example, high operating speed microprocessors tend to have higher power requirements and to generate more heat at the higher operating speeds.
Additional heat dissipation issues arise in the case where the semiconductor device is configured as a “flip-chip.” In a flip-chip configuration, the surface of a semiconductor die which has an electronic device formed therein directly opposes a die-attach substrate. The semiconductor die is typically attached to the die-attach substrate only by conductive bumps which lead to the bonding pads of the semiconductor die. Typically, electrical traces printed on the die-attach substrate lead from the bumps to provide interconnection to other circuit components.
The described flip-chip configuration gives rise to heat dissipation problems because most of the heat generated by a semiconductor device is generated at the active surface of the semiconductor die. In the flip-chip configuration, the active surface of the semiconductor die is sandwiched against a die-attach substrate, which is typically a ceramic insulator, a relatively poor heat-sink, having the space between the semiconductor die and the substrate filled with an underfill material to increase the strength of the connection between the semiconductor die and the substrate as well as to help prevent environmental attack of the electrical circuitry and connections to the substrate. As a result, the majority of the heat generated by a flip-chip semiconductor die is not efficiently dissipated. As such, the conductive bumps provide an extremely small surface area through which the heat must be dissipated, resulting in undesirable localized “hot points or hot spots,” which often result in thermal fatigue in the interconnections of the conductive bumps.
In an effort to prevent such localized hot points, U.S. Pat. No. 5,508,230 to Anderson et al. discloses a flip-chip assembly having improved heat dissipating capability. As shown in drawing FIGS. 1(a) and 1(b), the flip-chip semiconductor device assembly in the '230 Patent includes a diamond layer 16 over the active surface 14 of the semiconductor die 10 and a metalized pad 20 provided in a center portion over the top of the diamond layer 16. The solder bumps 22 are provided through openings 18 in the diamond layer 16. A die-attach substrate 12 is connected to the semiconductor die 10 so that the solder bumps 22 and the metalized pad 20 are directly contacting the die-attach substrate 12. In this manner, heat is dissipated across the diamond layer 16 and is drawn off the device into the metalized pad 20. Although the diamond layer 16 is an excellent conductor of heat, the heat may become trapped in the metalized pad 20, resulting in thermal fatigue between the semiconductor die 10 and substrate 12 since the metalized pad 20 abuts the substrate 12. Furthermore, the diamond layer 16 includes openings 18 for the solder bumps 22 to protrude therethrough, in which the solder bumps 22 have little, if any, contact with the diamond layer 16. This lack of structure contacting the solder bumps 22 results in the inability to effectively draw heat from the solder bumps 22 or localized hot points. Thus, heat dissipating through the solder bumps 22 will cause thermal fatigue in the solder bump interconnections between the semiconductor die 10 and substrate 12.
Therefore, it would be advantageous to provide a method and apparatus that transfer heat from a flip-chip assembly to limit the potential thermal fatigue to the semiconductor assembly.
BRIEF SUMMARY OF THE INVENTIONThe present invention relates to a method and apparatus for transferring heat from a flip-chip semiconductor device assembly to help limit and control any thermal fatigue of the flip-chip semiconductor device assembly. The present invention is directed to a method and apparatus for providing a heat sink that dissipates heat away from the semiconductor die of the assembly. The present invention includes a diamond layer overlying a surface of a semiconductor die for channeling heat from the semiconductor die in a semiconductor device assembly.
In one embodiment, the present invention includes a diamond layer deposited or formed on the active surface of a semiconductor die, the diamond layer having at least one opening therein. At least one bond pad formed on the active surface of the semiconductor die extends partially through the at least one opening in the diamond layer. According to the present invention, the diamond layer thermally conducts heat from the at least one bond pad of the semiconductor die being partially in contact therewith. Further, the diamond layer dissipates the heat away from the semiconductor die.
In another embodiment, the present invention includes a diamond layer having at least one opening or via therein deposited or formed over a surface, typically the active surface, of a semiconductor die. The diamond layer includes a trace formed therein for electrical communication between the semiconductor die and a contact pad formed in the opening or via in the diamond layer. In this embodiment, the diamond layer thermally conducts heat from the semiconductor die, the trace and the contact pad. In turn, the heat dissipates from the diamond layer.
In another embodiment, the present invention includes a semiconductor die having a surface, typically the active surface, with a first diamond layer, or film, deposited or formed thereon. Bond pads of the semiconductor die are exposed through the first diamond layer. A second diamond layer is formed over the first diamond layer having a passivation layer therebetween. A conductive trace is formed in the passivation layer to electrically communicate with the semiconductor die and a conductive pad provided in openings in the second diamond layer. According to the present invention, the conductive pad extends partially over and in contact with the second diamond layer to thermally conduct heat therefrom and, in addition, the first diamond layer directly contacts the active surface of the semiconductor die to thermally conduct heat therefrom. As a result, the present invention provides a method and apparatus for thermally conducting heat from a semiconductor device to prevent thermal fatigue in the interconnections therein.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGSThe method and apparatus of the present invention will be more fully understood from the detailed description of the invention when taken in conjunction with the drawings, wherein:
FIGS. 2(a)-2(i) are simplified partial cross-sectional views of a first embodiment, illustrating a method for repatterning the active surface of a semiconductor die to include a diamond layer thereon, in accordance with the present invention;
Embodiments of the present invention will be hereinafter described with reference to the accompanying drawings. It should be understood that the illustrations are not meant to be actual views of any particular apparatus and/or method, but are merely idealized representations which are employed to more clearly and fully depict the present invention than would otherwise be possible. Additionally, elements common between the figures retain the same numerical designation.
A method and apparatus of a first embodiment of the present invention are shown in drawing FIGS. 2(a) through 2(i). Illustrated in drawing
As shown in drawing
As shown in drawing
As shown in drawing
As shown in drawing
As shown in drawing
As the UBM structure 180 is formed from the metal layer 170, the UBM structure 180 also may comprise an adhesion layer and a solder wettable metal layer as previously set forth. The UBM structure 180 may be formed from the metal layer 170 as a laminate or composite by chemical vapor deposition (CVD), plasma enhanced CVD, or physical vapor deposition (PVD) such as sputtering, evaporation or otherwise, as known in the art. It should be noted that the present invention is not limited to any particular UMB metallurgy or to a multilayer UBM. The UBM structure 180 of the present invention may also be as described in U.S. Pat. No. 5,903,058, the disclosure of which is incorporated herein by this reference.
As shown in drawing
It has been determined in accordance with the present invention that diamond provides the best combination of thermal conductivity and electrical resistivity of available materials. Although the diamond layer 160 is preferred as a heat sink, other materials may be used such as silicon carbide, aluminum nitride, and/or aluminum oxide, which also provide high dielectric insulation but much less thermal conductivity than diamond. The only other materials providing similar thermal conductivity to that of diamond are electrically conductive metals such as copper and silver (diamond being approximately five times greater in thermal conductivity than copper), which are, of course, not useful in this particular aspect of the present invention due to their electrically conductive quality.
In the present invention, the methods used in depositing the diamond layer 160 typically include, but are not limited to, evaporation methods, laser-ablation methods, CVD methods, plasma enhanced CVD methods and PVD or sputtering methods. However, any method known to one of ordinary skill in the art may be employed in providing the diamond layer in the present invention. The diamond layer 160 provided may comprise crystal orientation of a single crystal or polycrystalline, or the diamond layer 160 may be amorphous. The diamond layer 160 may include but is not limited to other materials or layers such as hydrocarbons or organics, nitrogen, oxygen, etc. The diamond layer 160 may be doped with nitrogen and/or oxygen, or may include trace amounts of nitrogen and/or oxygen.
Therefore, according to the present invention, as shown in drawing
Thus, the heat produced in the semiconductor device in the flip-chip semiconductor device assembly 198 is channeled from the circuitry (not shown) in the substrate 110 through the bond pads 114, the trace 140 and through the partial contact area 182 of the UBM structure 180. Since diamond is a much greater heat sink than any type of conductive material, the majority of the heat is channeled from the partial contact area 182 of the UBM structure 180 to the diamond layer 160, rather than to the conductive bump 190. As such, the heat is drawn substantially uniformly across the diamond layer 160 to dissipate therefrom (illustrated by arrows in drawing
A second embodiment of the present invention is illustrated in drawing
The thick diamond layer 264 of the second embodiment may be desirable since diamond is not only a good dielectric insulator with excellent thermal conductivity but is a material which serves effectively as a passivation layer. As such, it is well appreciated that the thick diamond layer 264 thermally conducts heat from the elements it may have contact with, namely, the substrate 110, the bond pads 114, the conductive trace 140, and the UBM structure 180, as shown in drawing
An alternative to the second embodiment is illustrated in drawing
A third embodiment of the present invention is illustrated in drawing
An important aspect of the present invention in the third embodiment is the diamond film 360 having direct contact with the substrate surface 112, a portion of the trace 140, and a portion of the bond pad 114. In this manner, heat will be additionally channeled (in addition to that which the first embodiment provides) from the substrate surface 112, trace 140 and bond pad 114 through the diamond film 360 to dissipate therefrom, thereby further preventing the heat from thermally fatiguing the interconnections of the flip-chip semiconductor device packaging assembly 398.
It should be noted that if the diamond layer or layers, as discussed in the above preferred embodiments, are provided on a substrate that comprises a wafer or multiple dice, it may be preferable to provide an etching process to the diamond layer or layers so that the wafer or multiple dice having a diamond layer or layers thereon may be easily diced into predetermined individual semiconductor dice or multiple semiconductor dice. Such an etching process may be incorporated in the present invention during or in addition to the process of providing the openings or vias in the diamond layer as, for example, shown in drawing
Referring to drawing
While the present invention has been disclosed in terms of certain preferred embodiments and alternatives thereof, those of ordinary skill in the art will recognize and appreciate that the invention is not so limited. Additions, deletions and modifications to the disclosed embodiments may be effected without departing from the scope of the invention as claimed herein. For example, either the first diamond layer or the second diamond layer in the second embodiment may be replaced with a polyimide passivation layer. Similarly, features from one embodiment may be combined with those of another while remaining within the scope of the invention.
Claims
1. A semiconductor device assembly comprising:
- a substrate having a surface having a layer comprising a first layer and a second layer, the first layer comprising substantially diamond provided over at least a portion of the surface of the substrate having at least one aperture therein, and having at least one contact pad having a periphery, the at least one contact pad having at least a portion thereof extending at least partially over the first layer comprising substantially diamond adjacent the at least one aperture therein and having at least a portion thereof extending through the at least one aperture in the first layer comprising substantially diamond connected to at least one circuit on the substrate, a second layer comprising substantially diamond located between the substrate and the first layer comprising substantially diamond.
2. The assembly according to claim 1, further comprising:
- a passivation layer located between the first layer comprising substantially diamond and the second layer comprising substantially diamond.
3. The assembly according to claim 2, wherein the passivation layer has at least a portion of at least one trace located thereon to connect the substrate and the at least one contact pad.
4. The assembly according to claim 2, further comprising:
- a film comprising diamond formed between the passivation layer and the substrate, the film directly contacting the surface of the substrate.
5. The assembly according to claim 1, wherein the second layer includes a layer between the first layer and the second layer.
6. The assembly according to claim 5, wherein the second layer has at least one trace connecting the substrate and the at least one contact pad.
7. The heat sink according to claim 6, wherein the passivation layer includes at least a portion of one trace connecting the substrate and the at least one pad.
8. The heat sink according to claim 6, further comprising:
- a film including diamond formed between the passivation layer and the substrate, the film contacting the substrate.
9. The assembly according to claim 6, wherein the passivation layer comprises a second layer comprising substantially diamond located between a semiconductor device and the second layer comprising substantially diamond.
10. A semiconductor device assembly comprising:
- a semiconductor device having an active surface, having a layer comprising substantially diamond provided over at least a portion of the active surface of the semiconductor device having at least one aperture therein, and having at least one bond pad having a periphery located on the active surface, the at least one bond pad having at least a portion thereof extending at least partially over the layer comprising substantially diamond adjacent the at least one aperture therein and having at least a portion thereof extending at least through a portion of the at least one aperture in the layer comprising substantially diamond, the at least one bond pad connected to at least one circuit on the semiconductor device.
11. The assembly according to claim 10, further comprising:
- a second layer comprising substantially diamond located between the semiconductor device and the layer comprising substantially diamond.
12. The assembly according to claim 11, wherein at least one of the layer comprising substantially diamond and the second layer comprising substantially diamond has at least a portion of one trace located on a portion thereof to connect the substrate and the at least one bond pad.
13. The assembly according to claim 11, further comprising:
- a passivation layer located between the layer comprising substantially diamond and the second layer comprising substantially diamond.
14. The assembly according to claim 13, wherein the passivation layer has at least a portion of at least one trace located thereon to connect the substrate and the at least one bond pad.
15. The assembly according to claim 13, further comprising:
- a film comprising diamond formed between the passivation layer and the semiconductor device, the film directly contacting the active surface of the semiconductor device.
16. A semiconductor die assembly comprising:
- a semiconductor die having an active surface, a layer having at least one aperture therein, the layer including diamond provided substantially over a portion of the active surface of the semiconductor die, and at least one bond pad having at least a portion thereof extending at least partially over the layer and having a portion thereof extending at least into the at least one aperture in the layer; and
- a substrate having the semiconductor die attached thereto.
17. The assembly according to claim 16, further comprising:
- a second layer including diamond located between the semiconductor die and the layer.
18. The assembly according to claim 17, wherein at least one of the layer and the second layer has at least one trace connecting the semiconductor die and the at least one bond pad.
19. The assembly according to claim 18, further comprising:
- a passivation layer located between the layer and the second layer.
20. The assembly according to claim 19, wherein the passivation layer has at least one trace connecting the semiconductor die and the at least one bond pad.
21. The assembly according to claim 19, further comprising:
- a film including diamond formed between the passivation layer and the semiconductor die, the film contacting the active surface of the semiconductor die.
22. A heat sink disposed on a semiconductor device comprising:
- a layer including diamond disposed on at least a portion of an active surface of a semiconductor device, the layer including at least one opening therein; and
- at least one bond pad located on at least a portion of the active surface of the semiconductor device, the at least one bond pad having a portion thereof extending over at least a portion of the layer and having another portion thereof located in the at least one opening.
23. The heat sink according to claim 22, further comprising:
- a passivation layer comprising a second layer including diamond located between the semiconductor device and the layer.
24. The heat sink according to claim 23, wherein at least one of the layer and the second layer has at least one trace connecting the semiconductor device and the at least one bond pad.
25. The heat sink according to claim 24, further comprising:
- a passivation layer located between the layer and the second layer.
26. The heat sink according to claim 25, wherein the passivation layer has at least one trace connecting the semiconductor device and the at least one bond pad.
27. The heat sink according to claim 22, further comprising:
- a film including diamond formed between the passivation layer and the semiconductor device, the film contacting the semiconductor device.
28. A semiconductor die comprising:
- a substrate having a surface, at least one circuit located on the substrate, a layer including diamond provided over at least a portion of the surface of the substrate having at least one aperture therein, and having at least one contact pad having a periphery, the at least one contact pad having at least a portion thereof extending at least partially over the layer adjacent the at least one aperture therein and having at least a portion thereof extending through the at least one aperture in the layer, the at least one contact pad connected to the at least one circuit on the substrate.
29. The semiconductor die according to claim 28, further comprising:
- a second layer including diamond located between the substrate and the layer.
30. The semiconductor die according to claim 29, wherein at least one of the layer and the second layer has at least a portion of one trace located on a portion thereof to connect the substrate and the at least one contact pad.
31. The semiconductor die according to claim 28, further comprising:
- a passivation layer located between the layer and the second layer.
32. The semiconductor die according to claim 31, wherein the passivation layer has at least a portion of at least one trace located thereon to connect the substrate and the at least one contact pad.
33. The semiconductor die according to claim 28, further comprising:
- a film including diamond formed between a passivation layer and the substrate, the film directly contacting the surface of the substrate.
Type: Application
Filed: Jun 7, 2006
Publication Date: Oct 26, 2006
Inventors: Salman Akram (Boise, ID), Alan Wood (Boise, ID)
Application Number: 11/449,496
International Classification: H01L 23/34 (20060101);