Semiconductor device and method for fabricating the same
A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.
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This application claims priority under 35 U.S.C. § 119 on Patent Application No. 2004-138010 filed in Japan on May 7, 2004, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION(a) Fields of the Invention
The present invention relates to semiconductor devices which have MIS transistors capable of accomplishing a further miniaturization and operable at high speed and with low power consumption, and to methods for fabricating such a device.
(b) Description of Related Art
Accompanied with high integration of semiconductor integrated circuits, miniaturization of MIS transistors in the circuits is demanded. To accomplish this miniaturization, MIS transistors are required which have a heavily-doped source and drain structure with shallow junctions of source and drain regions (see, for example, Japanese Unexamined Patent Publication No. H11-261069).
Hereinafter, an example of conventional methods for fabricating a semiconductor device with a MIS transistor will be described with reference to the accompanying drawings.
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In order to miniaturize the MIS transistor without manifesting a short channel effect, the conventional fabrication methods as described above tend to lower the implantation energy of the impurity ion for forming the n-type diffused extension layers 105 and increase the temperature of the thermal treatment for activation.
SUMMARY OF THE INVENTIONThe above-described conventional method for fabricating a semiconductor device with a MIS transistor, however, has the following problems.
First, in the step shown in
Second, if annealing at a temperature higher than required is performed in order to suppress TED of the impurity atoms implanted into the n-type diffused source and drain layer 108, impurity redistribution occurs in the n-type diffused extension layer 105 having once been formed shallowly. This simultaneously causes a problem that the junction thereof is made deep. The depth and shape of the junction of the n-type diffused extension layer 105 directly affect short channel characteristics and driving current of the semiconductor device. Therefore, in the thermal treatment process for activating the impurity of the n-type diffused source and drain layer 108, prevention of redistribution of the impurity profile in the diffused extension layer 105 is as important as control of the impurity profile of the source and drain region 108.
Third, as miniaturization of transistors proceeds to make the gate lengths thereof smaller, the implantation energy of arsenic ions for forming the n-type diffused source and drain layer 108 is reduced. When this reduction is promoted, channeling arising in the <110>-oriented zone axis allows arsenic ions to enter even into the diffused channel layer 102 located below the gate electrode 104. Thus, the arsenic ions having entered also come to affect the short channel characteristics of the device.
As is apparent from the above, it is extremely difficult for the conventional method for fabricating a semiconductor device to form the diffused source and drain layers having a shallow junction and high impurity concentration essential to miniaturization of MIS transistors so that the layers have a desired impurity concentration and concurrently entry of an impurity ion and impurity distribution of the diffused extension layer by TED are minimized.
In view of the conventional problems, an object of the present invention is to miniaturize a semiconductor device by minimizing manifestation of short channel effect (and reverse short channel effect) accompanied with the miniaturization and concurrently allowing the shapes of diffused source and drain layers to be made shallow in the depth direction and small in the lateral direction.
To attain the above object, in the present invention, a method for fabricating a semiconductor device is designed so that an impurity having a conductivity type opposite to the conductivity type of source and drain regions is implanted into the source and drain regions and then thermal treatment is performed to make an impurity diffusion with impurity pairs (ion pairs) of n-type and p-type impurities produced, thereby forming the source and drain region of low resistance with a thermal budget reduced. By this method, the formed semiconductor device includes in the source and drain region an impurity diffused layer of a conductivity type opposite to the conductivity type of the source and drain regions. Note that “thermal budget” refers to the amount of thermal treatment represented by the product of the heating temperature and the heating time.
To be more specific, a semiconductor device according to the present invention is characterized by comprising: a semiconductor layer of a first conductivity type; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film; and diffused source and drain layers of a second conductivity type formed in regions of the semiconductor layer located below sides of the gate electrode, respectively. This device is also characterized in that insides of the diffused source and drain layers are formed with impurity implanted regions of the first conductivity type having a lower impurity concentration than the diffused source and drain layers.
In the semiconductor device of the present invention, insides of the diffused source and drain layers of the second conductivity type are formed with the impurity implanted regions of the first conductivity type having a lower impurity concentration than the diffused source and drain layer. By this, in thermally diffusing the impurity ion of the second conductivity type implanted for formation of the diffused source and drain layer, the impurity ion of the second conductivity type combines with the impurity ion of the first conductivity type implanted into the impurity implanted region to produce an ion pair, thereby suppressing transient enhanced diffusion. Thus, the junction depth of the diffused source and drain layer becomes shallow to miniaturize the semiconductor device with manifestation of short channel effect minimized.
Preferably, the semiconductor device of the present invention further comprises: diffused extension layers of the second conductivity type formed in regions of the semiconductor layer located below the sides of the gate electrode and between the diffused source and drain layers, respectively; and diffused pocket layers of the first conductivity type formed in regions of the semiconductor substrate located below the diffused extension layers, respectively, and the impurity concentration of the impurity implanted region is higher than that of the diffused pocket layer.
Preferably, the semiconductor device of the present invention further comprises a diffused channel layer of the first conductivity type formed in a region of the semiconductor layer located below the gate electrode, and the impurity concentration of the impurity implanted region is higher than that of the diffused channel layer.
Preferably, in the semiconductor device of the present invention, the impurity of the second conductivity type forming the diffused source and drain layers is arsenic, and the impurity of the first conductivity type forming the impurity implanted region is indium.
Preferably, in the semiconductor device of the present invention, the diffused source and drain layers contain an element belonging to the group IV at a higher concentration than that of the semiconductor layer located below the gate electrode.
A method for fabricating a semiconductor device according to the present invention is characterized by comprising: the step (a) of sequentially forming a gate insulating film and a gate electrode on a semiconductor layer of a first conductivity type; the step (b) of forming sidewalls on side surfaces of the gate electrode; the step (c) of subjecting the semiconductor layer to ion implantation of a first impurity of the first conductivity type using the gate electrode and the sidewalls as a mask, thereby forming impurity implanted layers of the first conductivity type in regions of the semiconductor layer located below sides of the sidewalls; the step (d) of subjecting the semiconductor layer to ion implantation of a second impurity of a second conductivity type using the gate electrode and the sidewalls as a mask, thereby forming implanted source and drain layers of the second conductivity type in regions of the semiconductor layer located below the sides of the sidewalls; and the step (e) of subjecting, after the steps (c) and (d), the semiconductor layer to a first thermal treatment, thereby diffusing the second impurity to form diffused source and drain layers of the second conductivity type in regions of the semiconductor layer located below the sides of the sidewalls. This device is also characterized in that in the step (e), insides of the diffused source and drain layers are formed with impurity implanted regions of the first conductivity type, respectively, which are made by diffusing the first impurity with a lower impurity concentration than that of the diffused source and drain layers.
The method for fabricating a semiconductor device according to the present invention includes not only the step (d) of implanting the second impurity of the second conductivity type to form the implanted source and drain layers of the second conductivity type, but also the step (c) of implanting the first impurity of the first conductivity type to form the impurity implanted layers. Therefore, in the subsequent first thermal treatment step (e), the first and second impurities having different conductivity types produce an impurity pair (ion pair). By producing an ionized pair (positive and negative ions) having polarities opposite to each other, the produced impurity pair is electrically neutral and difficult to diffuse. This suppresses transient enhanced diffusion of the second impurity. As a consequence of this, the diffused source and drain layers can be formed which have shallower junctions than the case where only the second impurity is implanted.
Preferably, the method for fabricating a semiconductor device according to the present invention further comprises, after the step (a) and before the step (b), the step (f) of subjecting the semiconductor layer to ion implantation of a third impurity of the second conductivity type using the gate electrode as a mask, thereby forming implanted extension layers of the second conductivity type in regions of the semiconductor layer located below sides of the gate electrode, the step (g) of subjecting regions of the semiconductor layer located below the sides of the gate electrode to ion implantation of a fourth impurity of the first conductivity type using the gate electrode as a mask, thereby forming implanted pocket layers of the first conductivity type in the semiconductor layer, and the step (h) of subjecting, after the steps (f) and (g), the semiconductor layer to a second thermal treatment, thereby diffusing the third impurity to form diffused extension layers of the second conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and simultaneously diffusing the fourth impurity to form diffused pocket layers of the first conductivity type in regions of the semiconductor layer located below the diffused extension layers, and the impurity concentration of the impurity implanted region is higher than that of the diffused pocket layer. With this method, the diffused extension layers having the same conductivity type as the diffused source and drain layers are formed in regions of the semiconductor layer located below the sides of the gate electrode, and the diffused pocket layers having the opposite conductivity type to the diffused source and drain layers are formed below the diffused extension layers. This reduces the resistance between the source and the drain, and limits expansion of a depletion layer in the channel region formed below the gate electrode.
Preferably, the method for fabricating a semiconductor device according to the present invention further comprises, before the step (a), the step (i) of subjecting the semiconductor layer to ion implantation of a fifth impurity of the first conductivity type to form an implanted channel layer of the first conductivity type in the semiconductor layer, and then subjecting the semiconductor layer to a third thermal treatment, thereby diffusing the fifth impurity to form a diffused channel layer of the first conductivity type in the semiconductor layer, and the impurity concentration of the impurity implanted region is higher than that of the diffused channel layer.
Preferably, the method for fabricating a semiconductor device according to the present invention further comprises, after the step (b) and before the steps (c) and (d), the step (j) of subjecting the semiconductor layer to ion implantation of a sixth impurity using the gate electrode and the sidewalls as a mask, thereby forming amorphous layers in regions of the semiconductor layer located below sides of the sidewalls. With this method, the second impurity for the source and drain formation carried out in the step (d) can be prevented from channeling in the depth direction of the semiconductor layer. Furthermore, in the case where the semiconductor layer is made of, for example, silicon, the second impurity can also be prevented from entering into the region below the gate electrode resulting from channeling in the <110>-oriented zone axis.
Preferably, in this case, in the step (j), the sixth impurity is implanted by angled implantation having a predetermined angle with respect to the normal to a main surface of the semiconductor layer. With this method, channeling in the <110>-oriented zone axis can be suppressed more certainly.
Preferably, in the method for fabricating a semiconductor device according to the present invention, the sixth impurity is a group IV element. With this method, in the case where the semiconductor layer is made of silicon, when the semiconductor layer is amorphized with the group IV element, the group IV element never exerts an electrical influence on the semiconductor layer after amorphization of the semiconductor layer. This is because the group IV element is electrically neutral.
Preferably, in the method for fabricating a semiconductor device according to the present invention, ion implantation of the second impurity is conducted at an implantation projected range equal to or larger than the implantation projected range of the first impurity.
Preferably, in the method for fabricating a semiconductor device according to the present invention, the first impurity is indium.
Preferably, the method for fabricating a semiconductor device according to the present invention further comprises, after the step (d) and before the step (e), the step (k) of performing an extremely low-temperature thermal treatment of a level at which the implanted impurity does not diffuse, thereby restoring crystal damages due to the ion implantation.
Preferably, in this case, the heating temperature of the extremely low-temperature thermal treatment is from 400 to 700° C. inclusive. Such a low heating temperature range from 400 to 700° C. inclusive is a temperature range in which solid phase epitaxial regrowth (SPER) of the amorphous layer occurs. Therefore, in this range, substantially only restoration of crystal damages can be carried out with the impurity ions hardly diffused.
Preferably, the method for fabricating a semiconductor device according to the present invention further comprises, the step (l) of removing, after the step (e), the sidewalls and then subjecting the semiconductor layer to ion implantation of a third impurity of the second conductivity type using the gate electrode as a mask, thereby forming implanted extension layers of the second conductivity type in regions of the semiconductor layer located below sides of the gate electrode; the step (m) of subjecting the semiconductor layer to ion implantation of a fourth impurity of the first conductivity type using the gate electrode as a mask, thereby forming implanted pocket layers of the first conductivity type in regions of the semiconductor layer located below the sides of the gate electrode; and the step (n) of subjecting, after the steps (l) and (m), the semiconductor layer to a second thermal treatment, thereby diffusing the third impurity to form diffused extension layers of the second conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and simultaneously diffusing the fourth impurity to form diffused pocket layers of the first conductivity type in regions of the semiconductor layer located below the diffused extension layers, and the impurity concentration of the impurity implanted region is higher than that of the diffused pocket layer.
As described above, in this method, the sidewalls are selectively removed after formation of the diffused source and drain layers, and then the diffused extension layers are formed using the gate electrode as a mask. Therefore, unlike the case where the diffused extension layers are formed previously, this method can avoid the situation in which by the thermal treatment in the step (e) of activating the impurity for source and drain formation, redistribution occurs in the impurity contained in the diffused extension layer, thereby making the junction depth thereof deep.
BRIEF DESCRIPTION OF THE DRAWINGS
A first embodiment of the present invention will be described with reference to the accompanying drawings.
Referring to
A p-type diffused channel layer 12 is formed in a region of the semiconductor substrate 11 located below the gate insulating film 14. N-type diffused extension layers 16 are selectively formed in regions of the semiconductor substrate 11 located below the sidewalls 18, respectively, and p-type diffused pocket layers 17 are selectively formed below the n-type diffused extension layers 16, respectively.
In regions of the semiconductor substrate 11 located below sides of the sidewalls 18, n-type diffused source and drain layers 20 are formed to have deeper junctions than the p-type diffused channel layer 12 and to connect inner edges thereof to the n-type diffused extension layers 16 and the p-type diffused pocket layers 17, respectively.
The first embodiment is characterized in that insides of the n-type diffused source and drain layers 20 are formed with p-type impurity implanted regions 19, respectively, made by implanting a p-type impurity with a lower impurity concentration than the concentration of the impurity contained in the n-type diffused source and drain layers 20. In this embodiment, for example, arsenic (As) is introduced into the n-type diffused source and drain layers 20, while, for example, indium (In) is implanted into the p-type impurity implanted region 19. The impurity concentration of the p-type impurity implanted region 19 is set higher than those of the p-type diffused channel layer 12 and the p-type diffused pocket layer 17.
As described above, in the semiconductor device according to the first embodiment, the insides of the n-type diffused source and drain layers 20 are formed with the p-type impurity implanted regions 19 having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layers 20. Thus, when arsenic ions implanted to form the n-type diffused source and drain layers 20 are thermally diffused, the arsenic ions serving as a donor and indium ions serving as an acceptor produce ion pairs electrically neutral. By this, it becomes difficult for the indium ions to diffuse, so that the n-type diffused source and drain layers 20 having shallow junctions can be formed. Since the junctions of the n-type diffused source and drain layers 20 can be made shallow, miniaturization of the MIS transistor can be attained.
A fabrication method of the MIS transistor constructed above will be described below with reference to the accompanying drawings.
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As described above, according to the first embodiment, in the step shown in
Ionized donor and acceptor atoms have the property of being electrically attracted to each other by thermal treatment to produce an ion pair. By this property, ionized arsenic in the n-type implanted source and drain layers 20A and ionized indium in the p-type ion implanted layer 19A produce an ion pair, which suppresses transient enhanced diffusion of arsenic. Therefore, a diffusion layer can be formed which has a shallower junction than the case where only an n-type impurity is implanted.
Thus, the ion pair of arsenic and indium suppresses arsenic diffusion, which eliminates the necessity to set the thermal treatment for activation for forming the n-type diffused source and drain layers 20 at a temperature higher than required. Moreover, in the thermal treatment step, the time for which the heated state is kept can be reduced, so that the activation process can be carried out with a low thermal budget. Furthermore, the step of activating the impurity for source and drain formation can be carried out with a low thermal budget, which also avoids the conventional drawback that by the thermal treatment in this step, redistribution of the impurity occurs in the diffused extension layer having once been formed shallowly, thereby making the junction thereof deep.
Moreover, an element with a relatively large mass number, such as indium, is used as a p-type impurity for combining with an impurity for source and drain formation to produce an ion pair. Therefore, even at a low dose, the source and drain formation region of the semiconductor substrate 11 can be amorphized. Thus, by implanting indium for ion pair production prior to the ion implantation of arsenic for source and drain region formation, the implanted indium ions also serve as an impurity for implantation for pre-amorphization. This pre-amorphous effect suppresses channeling of arsenic to be implanted subsequently, so that the implantation profile of arsenic can be made shallow. During restoration of the crystal of the amorphous layer, the layer is in the meta-stable state in which the solubility limit of the contained impurity is higher than that of the impurity contained in the crystal layer. Consequently, by this pre-amorphous effect, the impurity profile of arsenic created by the thermal diffusion for activation can obtain a shallow junction.
It is known that indium strongly segregates to a dislocation loop defect layer. Therefore, by forming the p-type ion implanted layers 19A with indium ions implanted therein within the n-type implanted source and drain layers 20A with arsenic ions implanted, the indium is trapped into the dislocation loop defect layer. This suppresses transient enhanced diffusion of arsenic caused by releasing interstitial silicon from the dislocation loop defect layer.
As is apparent from the above, with the method for fabricating a semiconductor device according to the first embodiment, the n-type diffused source and drain layers 20 with a shallow junction can be formed certainly while redistribution of the impurity in the n-type diffused extension layer 16 is suppressed.
Moreover, indium ions with a relatively large mass number are used for formation of the p-type diffused channel layer 12. Therefore, a region of the p-type diffused channel layer 12 located around the substrate surface has a decreased impurity concentration, while a region thereof located slightly deeper than the substrate surface has an increased impurity concentration. That is to say, a retrograde impurity profile can be provided in this layer. This prevents a decrease in carrier mobility mainly resulting from impurity dispersion and therefore minimizes manifestation of short channel effect. As a result, the transistor in the device can be miniaturized reliably.
Second EmbodimentA second embodiment of the present invention will be described below with reference to the accompanying drawings.
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Subsequently to the third extremely low-temperature thermal treatment, the semiconductor substrate 11 is heated to about 850 to 1000° C. at a heating rate of about 200 to 250° C./sec. After the heating, a fourth rapid thermal annealing is performed either with the peak temperature thereof kept for about 10 seconds at the maximum or with the peak temperature not kept. The fourth rapid thermal annealing activates arsenic ions contained in the n-type implanted source and drain layers 20A to form, in regions of the semiconductor substrate 11 located below the sides of the sidewalls 18, n-type diffused source and drain layers 20. By the formation of the n-type diffused source and drain layers 20, the n-type diffused extension layers 16 and the p-type diffused pocket layers 17 are also formed between the p-type diffused channel layer 12 below the gate electrode 15 and the n-type diffused source and drain layers 20. Each of the n-type diffused source and drain layers 20 has a junction connected to the n-type diffused extension layer 16 and made deeper than the n-type diffused extension layer 16. In this state, inside each of the n-type diffused source and drain layers 20, the p-type impurity implanted region 19 shown by the broken curve is embedded which is formed from the p-type ion implanted layer 19A. The p-type impurity concentration of the p-type impurity implanted region 19 is lower than the n-type impurity concentration of the n-type diffused source and drain layers 20, so that the p-type impurity implanted region 19 will not be formed in the structure of a p-type impurity diffused layer. The fourth rapid thermal annealing, such as spike RTA, laser annealing, and flash lamp annealing, can be performed to enhance activation of impurities for which the activation only by the third extremely low-temperature thermal treatment is inadequate.
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Thus, the ion pair suppresses arsenic diffusion, which eliminates the necessity to set the thermal treatment performed subsequently to the extremely low-temperature thermal treatment and performed for activation for forming the diffused source and drain layers at a temperature higher than required. Moreover, in the thermal treatment, the time for which the heated state is kept can be reduced, so that the activation process can be carried out with a low thermal budget. Furthermore, the step of activating the impurity for source and drain formation can be carried out with a low thermal budget, which also avoids the conventional drawback that by the thermal treatment in this step, redistribution of the impurity occurs in the diffused extension layer having once been formed shallowly, thereby making the junction thereof deep.
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Moreover, as described above, it is known that indium strongly segregates to a dislocation loop defect layer. Therefore, by forming the p-type ion implanted layers 19A with indium ions implanted therein within the n-type implanted source and drain layers 20A with arsenic ions implanted, the indium is trapped into the dislocation loop defect layer. This suppresses transient enhanced diffusion of arsenic caused by releasing interstitial silicon from the dislocation loop defect layer.
As is apparent from the above, the n-type diffused source and drain layers 20 with shallow junctions can be formed certainly while redistribution of the impurity contained in the n-type diffused extension layer 16 is prevented.
Moreover, indium ions with a relatively large mass number are used for formation of the p-type diffused channel layer 12. Therefore, a region of the p-type diffused channel layer 12 located around the substrate surface has a decreased impurity concentration, while a region thereof located away from the substrate surface has an increased impurity concentration. That is to say, a retrograde impurity profile can be provided in this layer. This prevents a decrease in carrier mobility mainly resulting from impurity dispersion and therefore minimizes manifestation of short channel effect. As a result, the transistor in the device can be miniaturized reliably.
Third EmbodimentA semiconductor device according to a third embodiment of the present invention will be described below with reference to the accompanying drawings.
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As described above, according to the third embodiment, in the step shown in
As mentioned above, ionized arsenic in the n-type implanted source and drain layers 20A and ionized indium in the p-type ion implanted layer 19A produce an ion pair. The produced ion pair suppresses transient enhanced diffusion of arsenic, whereby the n-type diffused source and drain layers 20 can be formed which has a shallower junction depth than the case where only an n-type impurity is implanted.
Thus, the ion pair of arsenic and indium suppresses arsenic diffusion, which eliminates the necessity to set the thermal treatment for activation for forming the n-type diffused source and drain layers 20 at a temperature higher than required. Moreover, in the thermal treatment step, the necessity to set the time for which the heated state is kept is eliminated, so that the activation process can be carried out with a low thermal budget.
Furthermore, the n-type diffused extension layer 16 is formed after formation of the n-type diffused source and drain layers 20, which also avoids the situation in which by the thermal treatment in the step of activating the n-type impurity for source and drain formation, redistribution occurs in the impurity contained in the n-type diffused extension layer 16 having been formed once, thereby making the junction depth thereof deep.
Moreover, if the gate electrode 15 is made of polysilicon or polymetal, an activation process for an impurity introduced in the polysilicon forming the gate electrode 15 can also be carried out by the formation step of the diffused source and drain layers 20 to more fully activate the polysilicon or the like forming the gate electrode 15.
As is apparent from the above, with the method for fabricating a semiconductor device according to the third embodiment, the n-type diffused source and drain layers 20 with shallow junctions can be formed certainly while redistribution of the impurity in the n-type diffused extension layer 16 is suppressed.
Moreover, indium ions with a relatively large mass number are used for formation of the p-type diffused channel layer 12. Therefore, a region of the p-type diffused channel layer 12 located around the substrate surface has a decreased impurity concentration, while a region thereof located slightly deeper than the substrate surface has an increased impurity concentration. That is to say, a retrograde impurity profile can be provided in this layer. This prevents a decrease in carrier mobility mainly resulting from impurity dispersion and therefore minimizes manifestation of short channel effect. As a result, the transistor in the device can be miniaturized reliably.
Fourth EmbodimentA semiconductor device according to a fourth embodiment of the present invention will be described below with reference to the accompanying drawings.
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Subsequently to the first extremely low-temperature thermal treatment under an extremely low temperature, the semiconductor substrate 11 is heated to about 850 to 1000° C. at a heating rate of about 200 to 250° C./sec. After the heating, a second rapid thermal annealing (spike RTA, laser annealing, flash lamp annealing, or the like) is performed either with the peak temperature thereof kept for about 10 seconds at the maximum or with the peak temperature not kept. The second rapid thermal annealing activates arsenic ions contained in the n-type implanted source and drain layers 20A to form, in regions of the semiconductor substrate 11 located below the sides of the first sidewalls 18A, n-type diffused source and drain layers 20. In this state, inside each of the n-type diffused source and drain layers 20, the p-type impurity implanted region 19 shown by the broken curve is embedded which is formed from the p-type ion implanted layer 19A. The p-type impurity concentration of the p-type impurity implanted region 19 is lower than the n-type impurity concentration of the n-type diffused source and drain layers 20, so that the p-type impurity implanted region 19 will not be formed in the structure of a p-type impurity diffused layer. The second rapid thermal annealing can be performed to enhance activation of impurities for which the activation only by the first extremely low-temperature thermal treatment is inadequate.
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As described above, according to the fourth embodiment, in the step shown in
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Thus, the ion pair suppresses arsenic diffusion, which eliminates the necessity to set the second rapid thermal annealing performed subsequently to the first extremely low-temperature thermal treatment and performed for activation for forming the n-type diffused source and drain layers 20 at a temperature higher than required. Also, the necessity to keep the heated state for a long time even after completion of the heating is eliminated, so that the activation process can be carried out with a low thermal budget. The n-type diffused extension layer 16 is formed after formation of the n-type diffused source and drain layers 20, which also avoids the situation in which by the thermal treatment in the step of activating the n-type impurity for source and drain formation, redistribution of the impurity occurs in the n-type diffused extension layer 16 having once been formed shallowly, thereby making the junction depth thereof deep.
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Furthermore, in the fourth embodiment, by implanting in advance ions of the element belonging to the group IV into the source and drain formation region to form the amorphous layer 21, the source and drain formation region can be amorphized selectively and positively. That is to say, the source and drain formation region is pre-amorphized by angled implantation before formation of the n-type implanted source and drain layers 20A, whereby not only channeling in the depth direction of the implanted arsenic ions can be suppressed, but also laterally struggling intrusion of arsenic ions into the region below the gate electrode 15 resulting from channeling in the <110>-oriented zone axis can be suppressed.
Moreover, it is known that indium strongly segregates to a dislocation loop defect layer. Therefore, by forming the p-type ion implanted layers 19A with indium ions implanted therein within the n-type implanted source and drain layers 20A with arsenic ions implanted, the indium is trapped into the dislocation loop defect layer. This suppresses transient enhanced diffusion of arsenic contributing to release of interstitial silicon from the dislocation loop defect layer.
As is apparent from the above, the n-type diffused source and drain layers 20 with shallow junctions can be formed certainly while redistribution of the impurity in the n-type diffused extension layer 16 is suppressed.
Moreover, indium ions with a relatively large mass number are used for formation of the p-type diffused channel layer 12. Therefore, a region of the p-type diffused channel layer 12 located around the substrate surface has a decreased impurity concentration, while a region thereof located slightly deeper than the substrate surface has an increased impurity concentration. That is to say, a retrograde impurity profile can be provided in this layer. This prevents a decrease in carrier mobility mainly resulting from impurity dispersion and therefore minimizes manifestation of short channel effect. As a result, the transistor in the device can be miniaturized reliably.
Also in the second embodiment, angled implantation of germanium ions or silicon ions may be performed when the source and drain formation region is formed with the amorphous layer 21.
In the first to fourth embodiments, an indium ion is used as an impurity ion of the p-type diffused channel layer 12. Instead of this, a boron ion or an ion of an element heavier than boron and serving as a p-type element may be used thereas, or these ions may be used together. Furthermore, an element belonging to the group 3B and having a larger mass number than indium may be used. In addition, silicon oxide is used for the gate insulating film 12, but an oxynitride film or an insulating film of high dielectric such as hafnium oxide or hafnium silicate may be used therefor.
In the first to fourth embodiments, description has been made using the n-channel type MIS transistor as the semiconductor device. Instead of this, the device used may be a p-channel MIS transistor. In the case of the p-channel MIS transistor, as a p-type impurity ion forming p-type diffused source and drain layers, use can be made of a boron ion, an indium ion, or the like, and as an n-type impurity combining with the p-type impurity ion to produce an ion pair, use can be made of a group 5B element such as an arsenic ion, an antimony (Sb) ion, or a bismuth (Bi) ion.
In the first to fourth embodiments, silicon oxide is used for the gate insulating film 14, and polysilicon or polymetal is used for the gate electrode 15. Alternatively, a so-called gate replacement may be carried out in which the gate electrode 15 and the gate insulating film 14 are removed by etching after formations of the n-type diffused source and drain layers 20 and the n-type diffused extension layer 16, and then the gate electrode structure is substituted by employing the gate insulating film 14 made of a high dielectric film of silicon oxynitride, hafnium oxide, or the like and the gate electrode 15 made of a metal film of tungsten, titanium, or the like.
As described above, in the semiconductor device and the method for fabricating the device according to the present invention, implantation of an impurity with an opposite conductivity type to the impurity in the diffused source and drain layers into the diffused source and drain layers exerts the following effects: transient enhanced diffusion of the impurity forming the diffused source and drain layers can be suppressed by a low thermal budget, diffused source and drain layers with an abrupt, shallow junction can be formed, and impurity distribution in the diffused extension layer can be suppressed. Consequently, the semiconductor device according to the present invention is useful for a miniaturizable semiconductor device and the like having a diffused layer with a shallow junction and a low resistance.
Claims
1-5. (canceled)
6. A method for fabricating a semiconductor device, comprising:
- the step (a) of sequentially forming a gate insulating film and a gate electrode on a semiconductor layer of a first conductivity type;
- the step (b) of forming sidewalls on side surfaces of the gate electrode;
- the step (c) of subjecting the semiconductor layer to ion implantation of a first impurity of the first conductivity type using the gate electrode and the sidewalls as a mask, thereby forming impurity implanted layers of the first conductivity type in regions of the semiconductor layer located below sides of the sidewalls;
- the step (d) of subjecting the semiconductor layer to ion implantation of a second impurity of a second conductivity type using the gate electrode and the sidewalls as a mask, thereby forming implanted source and drain layers of the second conductivity type in regions of the semiconductor layer located below the sides of the sidewalls; and
- the step (e) of subjecting, after the steps (c) and (d), the semiconductor layer to a first thermal treatment, thereby diffusing the second impurity to form diffused source and drain layers of the second conductivity type in regions of the semiconductor layer located below the sides of the sidewalls,
- wherein in the step (e), insides of the diffused source and drain layers are formed with impurity implanted regions of the first conductivity type, respectively, which are made by diffusing the first impurity with a lower impurity concentration than that of the diffused source and drain layers.
7. The method of claim 6, further comprising, after the step (a) and before the step (b),
- the step (f) of subjecting the semiconductor layer to ion implantation of a third impurity of the second conductivity type using the gate electrode as a mask, thereby forming implanted extension layers of the second conductivity type in regions of the semiconductor layer located below sides of the gate electrode,
- the step (g) of subjecting the semiconductor layer to ion implantation of a fourth impurity of the first conductivity type using the gate electrode as a mask, thereby forming implanted pocket layers of the first conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and
- the step (h) of subjecting, after the steps (f) and (g), the semiconductor layer to a second thermal treatment, thereby diffusing the third impurity to form diffused extension layers of the second conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and simultaneously diffusing the fourth impurity to form diffused pocket layers of the first conductivity type in regions of the semiconductor layer located below the diffused extension layers,
- wherein the impurity concentration of the impurity implanted region is higher than that of the diffused pocket layer.
8. The method of claim 6, further comprising, before the step (a), the step (i) of subjecting the semiconductor layer to ion implantation of a fifth impurity of the first conductivity type to form an implanted channel layer of the first conductivity type in the semiconductor layer, and then subjecting the semiconductor layer to a third thermal treatment, thereby diffusing the fifth impurity to form a diffused channel layer of the first conductivity type in the semiconductor layer,
- wherein the impurity concentration of the impurity implanted region is higher than that of the diffused channel layer.
9. The method of claim 6, further comprising, after the step (b) and before the steps (c) and (d), the step (j) of subjecting the semiconductor layer to ion implantation of a sixth impurity using the gate electrode and the sidewalls as a mask, thereby forming amorphous layers in regions of the semiconductor layer located below sides of the sidewalls.
10. The method of claim 9,
- wherein the sixth impurity is a group IV element.
11. The method of claim 6,
- wherein ion implantation of the second impurity is conducted at an implantation projected range equal to or larger than the implantation projected range of the first impurity.
12. The method of claim 6,
- wherein the first impurity is indium.
13. The method of claim 6, further comprising, after the step (d) and before the step (e), the step (k) of performing an extremely low-temperature thermal treatment of a level at which the implanted impurity does not diffuse, thereby restoring crystal damages due to the ion implantation.
14. The method of claim 13,
- wherein the heating temperature of the extremely low-temperature thermal treatment in the step (k) is from 400 to 700° C. inclusive.
15. The method of claim 6, further comprising:
- the step (l) of removing, after the step (e), the sidewalls and then subjecting the semiconductor layer to ion implantation of a third impurity of the second conductivity type using the gate electrode as a mask, thereby forming implanted extension layers of the second conductivity type in regions of the semiconductor layer located below sides of the gate electrode;
- the step (m) of subjecting the semiconductor layer to ion implantation of a fourth impurity of the first conductivity type using the gate electrode as a mask, thereby forming implanted pocket layers of the first conductivity type in regions of the semiconductor layer located below the sides of the gate electrode; and
- the step (n) of subjecting, after the steps (l) and (m), the semiconductor layer to a second thermal treatment, thereby diffusing the third impurity to form diffused extension layers of the second conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and simultaneously diffusing the fourth impurity to form diffused pocket layers of the first conductivity type in regions of the semiconductor layer located below the diffused extension layers,
- wherein the impurity concentration of the impurity implanted region is higher than that of the diffused pocket layer.
16. The method of claim 9,
- wherein in the step (j), the sixth impurity is implanted by angled implantation having a predetermined angle with respect to the normal to a main surface of the semiconductor layer.
Type: Application
Filed: Aug 16, 2006
Publication Date: Dec 7, 2006
Applicant: Matsushita Electric Industrial Co., Inc. (Osaka)
Inventor: Taiji Noda (Osaka)
Application Number: 11/504,672
International Classification: H01L 21/84 (20060101);