Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

Abstract: Apparatuses and techniques for reporting multiple events associated with mitigating usage-based disturbance are described. In an example aspect, a memory device can report to a memory controller various events associated with mitigating usage-based disturbance. This includes notifying the memory controller of events associated with a first event category and alerting the memory controller of events associated with a second event category. For events associated with the first event category, there can be a smaller risk of an alert condition occurring if the memory controller does not take action. For events associated with the second event category, there can be a larger risk of an alert condition occurring if the memory controller does not take action. By reporting these multiple events by category, the memory device empowers the memory controller to take appropriate action and efficiently manage available resources for mitigating usage-based-disturbance.

Abstract: Methods and devices related to selecting image sensors are described. In an example, a method can include receiving, at a processing resource of a computing device, first signaling indicative of image data from a plurality of image sensors that are located under a surface of a display of the computing device; receiving, at the processing resource of the computing device, second signaling indicative of display data indicating a first portion of the display is active when the computing device is running an application, determining, at the processing resource, that a first image sensor of the plurality of sensors is closest to the first portion of the display, and selecting the first image sensor of the plurality of sensors closest to the first portion of the display for generating image data for the application.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

Abstract: Methods, systems, and devices for abnormal sound detection are described. An audio recording of a mechanized environment may be obtained. First sounds extracted from the audio recording may be categorized into a set of categorical sounds. A library of first sound patterns may be generated using the categorical sound and based on second sounds extracted from the audio recording. The first sound patterns may include sequences of the categorical sounds. Audio data including audio signals capture by sensors in the mechanized environment may be received, and second sound patterns detected in the audio signals may be compared with the first sound patterns. Based on comparing the second sound patterns with the first sounds patterns, a sound pattern that is not in the library of the first sound patterns may be identified. An alarm may be generated based on detecting the sound pattern a threshold quantity of times.

Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.

Abstract: A system for providing an enhanced vision transformer block for mobile vision transformers to perform computer vision tasks, such as image classification, segmentation, and objected detection is disclosed. A local representation block of the block applies a depthwise-separable convolutional layer to vectors of an input image to facilitate creation of local representation outputs associated with the image. The local representation output is fed into a global representation block, which unfolds the local representation outputs, applies vision transformers, and folds the result to generate a global representation output associated with the image. The global representation output is fed to a fusion block, which concatenates the local representations with the global representations, applies a point-wise convolution to the concatenation to generate a fusion block output, and fuses input features of the image with the fusion block out to generate an output to facilitate performance of a computer vision tasks.

Abstract: A memory device can include an array of memory cells comprising groups of memory cells, the groups including at least one redundant group for repairing a defective group. The memory device can include a controller coupled to the array. Responsive to receiving a memory access command, the controller can detect whether a defective group is present. If a defect is present, sensing operations are not performed for the defective group. If no defect is present, sensing operations are not performed for the redundant group.

Abstract: Protection of access to a tensor in outsourcing deep learning computations via shuffling. For example, the tensor in the computation of an artificial neural network can be partitioned into portions of different sizes. The computing tasks can be generated for operating on the portions such that the results of the computing tasks can be combined to obtain the result of a computing task operates on the tensor in the computation of the artificial neural network. The computing tasks can be shuffled for distribution out of order to external entities. The partitioning and shuffling can prevent the external entities from accessing and/or reconstructing the tensor.

Abstract: A memory system having a set of media, a plurality of inter-process communication channels, and a controller configured to run a plurality of processes that communicate with each other using inter-process communication messages transmitted via the plurality of inter-process communication channels, in response to requests from a host system to store data in the media or retrieve data from the media. The memory system has a message manager that examines requests from the host system, identifies a plurality of combinable requests, generates a combined request, and provides the combined request to the plurality of processes as a substitute of the plurality of combinable requests.

Abstract: An example method for critical timing driven adjustable voltage frequency scaling can include performing sensing operations on a system on chip (SoC) at a respective plurality of time windows each associated with a particular data value, comparing at least two of the particular data values associated with at least two respective time windows of the plurality of time windows, in response to the at least two of the particular data values being a same data value, determining that a clock margin is above a threshold clock margin, and determining that a clock margin is below a threshold clock margin. In some instance, in response to determining that the clock margin is above the threshold clock margin, a clocking of the SoC can be adjusted, a voltage of at least one operation of the SoC can be adjusted, and/or a clocking frequency of at least one operation of the SoC, among other possibilities.

Abstract: Disclosed are methods, systems, and apparatuses for a memory device with test circuitry-based processing-in-memory (PIM). The memory device utilizes circuitry used to control, sequence, and/or perform test functions, found on a die of the memory device (e.g., an interface die and/or memory die), to perform PIM functions. For example, the memory device may utilize a memory built-in self-test (mBIST) automatic pattern generator (APG) for PIM sequencing. To control PIM operations, the mBIST APG may fetch and decode microcode instructions local to the die. The microcode instructions may be fetched from a read-only memory (ROM) and/or non-volatile memory. Microcode instructions to perform desired PIM operations may be written to the non-volatile memory by a host device coupled to the memory device.

Abstract: A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first polygon shape having at least six sides in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.

Abstract: Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.

Abstract: Apparatuses and techniques for implementing collision avoidance for bank-shared circuitry that supports usage-based disturbance mitigation are described. A memory device includes bank-shared circuitry coupled to multiple banks. The bank-shared circuitry can support usage-based disturbance mitigation. By using the bank-shared circuitry to service multiple banks, the memory device can have a smaller footprint and can be cheaper to manufacture compared to other memory devices with circuitry dedicated for each bank. To avoid conflicts associated with some sequences of commands that may relate to a same bank or different banks and utilize the bank-shared circuitry, the memory controller applies an appropriate timing offset (or delay) between commands. The timing offset allows the memory device time to finish utilizing the bank-shared circuitry for usage-based disturbance mitigation prior to utilizing the bank-shared circuitry in accordance with a subsequent command.

Abstract: A system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: monitoring a host command stream from a host system to the memory device; determining whether a phase value of a host command in the host command stream is valid; responsive to determining that the phase value of the host command is valid, copying the host command; storing the copied host command in a queue in a local memory; and executing the copied host command in the queue in the local memory.

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.

Abstract: A variety of applications can include a phase frequency detector structured to track the falling edges of two input signals to detect a phase difference between the two signals and to generate one or more signals that can be used to adjust one of the signals with respect to the other when the phase difference is greater than 180 degrees. The phase frequency detector can be implemented in a phase lock loop circuit to track the falling edges of a reference clock signal and the falling edge of a feedback signal. In response to detection of the phase difference between the reference clock signal and the feedback signal being greater than 180 degrees using the falling edges of these signals, the phase frequency detector can adjust its output signals to provide for recovery of a lock condition for the reference clock signal. Additional devices, systems, and methods are discussed.