Patents Assigned to Micron Technology, Inc.
  • Publication number: 20220149061
    Abstract: A memory array comprises a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material. The upper and lower conductor materials comprise different compositions relative one another. Laterally-spaced memory blocks individually comprising a vertical stack comprise alternating insulative tiers and conductive tiers, Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material. The channel material of the channel-material strings is directly electrically coupled to the upper and lower conductor materials of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli
  • Publication number: 20220149066
    Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee, Nancy M. Lomeli, Alyssa N. Scarbrough
  • Publication number: 20220148646
    Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: HIDEKAZU NOGUCHI
  • Publication number: 20220149067
    Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee, Nancy M. Lomeli, Alyssa N. Scarbrough
  • Publication number: 20220149828
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 12, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Dean D. Gans
  • Publication number: 20220148640
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 12, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Dean D. Gans
  • Publication number: 20220148661
    Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
  • Patent number: 11329127
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 11328967
    Abstract: A substrate is orientated parallel to a plane and includes pads that are located at a bottom surface of the substrate and external to the electrical device. A first integrated circuit die is orientated parallel to the plane and disposed above the substrate in a vertical direction. The first integrated circuit die is electrically coupled to at least some of the pads of the substrate. A packaging material is disposed above the first integrated circuit die around at least a top surface and side surfaces of the first integrated circuit die. Test pads are orientated parallel to the plane and disposed above the first integrated circuit die in the vertical direction. The test pads are electrically coupled to the first integrated circuit die and encased within the packaging material.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Joseph A. De La Cerda
  • Patent number: 11328997
    Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Matthew Monroe
  • Patent number: 11330101
    Abstract: Methods and apparatuses for managing spoofed calls to a mobile device are described, in which the mobile device receives a call transmitted over a cellular or mobile network. The call may include a set of information associated with the network, such as a geological location of a device that generated the call, a hardware device identifier corresponding to the device, an internet protocol (IP) address associated with the device, or a combination thereof. The mobile device may determine whether the call is spoofed or genuine based on the set of information. Subsequently, the mobile device may assist a user of the mobile device to manage the call, such as blocking the call from reaching the user, informing the user that the call is spoofed, facilitating the user to report the call as spoofed to an authority and/or a service provider of the network.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Elsie de la Garza Villarreal, Madison E. Wale, Bhumika Chhabra, Claudia A. Delaney
  • Patent number: 11329983
    Abstract: The present disclosure includes apparatuses, methods, and systems for validating an electronic control unit of a vehicle. An embodiment includes a memory, and circuitry configured to generate a run-time cryptographic hash based on an identification (ID) number of an electronic control unit of a vehicle and compare the run-time cryptographic hash with a cryptographic hash stored in a portion of the memory.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Alberto Troia
  • Patent number: 11328782
    Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ke Liang, Jun Xu
  • Patent number: 11329051
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, III, Gurtej S. Sandhu, Armin Saeedi Vahdat, Si-Woo Lee, Scott E. Sills
  • Patent number: 11327862
    Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11328210
    Abstract: A vehicle having the first ANN model initially installed therein to generate outputs from inputs generated by one or more sensors of the vehicle. The vehicle selects an input based on an output generated from the input using the first ANN model. The vehicle has a module to incrementally train the first ANN model through unsupervised machine learning from sensor data that includes the input selected by the vehicle. Optionally, the sensor data used for the unsupervised learning may further include inputs selected by other vehicles in a population. Sensor inputs selected by vehicles are transmitted to a centralized computer server, which trains the first ANN model through supervised machine learning from sensor received inputs from the vehicles in the population and generates a second ANN model as replacement of the first ANN model previously incrementally improved via unsupervised machine learning in the population.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Alberto Troia
  • Patent number: 11329026
    Abstract: Apparatuses and methods for internal heat spreading for packaged semiconductor die are disclosed herein. An example apparatus may include a plurality of die in a stack, a bottom die supporting the plurality of die, a barrier and a heat spreader. A portion of the bottom die may extend beyond the plurality of die and a top surface of the bottom die extending beyond the plurality of die may be exposed. The barrier may be disposed alongside the plurality of die and the bottom die, and the heat spreader may be disposed over the exposed top surface of the bottom die and alongside the plurality of die.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: May 10, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: David R. Hembree
  • Patent number: 11327867
    Abstract: An on-die logic analyzer (ODLA) can reduce the time and resources that would otherwise be spent in validating or debugging memory system timings. The ODLA can receive an enable signal with respect to a start command and start a count of clock cycles in response to a first issued command matching the start command defined in a first mode register. The ODLA can stop the count of clock cycles in response to a second issued command matching a stop command defined in a second mode register. The ODLA can write a value indicative of the stopped count to a third mode register or an on-die storage array in response to the stopped count exceeding a previously stored count.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jackson N. Callaghan, Kazuaki Ohara, Ji-Hye G. Shin, Vyjayanthi Prasad, Rosa M. Avila-Hernandez, Gitanjali T. Ghosh, Rachael R. Skreen
  • Patent number: 11328779
    Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Rowley, Dustin J. Carter
  • Patent number: 11329058
    Abstract: A microelectronic device comprises a stack structure having tiers each including a conductive structure and an insulating structure, the stack structure comprises a staircase region comprising staircase structures, a select gate contact region, and a memory array region between the staircase region and the select gate contact region; contact structures on steps of the staircase structures; string drivers coupled to the contact structures and comprising transistors underlying and within horizontal boundaries of the staircase region; a triple well structure underlying the memory array region; a select gate structure between the stack structure and the triple well structure; semiconductive pillar structures within horizontal boundaries of the memory array region and extending through the stack structure and the select gate structure to the triple well structure; and a select gate contact structure within horizontal boundaries of the select gate contact region and extending through the stack structure to the sele
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Aaron S. Yip