Patents Assigned to Micron Technology, Inc.
  • Publication number: 20200176070
    Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example self-trimming circuit includes a control circuit configured to, during a self-trimming operation, decode a test command signal to set a target voltage and set a voltage trim code to an initial value, and to adjust a value of the voltage trim code based on a stop signal. The example self-trimming circuit further includes a reference voltage regulator configured to receive the voltage trim code and to convert a band-gap reference voltage to an output voltage based on the voltage trim code, and a comparator configured to compare the target voltage with the output voltage and to provide the stop signal having a value based on the comparison.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Miguel Jimenez-Olivares, Maksim Kuzmenka
  • Publication number: 20200177244
    Abstract: Examples described herein include systems and methods, including wireless devices and systems with neuron calculators that may perform one or more functionalities of a wireless transceiver. The neuron calculator calculates output signals that may be implemented, for example, using accumulation units that sum the multiplicative processing results of ordered sets from ordered neurons with connection weights for each connection between an ordered neuron and outputs of the neuron calculator. The ordered sets may be a combination of some input signals, with the number of signals determined by an order of the neuron. Accordingly, a kth-order neuron may include an ordered set comprising product values of k input signals, where the input signals are selected from a set of k-combinations with repetition. As an example in a wireless transceiver, the neuron calculator may perform channel estimation as a channel estimation processing component of the receiver portion of a wireless transceiver.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 4, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: FA-LONG LUO, JAIME CUMMINS, TAMARA SCHMITZ, JEREMY CHRITZ
  • Publication number: 20200176465
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Richard J. Hill, Yi Fang Lee, Martin C. Roberts
  • Publication number: 20200176454
    Abstract: Some embodiments include an integrated assembly having active-region-pillars. Each of the active-region-pillars has contact regions. The contact regions include a pair of storage-element-contact-regions, and include a digit-line-contact-region between the storage-element-contact-regions. The active-region-pillars include silicon. Wordlines are along the active-region-pillars and extend along a first direction. Cobalt silicide is directly against the silicon of one or more of the contact regions. Metal-containing material is directly against the cobalt silicide. Digit-lines are electrically coupled with the digit-line-contact-regions and extend along a second direction which crosses the first direction. Storage-elements are electrically coupled with the storage-element-contact-regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 4, 2020
    Applicant: Micron Technology, Inc.
    Inventor: Arzum F. Simsek-Ege
  • Publication number: 20200176471
    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Jie Li, James Mathew, Kunal Shrotri, Luan C. Tran, Gordon A. Haller, Yangda Zhang, Hongpeng Yu, Minsoo Lee
  • Publication number: 20200176034
    Abstract: Apparatuses and methods for operation of a sense amplifier during a power-down operation. The example apparatus may include a sense amplifier including of a transistor coupled between a digit line and a gut node of the sense amplifier. While a wordline coupled to a memory cell is activated, in response to entering a power-down mode, the transistor is disabled to decouple a digit line coupled to the memory cell from the gut node, which reduces leakage current in the sense amplifier.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Applicant: Micron Technology, Inc.
    Inventor: Christopher Kawamura
  • Publication number: 20200176404
    Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: JASPREET S. GANDHI, JAMES M. DERDERIAN, SAMEER S. VADHAVKAR, JIAN LI
  • Publication number: 20200176059
    Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Luigi Pilolli, Agatino Massimo Maccarrone, Hoon Choi, Qiang Tang, Ali Feiz Zarrin Ghalam
  • Publication number: 20200176050
    Abstract: Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Applicant: c/o Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 10673490
    Abstract: Method and Apparatuses for of transmitting data between semiconductor chips are described. An example apparatus includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes first and second inductors. The first semiconductor chip transmits a first combination of a plurality of data bits in logical value by flowing a first current through the first inductor and by flowing substantially no current through the second inductor. The second semiconductor chip includes third and fourth inductors that correspond respectively to the first and second inductors of the first semiconductor chip. The second semiconductor chip receives the first combination of the plurality of data bits in logical value by detecting an electromotive force at the third inductor responsive to the first current and by detecting substantially no electromotive force at the fourth inductor responsive to no current.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ken Iwakura
  • Patent number: 10672835
    Abstract: Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Paolo Fantini
  • Patent number: 10672981
    Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
  • Patent number: 10667621
    Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Huy T. Vo, Adam S. El-Mansouri
  • Patent number: 10672833
    Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Fabio Pellizzer
  • Patent number: 10671298
    Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • Patent number: 10671295
    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes
  • Patent number: 10672441
    Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Liang Chen, David R. Brown
  • Patent number: 10671310
    Abstract: Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yihua Zhang, James Cooke
  • Patent number: 10672657
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Patent number: 10672785
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Meng-Wei Kuo, John D. Hopkins