Patents Assigned to Micron Technology, Inc.
  • Publication number: 20240203791
    Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 20, 2024
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Shuangqiang Luo, Alyssa N. Scarbrough
  • Publication number: 20240206175
    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack comprises horizontally-elongated trenches extending through the first tiers and the second tiers and are individually between immediately-laterally-adjacent memory-block regions. Channel-material strings are formed that extend through the first and second tiers in the memory-block regions. Through the horizontally-elongated trenches, the sacrificial material is replaced with conductive material that comprises control-gate lines in the memory-block regions.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Sidhartha Gupta, Adam W. Saxler, Andrew Li, John D. Hopkins
  • Publication number: 20240206190
    Abstract: A method used in forming an array of capacitors comprises forming first walls along a column direction and second walls along a row direction. The first and second walls individually comprise a first material directly above a second material. The first and second materials are of different compositions relative one another. All of the second material is removed from being directly under the first material in the second walls to form beams that are elongated along the row direction and are suspended between immediately-adjacent of the first walls and to leave the second material directly under the first material in the first walls. Third walls are formed along the row direction. The third walls comprise third material that is of different composition from those of the first and second materials. The third material of individual of the third walls circumferentially-covers the beams. Conductive material is grown over the first and second materials selectively relative to the third material.
    Type: Application
    Filed: November 7, 2023
    Publication date: June 20, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Marcello Mariani, Giorgio Servalli
  • Publication number: 20240203520
    Abstract: An apparatus that includes a plurality of first memory mats each including a plurality of normal column sections each storing user data, and a second memory mat including a plurality of first redundant column sections each substituting a defective one of column sections included in the plurality of first memory mats and a plurality of first BCC column sections each storing an error correction code.
    Type: Application
    Filed: October 12, 2023
    Publication date: June 20, 2024
    Applicant: Micron Technology, Inc.
    Inventors: SUSUMU TAKAHASHI, HIROKI FUJISAWA
  • Publication number: 20240202145
    Abstract: This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Yang Lu, Kang-Yong Kim
  • Publication number: 20240202110
    Abstract: Apparatuses, systems, and methods for a memory refresh watchdog circuit. A memory may include a temperature sensor which sets a value of a refresh multiplier in a mode register. The memory includes a refresh watchdog circuit which determines an expected rate of refresh commands based on a current value of the refresh multiplier. The refresh watchdog circuit measures a rate at which refresh commands are received from a memory controller and compares the measured rate to the expected rate. For example, the refresh watchdog circuit may set a threshold based on the value of the refresh multiplier. The refresh watchdog circuit may change a count value each time a refresh command is received and compare the count value to the threshold. If the count value is less than the threshold, then the refresh watchdog circuit may determine that not enough refresh commands have been received.
    Type: Application
    Filed: November 17, 2023
    Publication date: June 20, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Rainer Bonitz, Aaron P. Boehm
  • Publication number: 20240203496
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions.
    Type: Application
    Filed: February 27, 2024
    Publication date: June 20, 2024
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20240201871
    Abstract: Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
    Type: Application
    Filed: January 31, 2024
    Publication date: June 20, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: JEREMY CHRITZ, DAVID HULTON
  • Patent number: 12015476
    Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Stefan Dietrich, Thomas Hein, Natalija Jovanovic, Ronny Schneider, Michael Dieter Richter, Martin Brox
  • Patent number: 12014082
    Abstract: The present disclosure includes apparatuses and methods related to a memory apparatus and/or method for addressing in memory with a read identification (RID) number. An example apparatus can include a first memory device, a second memory device coupled to the first memory device, and a controller coupled to the first memory device and the second memory device, wherein the controller is configured to receive a read command requesting data from the first memory device, wherein the read command includes a read identification (RID) number that includes an address to identify a location of the data in the first memory device, and transfer the data from the location in the first memory device to the second memory device in response receiving the read command.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Frank F. Ross
  • Patent number: 12013762
    Abstract: A memory system having a set of non-volatile media, a volatile memory, a buffer memory, and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. The buffer memory is capable of holding data for at least a predetermined period of time after the volatile memory loses data during an event of power outage in the memory system. A power manager monitors a power supply of the memory system to detect an onset of power outage and, in response to the onset of power outage, causes the controller to copy meta data in the volatile memory to the buffer memory.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 12014792
    Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Mark D. Ingram, Todd Jackson Plum, Scott E. Schaefer, Aaron P. Boehm, Scott D. Van De Graaff
  • Patent number: 12013788
    Abstract: System and techniques for evicting a cache line with pending control request are described herein. A memory request—that includes an address corresponding to a set of cache lines—can be received. A determination can be made that a cache line of the set of cache lines will be evicted to process the memory request. Another determination can be made that a control request has been made to a host from the memory device and that the control request pending when it is determined that the cache line will be evicted. Here, a counter corresponding to the set of cache lines can be incremented (e.g., by one) to track the pending control request in face of eviction. Then, the cache line can be evicted.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tony M. Brewer, Dean E. Walker
  • Patent number: 12014050
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Ching-Huang Lu, Murong Lang
  • Patent number: 12013756
    Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala, Nevil Gajera
  • Patent number: 12014077
    Abstract: Methods, systems, and devices for rating-based mapping of data to memory are described. A memory system may determine a first rating for a set of data selected for writing to a memory system. The memory system may select a target page of a block in the memory system for writing the set of data based at least in part on a second rating for the target page. The memory system may write the set of data to the target page based at least in part on the first rating for the set of data corresponding to the second rating for the target page.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Carla L Christensen, Gangotree Chakma, Yingqi Zheng, Yunfei Xu, Bhumika Chhabra
  • Patent number: 12013792
    Abstract: A read command is received by a processing device coupled to a memory device. The read command specified a logical address. The processing device translates the logical address into a physical address of a physical block of the memory device, wherein the physical address specifies a wordline and a memory device die. Responsive to determining that the physical block is partially programmed, the processing device identifies a threshold voltage offset associated with the wordline. The processing device computes a modified threshold voltage by applying the threshold voltage offset to a read level associated with the memory device die. The processing device reads the data from the physical block using the modified threshold voltage.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Li-Te Chang, Murong Lang, Zhenming Zhou
  • Patent number: 12013789
    Abstract: Methods, systems, and devices for flexible information compression at a memory system are described. For example, a memory system may compress information in a change log to reduce the frequency of transfers of one or more mappings between volatile memory and non-volatile memory. The memory system may compress information associated with a sequence of sequentially-indexed addresses by storing the information associated with those addresses at a pair of entries in the change log. The memory system may additionally switch between a first operating mode associated with identifying sequentially-indexed addresses and generating compressed entries, and a second operating mode associated with generating entries of the change log for each address received in commands.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yanming Liu, Zhenzhen Yang, Yi Heng Sun, Junjun Wang
  • Patent number: 12014049
    Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: June 18, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Yu-Chung Lien, Zhenming Zhou, Murong Lang, Ching-Huang Lu
  • Patent number: 12014187
    Abstract: Implementations described herein relate to boot processes for memory devices. In some implementations, a controller of a storage system receives a command for enabling a fast bootup process for the storage system. The fast bootup process may exclude a measurement of information retrieved from a memory device of the storage system during the fast bootup process. The controller may enable the fast bootup process based on the command. The controller may disable a normal bootup process for the storage system based on the fast bootup process being enabled. The normal bootup process may include a measurement of information retrieved from the memory device during the normal bootup process.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sourin Sarkar, Vamshikrishna Komuravelli, Kanika Mittal