Abstract: An apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. The first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.

Abstract: Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.

Abstract: A liner is formed laterally-outside of individual channel-material strings in one of first tiers and in one of second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Abstract: According to one or more embodiments of the disclosure, an apparatus comprising a voltage dividing circuit is provided. The voltage dividing circuit includes a first resistor unit, a second resistor unit parallel to the first resistor unit in a first direction, and a bridge. The bridge is between the first resistor unit and the second resistor unit and links a first middle portion of the first resistor unit to a second middle portion of the second resistor unit. The first and second middle portions are middle portions of the first and the second resistor units in a second direction perpendicular to the first direction.

Abstract: A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.

Abstract: Operations include identifying a system failure affecting visibility, to at least one dual port node of a plurality of dual port nodes, of at least one of a first volume of a plurality of volumes of a first memory device or a second volume of the plurality of volumes, and modifying a visibility configuration to address the system failure. Each volume of the plurality of volumes includes a persistent memory region (PMR). Modifying the visibility configuration includes modifying the visibility of at least one of the first volume or the second volume to the at least one dual port node of the plurality of dual port nodes through its first port or its second port via the at least one switch domain of the plurality of switch domains.

Abstract: Apparatuses and methods of overlay measurement are disclosed. An example apparatus includes first and second layers. The first layer includes a first alignment pattern that includes a first line extending in a first direction. The first line includes first, second and third segments. The second layer above the first layer includes a second alignment pattern including: a second line extending in the first direction above the first segment and having a first offset from the first segment in a second direction perpendicular to the first direction; a third line extending in the first direction above the second segment and having a second offset from the second segment in the second direction; and a fourth line extending in the first direction above the third segment and having a third offset from the third segment in the second direction. The first, second and third offsets are different from one another.

Abstract: Embodiments are directed to system and methods for determining the user identity of a vehicle occupant and identifying a corresponding user profile to provide customer settings for the user. In some embodiments, the seat or position of the user is determined and settings are applied depending on the which seat is occupied by the user. In some embodiments, vehicle settings are updated as additional vehicle occupants enter the vehicle.

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

Abstract: Apparatuses and methods for implementing artificial synapses utilizing SSM cells. A leaky-integrate-and-fire circuit can provide a feedback signal to an SSM cell responsive to a threshold quantity of pulses being applied to the gate from the signal line. A resulting state of the SSM cell can be dependent on a time difference between a latest of the threshold quantity of pulses and an initial pulse of the feedback signal.

Abstract: Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

Abstract: Exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. The initial error rate and the initial time are stored. A subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. A difference between the initial error rate and the subsequent error rate is determined. A difference between the initial time and the subsequent time is determined. A remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.

Abstract: A vehicle that can be customized and personalized via a mobile user profile. The vehicle can include a body, a powertrain, vehicle electronics, and a computing system. The computing system of the vehicle can be configured to: receive data fields of a driver profile of a user from a mobile device; estimate, using machine learning, configurations of vehicle functions for the vehicle according to the data fields; and control settings of a set of components of the vehicle, via the vehicle electronics, according to the estimated configurations.

Abstract: Methods, systems, and devices for read latency and suspend modes are described. A memory system may operate in a first mode of operation associated with a first set of access operations including executing read operations, executing write operations, and suspending write operations. The memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations. For example, the host system may transmit a command including the indication to switch to the second mode of operation. In another example, the host system may write a value to a register at the memory system including the indication to switch to the second mode of operation. Based on receiving the indication from the host system, the memory system may then operate according to the second mode of operation.

Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. An ordered set cursors is maintained. A source cursor of the ordered set of cursors associated with the victim MU is identified. A target cursor of the ordered set of cursors referencing one or more available MUs is identified as the cursor following the source cursor in the ordered set of cursors. The valid data is associated with the identified target cursor.

Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.

Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.