Abstract: A method comprising receiving a memory access request comprising an address of data to be accessed and determining an access granularity of the data to be accessed based on the address of the data to be accessed. The method further includes, in response to determining that the data to be accessed has a first access granularity, generating first cache line metadata associated with the first access granularity and in response to determining that the data to be accessed has a second access granularity, generating second cache line metadata associated with the second access granularity. The method further includes storing the first cache line metadata and the second cache line metadata in a single cache memory component.

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A tinier of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.

Abstract: A method includes obtaining a first operation execution time corresponding to an operation performed on a page of a first data unit of a memory device, determining whether the first operation execution time satisfies a condition that is based on a second operation execution time, wherein the second operation execution time is indicative of lack of defect in at least a second data unit of the memory device, and responsive to determining that the first operation execution time satisfies the condition that is based on the second operation execution time, initiating a defect scan operation of at least a subset of pages of the first data unit.

Abstract: Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit.

Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

Abstract: Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.

Abstract: Methods, apparatuses, and non-transitory machine-readable media for image location based on a perceived interest are described. Apparatuses can include a display, a memory device, and a controller. In an example, the controller can assign a perceived interest and sort images based in part on the perceived interest. In another example, a method can include the assigning, by a controller coupled to a memory device, a perceived interest of an image of a plurality of images, wherein the perceived interest is assigned based in part on a period of time the image is visible on a display coupled to the memory device, selecting the image from an initial viewing location responsive to the assigned perceived interest; and transferring the image to a different viewing location, wherein the initial viewing location and the different viewing location are visible on the display.

Abstract: A processing device in a memory sub-system receives an indication that a write back operation was performed for a management unit in a memory device. Responsive to receiving the indication that the write back operation was performed, the processing device initiates a read verify operation for the management unit and receives an indication of a number of write back errors associated with the management unit during the read verify operation. The processing device further determines whether the number of write back errors satisfies a read verify threshold criterion, and responsive to the number of write back errors satisfying the read verify threshold criterion, remaps the management unit to a different location on the memory device.

Abstract: A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.

Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer read command comprising a physical address of data to be read from a memory device, wherein the physical address is indicated in at least a portion of a translation layer entry previously provided to the host system with a response to a host-resident translation layer write command and stored in a host-resident translation layer mapping table. The processing device further performs a read operation to read the data stored at the physical address from the memory device and sends, to the host system, the data from the physical address of the memory device.

Abstract: Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors.

Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.

Abstract: Systems and methods for re-purposing autonomous vehicle for package transportation are disclosed. In one embodiment, a method is disclosed comprising receiving a request from an autonomous vehicle; identifying, responsive to the request, a nearby package stored within a delivery structure; transmitting routing instructions to the autonomous vehicle, the routing instructions including a location of the delivery structure; detecting a presence of the autonomous vehicle; instructing the delivery structure to deposit the nearby package into the autonomous vehicle; calculating a waypoint for delivery of the nearby package; and transmitting transport routing instructions to the autonomous vehicle, the transport routing instructions including the waypoint.

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

Abstract: A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to select a block size for allocating blocks to namespaces based on a storage capacity of the non-volatile storage media. Various requests by a host to create namespaces are received by the controller via the host interface. After each request is received, the controller allocates blocks to the requested namespace using the selected block size. The controller can select the block size at the time of initial manufacture or operation, and/or can dynamically select various block sizes during operation of the storage device. Dynamic selection of the block size can be based on signaling from sensors of the storage device and/or host.

Abstract: Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.