Patents Assigned to Micron Technology, Inc.
  • Publication number: 20210143860
    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data delayed versions of at least a portion of the respective processing results with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data delayed versions of respective outputs of various layers of multiplication/accumulation processing units (MAC units) for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a wireless processing mode selection. In another example, such mixing input data with delayed versions of processing results may be to receive and process noisy wireless input data. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 13, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Fa-Long Luo
  • Publication number: 20210142852
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: John Schreck, Dan Penney
  • Publication number: 20210143167
    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack.
    Type: Application
    Filed: January 18, 2021
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Collin Howder, Chet E. Carter
  • Publication number: 20210143142
    Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner
  • Publication number: 20210143164
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Bharat Bhushan, David Daycock, Subramanian Krishnan, Leroy Ekarista Wibowo
  • Publication number: 20210143171
    Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Shyam Surthi
  • Publication number: 20210143840
    Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing the neural network decoders and/or recurrent neural networks. In this manner, neural networks or recurrent neural networks described herein may be used to implement error correction coding (ECC) decoders.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Fa-Long Luo
  • Publication number: 20210143165
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Publication number: 20210141605
    Abstract: An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Fabio Indelicato
  • Publication number: 20210143054
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Lingyu Kong, David Daycock, Venkata Satyanarayana Murthy Kurapati, Leroy Ekarista Wibowo
  • Patent number: 11002914
    Abstract: Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical waveguide integrated on a chip. An on-chip feedback mechanism can steer the beam between the fiber and a grating based waveguide to minimize the insertion loss of the system.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 11003240
    Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Parthasarathy Gajapathy
  • Patent number: 11003515
    Abstract: Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Paul Dlugosch
  • Patent number: 11003164
    Abstract: Methods of aligning a number of physical layers to a pattern formed via multi-patterning are disclosed. A method may include determining a misalignment vector between a first layer and a second layer used to form a pattern via multi-patterning. The method may also include calculating, based on the misalignment vector between the first layer and the second layer, a center position of the pattern. Further, the method may include aligning a third layer to center position of the pattern. A computing system and a processing system are also described.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kohei Hosokawa
  • Patent number: 11003448
    Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gregory Edvenson, David Hulton, Jeremy Chritz
  • Patent number: 11003363
    Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: J. Thomas Pawlowski
  • Patent number: 11003365
    Abstract: Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Claudio Resta, Marco Ferraro
  • Patent number: 11003384
    Abstract: Host data to be written at a memory sub-system is received. A write operation is performed to write the host data at the memory sub-system. Based on the performance of the write operation, one or more usage parameter values are determined. The one or more parameter values correspond to one or more operations performed at the memory sub-system. Based on the one or more usage parameter values, a first expected time period is determined during which a first set of subsequent host data will be received from the host system and a second expected time period is determined during which a second set of subsequent host data will be received from the host system. A media management operation is scheduled to be performed between the first expected time period and the second expected time period.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 11, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Poorna Kale
  • Patent number: 11004798
    Abstract: Embodiments of the disclosure are drawn to arrangements of one or more “cuts” or pattern of cuts in conductive structures. Wiring layers may each include a cut pattern including a set of cuts through conductive structures of the wiring layers where each of the cuts is offset from the other in a direction orthogonal to the cut. The cut pattern in a wiring layer may be orthogonal to the cut pattern in another wiring layer. In some examples, the cut pattern may be a stair-step pattern. In some examples, the cut pattern may be interrupted by other conductive structures.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hirokazu Matsumoto, Ryota Suzuki, Mitsuki Koda, Makoto Sato
  • Patent number: 11003386
    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather