Abstract: A 3D memory device includes sense amplifier drivers which are positioned adjacent to the sense amplifiers. The memory device may include memory patches with memory cells organized in a 3D array. The sense amplifiers and sense amplifier drivers are positioned above the memory patches. In some embodiments the sense amplifier drivers are positioned above the patch and next to a sense amplifier region. In some embodiments the sense amplifier drivers are within the sense amplifier region, for example between two rows of sense amplifiers. In some embodiments, portions of the sense amplifier drivers may overlap portions of the adjacent row(s) of sense amplifiers.

Abstract: Apparatuses, systems, and methods for a refresh scheme that refreshes word lines in a same tier in 3D-DRAM. The 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The 3D memory array may be refreshed on a word line-by-word line basis as part of a refresh operation. During the refresh operation, one or more word lines may be refreshed in the 3D memory device. The word lines being refreshed may all be at a same tier of the 3D memory device. The tier may represent the depth at which the refreshed word line exists within a stack of word lines in the 3D memory array.

Abstract: A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The GDLs are organized in pairs, with each pair coupled to a sense amplifier. In an example arrangement, one GDL of the pair may be in a first metal layer while the other GDL of the pair may be in a second metal layer. The folded GDL arrangement may allow more flexibility in the placement of the sense amplifiers. For example, rather than being placed between two array sections that they are associated with, the sense amplifiers may be at the edge of a single section that they are associated with.

Abstract: A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The GDLs are organized in pairs, with each pair coupled to a sense amplifier. In an example arrangement, an area between memory array patches may contain capacitors. For example, the capacitors may be for managing internal voltages of the memory device. In some embodiments, the memory cells directly adjacent to the capacitor region may be dummy memory cells to act as a buffer between active memory cells and the capacitors located in the capacitor region.

Abstract: A 3D memory device includes memory banks. During refresh operations, responsive to a refresh signal and refresh address directed to a given bank, one or more word lines in a first portion of the bank are refreshed at a first time and one or more word lines in a second portion of the bank are refreshed at a second time after the first time. For example, one or more row control circuits associated with the bank provide a first sense amplifier enable signal to the first portion and a second sense amplifier enable signal to the second portion. The second sense amplifier enable signal is provided through a delay circuit to stagger the two signals in time.

Abstract: The disclosure provides a 3D memory device with various staircase arrangements in a staircase region between two memory patches each including memory cells arranged in a 3D array. The staircase includes vertical conductive elements extending from groups of sub-word line drivers (SWDs) arranged above the staircase region to stacks of horizontal word lines (WLs) extending through the two patches and the in-between staircase region. The conductive elements couple SWDs selected from the SWD groups to the associated WLs in the WL stacks. The conductive elements have lengths to match depths of the WLs. The shortest and longest conductive elements are coupled to the top and bottom WLs, respectively. The WLs may be in a first die such as an array die and the SWDs may be in a second die such as a CMOS die bonded to the array die.

Abstract: A 3D memory device includes a memory patch with memory cells organized in a 3D array. The memory cells are coupled to local digit lines which are coupled in sets to global digit lines. The global digit lines are coupled to sense amplifiers. The sense amplifiers are in a sense amplifier region which is positioned above the memory patch. The sense amplifiers may be arranged in a grid of multiple columns and at least two rows. The global digit lines may be coupled to their respective sense amplifiers by vertical conductive elements. The sense amplifiers may have two contact pads coupling them to two global digit lines, and the contact pads may be arranged on a same side of the sense amplifier.

Abstract: A 3D memory device includes a memory patch with memory cells organized in a 3D array. The memory cells are coupled together by local digit lines, and sets of local digit lines are coupled to global digit lines through respective multiplexer circuits. Multiplexer drivers provide multiplexer control signals to sets of the multiplexer circuits. The multiplexer drivers may be positioned in a die above the array die. In some embodiments, multiplexer drivers provide their signals just to the multiplexers in the patch they are over. In some embodiments, the multiplexer drivers provide their signals to the multiplexers in multiple patches. For example, the multiplexer control signals may extend through a staircase region between memory patches.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for managing sPPR undo operations based on activation count values of original rows after a repair. After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During an sPPR operation, an address of an original row of memory may be associated with an open repair address instead, such as when the original row is determined to be damaged or defective. The sPPR repair may be reversed by performing an sPPR undo operation. While the repair row is associated with the original row, the activation count of the original row may become corrupted, and it may be necessary to reset the activation count associated with the original row during a repair undo operation to prevent unnecessary refresh operations occurring on the original row and adjacent rows.

Abstract: A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third direction. The GDLs are coupled to sense amplifiers. For example, a first set of sense amplifiers are coupled to even ones of a first half of the GDLs, a second set are coupled to even ones of a second half of the GDLs, a third set are coupled to odd ones of the first half of the GDLs, and a fourth set are coupled to odd ones of the second half of GDLs. The first and the fourth set of sense amplifiers may be positioned above the array, while the second and third sets are not.

Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

Abstract: A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.

Abstract: A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The GDLs are organized in pairs, with each pair coupled to a sense amplifier. In an example arrangement, an area between memory patches on a CMOS die may be a peripheral region that contains circuit components for the memory device. In some embodiment, the area directly below the peripheral region on the array die may be generally not be used. In some embodiments, capacitors may be placed in the peripheral region of the array die to manage voltages generated by components on the CMOS die. In some embodiments, other components may be placed in the peripheral region of the array die.

Abstract: A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third direction. The memory device includes a number of ‘quilts’ each of which includes four memory patches arranged in a 2x2 grid. The sense amplifiers are positioned along the border between patches in the third direction. Adjacent sense amplifiers are couple to adjacent GDLs in the two associated patches. In some embodiments, the sense amplifiers are positioned above the memory patches in the second direction. In some embodiments, multiplexer drivers are also positioned above the array. The quilts may be relatively compact and don’t have sense amplifiers along their edges, allowing for easier tiling at the edge of the device.

Abstract: Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells are in the memory-cell tiers and individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. A capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. Immediately-vertically-adjacent of the memory-cell tiers comprise an upper memory-cell tier and a lower memory-cell tier. The insulative tiers comprise an insulator that is vertically between the immediately-vertically-adjacent memory-cell tiers. The insulator comprises a void-space that is vertically between the gate of the upper memory-cell tier and the gate of the lower memory-cell tier. The void-space is directly against at least one of (a) and (b), where: (a) a bottom surface of the gate of the upper memory-cell tier; and (b) a top surface of the gate of the lower memory-cell tier.

Abstract: Apparatuses and methods for error correction based on data characteristics are disclosed. Data characteristics can include importance of the data. Data is received at a memory controller from a host device, and a characteristic of the received data is determined. A level of error correction is selected from a plurality of error correction levels for the received data based on the determined characteristic. The received data and an error correction code are written to a memory. The error correction code is generated based on the selected level of error correction. In some implementations, the characteristic of the received data is determined using a neural network.

Abstract: Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: A 3D memory device includes a plurality of global digit line pairs. Each global digit line pair may generally be stacked with one global digit line of the pair above the other. Along the length of a global digit line pair there may be one or more twist regions. Within a twist region, the global digit line pair exchanges which global digit line is on top and which is on bottom. Within the twist region, at least one of the global digit lines couples to a transfer element which is offset from the twisting global digit line. To accommodate this, the adjacent global digit line pair may be shunted to have one of the global digit lines run in a shunt layer different than the layer with the transfer element.

Abstract: A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third direction. A memory section includes two memory patches with a staircase region in between. The word lines run continuously through the two patches and through the in-between staircase region. Sub-word line drivers (SWDs) are positioned above the staircase region and coupled to respective ones of the word lines by conductive elements running in the second direction. In this way the SWDs may be located in a middle of the memory section.