Patents Assigned to Micron Technology, Inc.
  • Publication number: 20240087948
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Micron Technology, Inc.
    Inventor: David H. Wells
  • Publication number: 20240090197
    Abstract: An apparatus includes: a plurality of capacitors each including first and second conductive portions and a dielectric portion therebetween; a first conductive structure containing the plurality of capacitors therein, and electrically coupled to the second conductive portions of the plurality of capacitors; a second conductive structure on a top surface of the first conductive structure; and a third conductive structure on a top surface of the second conductive structure.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Harutaka Honda, SHOGO OMIYA, SHOKO NORIFUSA, HIDEKAZU NOBUTO
  • Publication number: 20240087643
    Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Justin Eno, Sean S. Eilert, Ameen D. Akel, Kenneth M. Curewitz
  • Publication number: 20240086100
    Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Justin Eno, Sean S. Eilert, Ameen D. Akel, Kenneth M. Curewitz
  • Patent number: 11928442
    Abstract: A method related to posit tensor processing can include receiving, by a plurality of multiply-accumulator (MAC) units coupled to one another, a plurality of universal number (unum) or posit bit strings organized in a matrix and to be used as operands in a plurality of respective recursive operations performed using the plurality of MAC units and performing, using the MAC units, the plurality of respective recursive operations. Iterations of the respective recursive operations are performed using at least one bit string that is a same bit string as was used in a preceding iteration of the respective recursive operations. The method can further include prior to receiving the plurality of unum or posit bit strings, performing an operation to organize the plurality of unum or posit bit strings to achieve a threshold bandwidth ratio, a threshold latency, or both during performance of the plurality of respective recursive operations.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Vijay S. Ramesh
  • Patent number: 11928063
    Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
  • Patent number: 11928330
    Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Doyle W. Rivers
  • Patent number: 11928055
    Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
  • Patent number: 11928018
    Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11928023
    Abstract: Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Schaefer
  • Patent number: 11928021
    Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes an address fault detection system designed to detect a mismatch between the address originally used to store the data and the address subsequently used to read the data. The address fault detection system generates an address parity bit from the received address and either stores that address parity bit with the user data or uses the address parity bit to invert the internal ECC bits generated from the user data. The address fault detection system can determine from the resulting syndrome from the ECC bits whether or not an address fault has occurred and raise an address fault indication flag if the address fault is detected.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Melissa I. Uribe
  • Patent number: 11928025
    Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tony M. Brewer, Brent Keeth
  • Patent number: 11928246
    Abstract: Content within a memory device (e.g., a DRAM) may be secured in a customizable manner. Data can be secured and the memory device performance by be dynamically defined. In some examples, setting a data security level for a group of memory cells of a memory device may be based, at least in part, on a security mode bit pattern (e.g., a flag, flags, or indicator) in metadata read from or written to the memory device. Some examples include comparing a first signature (e.g., a digital signature) in metadata to a second value (e.g., an expected digital signature) to validate the first value in the metadata. The first value and the second value can be based, at least in part, on the data security level. Some examples include performing a data transfer operation in response to validation of the first and/or second values.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11928039
    Abstract: Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technologies, Inc.
    Inventors: Yang Lu, Kang-Yong Kim, Mark Kalei Hadrick, Keun Soo Song
  • Patent number: 11928333
    Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11928332
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11928590
    Abstract: A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows includes a plurality of programmable elements. Furthermore, each of the programmable elements are configured to analyze at least a portion of a data stream and to selectively output a result of the analysis. Each of the plurality of blocks also has corresponding block activation logic configured to dynamically power-up the block.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Patent number: 11928353
    Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Patent number: 11928343
    Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Liang Yu, Jonathan Scott Parry, Luigi Pilolli
  • Patent number: 11928347
    Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Mustafa N Kaynak, Peter Feeley, Sampath K Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Karl D Schuh, Jiangang Wu