HIGH RESISTANCE CMOS RESISTOR
A high resistance CMOS resistor with a relatively small die size is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor. The CMOS resistor according to the present invention has a resistance of, for example, 10 kΩ-20 kΩ per square.
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This application is a continuation application of a prior application Ser. No. 10/823,238, filed Apr. 12, 2004. All disclosure of the U.S. application is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor structure, and more specifically to a high resistance CMOS resistor.
2. Description of Related Art
Many common circuits manufactured using CMOS process require resistor elements. In the area of analog circuits, resistor elements having high-resistance values (100 kΩ-500 kΩ) are sometimes desired. The demand for such resistors is especially common in the field of power-relative analog circuits.
In one common application, many power-relative analog circuits include voltage dividers constructed from a pair of CMOS resistors. Such voltage dividers provide reference voltages that are stepped down from a supply voltage. The higher the resistance of the resistors is, the less standby power will be consumed.
Currently, most widely used CMOS resistors are either junction resistors or film resistors. Common junction resistor types include NW resistors, PW resistors, NDIFF(N+S/D) resistors, and PDIFF(N+S/D) resistors. Common film resistor types include Poly resistors, M1 resistors, and M2 resistors.
Though these resistors have satisfactory resistor characteristics, their resistance is generally limited to 1 kΩ-5 kΩ per square. When a high-resistance element is required, it can be created either by using extra die space, or by performing additional masking steps during the manufacturing process. However, neither of these alternatives is desirable because they both increase the cost of manufacturing the circuit.
Creating a high-resistance resistor (for example, from 100 kΩ to 500 kΩ) with traditional CMOS resistors is often commercially impractical due to die-size and cost restrictions. Therefore, there exists a need for a CMOS resistor having a significantly higher resistance per square than existing CMOS resistors. Furthermore, the process for manufacturing such a CMOS resistor should not require any additional masking steps.
SUMMARY OF THE INVENTIONThe present invention provides a CMOS resistor with a relatively small die-size. Such a CMOS component can reduce the cost and the die-size of existing circuits to fabricate many novel CMOS circuit designs.
While current CMOS resistors generally do not exceed 1 kΩ-5 kΩ per square, the present invention presents a high resistance CMOS resistor having a high resistance, for example, from 10 k to 20 kΩ per square. Furthermore, unlike many existing processes of fabricating CMOS resistors, the process according to the present invention does not require any additional masking steps.
According to an embodiment of the present invention, a CMOS resistor is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor.
According to an embodiment of the present invention, a semiconductor structure of a CMOS resistor is provided. The semiconductor structure of the CMOS resistor includes a p-type silicon substrate; an n-well disposed in the p-type silicon substrate; a p-well disposed in a non-active area of the p-type silicon substrate; a first p-field region disposed in the p-well; a second p-field region disposed in the n-well; a field oxide layer disposed on the first p-field region and the second p-field region; an n-type contact region disposed in the n-well; and a two p-type contact regions respectively disposed beside the field oxide layer in the n-well as a first ohmic contact and a second ohmic contact.
The CMOS resistor according to the present invention substantially reduces the standby power consumption of voltage dividers that are widely used for generating reference voltages. A CMOS resistor having a resistance of 10 kΩ-20 kΩ per square could also substantially reduce the manufacturing and operating costs of many other existing circuits. A higher resistance per square could also make many new analog circuit designs involving high-resistance resistors possible.
However, the scope of this invention is no way limited to the field of low standby-power electronics, or to voltage dividers. There are many other types of circuits that could potentially benefit from the use of such high-resistance CMOS resistors. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
According to an embodiment of the present invention, a high resistance CMOS resistor is provided. The process of fabricating the high resistance CMOS resistor comprises for example, the following steps. An n-well and a p-well are formed in a p-type silicon substrate. A nitride layer is then deposited over the p-type silicon substrate. Next, photolithography and etching steps are used to pattern the nitride layer to form a patterned mask layer for defining a non-active area and active area over the p-type silicon substrate. In general, some p-type ions are implanted into the non-active area of the p-well. Some channel-stops are also implanted for increasing the isolation capability.
To form a CMOS resistor in another embodiment, the CMOS process includes injecting the same p-type ions into the n-well to form a p-field region. After that, a field oxide is formed on the CMOS resistor. Heavily doped p-type contact regions are formed as the ohmic contacts of the CMOS resistor, after the photolithography, etching, and implanting steps. Finally, two contact openings and two metal contact plugs are formed to electrically connect two ohmic contacts of the CMOS resistor. Thus, a high resistance resistor is formed without requiring any additional masking steps. In addition, this process is fully compatible with standard CMOS processes.
Referring now to the drawings wherein the contents are for purposes of illustrating the preferred embodiment of the invention only and not for purposes of limiting the same. Referring to
Next, as
As shown in
Hereinafter, as
As shown in
Now turning to
As shown in
Next, contact openings and metal contact plugs are formed to electrically contact the two ohmic contacts of the CMOS resistor. As shown in
Thus, a CMOS resistor having high resistance is formed without any additional masking steps. In addition, this process is fully compatible with standard CMOS processes. This CMOS resistor will have a resistance of about 10 kΩ-20 kΩ per square.
It is to be understood that this process of fabricating a CMOS resistor according to the present invention is described for the purpose of illustrating rather than limiting the scope of the present invention.
Thus, it will be apparent to those skilled in the art, that the method for manufacturing a CMOS resistor according to the present invention could also be applied to manufacture an n-field resistor in an n-type silicon substrate, without departing from the spirit or the scope of the invention.
In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims or their equivalents.
Claims
1. A semiconductor structure of a CMOS resistor, comprising:
- a p-type silicon substrate;
- an n-well disposed in the p-type silicon substrate;
- a p-well disposed in a non-active area of the p-type silicon substrate;
- a first p-field region disposed in the p-well;
- a second p-field region disposed in the n-well;
- a field oxide layer disposed on the first p-field region and the second p-field region;
- an n-type contact region disposed in the n-well; and
- a pair of two p-type contact regions respectively disposed beside the field oxide layer in the n-well as a first ohmic contact and a second ohmic contact.
2. The semiconductor structure according to claim 1, further comprising a patterned BPSG layer formed to build two contact openings exposing a portion of the n-type contact region and the two p-type contact regions.
3. The semiconductor structure according to claim 2, further comprising two metal contact plugs disposed in the contact openings to electrically connect to the first ohmic contact and the second ohmic contact of the CMOS resistor.
4. The semiconductor structure according to claim 3, further comprising a passivation layer deposited over the contact plugs covering the CMOS resistor.
5. The semiconductor structure according to claim 1, wherein the CMOS resistor is formed compatibly with a standard CMOS process.
6. A semiconductor structure of a CMOS resistor, comprising:
- an n-well;
- a first p-type contact region disposed in the n-well;
- a second p-field region coupled to the first p-type contact region;
- a second p-type contact region coupled to the second p-field region; and
- a field oxide layer formed on the second p-field region.
7. The semiconductor structure according to claim 6, further comprising an n-type contact region coupled to the first p-type contact region.
8. The semiconductor structure according to claim 6, further comprising a p-well coupled to the n-well.
9. The semiconductor structure according to claim 8, further comprising a first p-field region formed on the p-well.
10. The semiconductor structure according to claim 9, further comprising a field oxide layer formed on the second p-field region.
11. A CMOS resistor, comprising:
- a p-field region disposed in a n-well of a substrate; and
- a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well, wherein the pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor.
Type: Application
Filed: Dec 6, 2006
Publication Date: May 3, 2007
Applicant: SYSTEM GENERAL CORP. (TAIPEI HSIEN)
Inventors: CHIH-FENG HUANG (HSINCHU COUNTY), TUO-HSIN CHIEN (TAIPEI)
Application Number: 11/567,349
International Classification: H01L 29/00 (20060101);