BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD
A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.
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1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to a structure, and method of forming same, including a bipolar transistor and a back-gated transistor in which the emitter region and back-gate conductor are in the same layer of material.
2. Background Art
The semiconductor fabrication industry is continually investigating ways to further miniaturize integrated circuits. One current area of investigation is use of back-gated complementary metal-oxide semiconductor (CMOS) transistors (BGCMOS) to provide further scaling of conventional CMOS technology. One challenge in this area, however, is integration of high-performance bipolar transistors to form bipolar CMOS devices (BiCMOS) with BGCMOS devices. That is, conventional integration schemes do not adequately integrate the two technologies.
In view of the foregoing, there is a need in the art for a solution for generating bipolar transistors and back-gated transistors together.
SUMMARY OF THE INVENTIONA structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.
A first aspect of the invention provides a structure comprising: a substrate including an insulator layer on a bulk layer; and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer.
A second aspect of the invention provides a structure comprising: an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region; and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material.
A third aspect of the invention provides a method of forming a structure, the method comprising the steps of: forming a bipolar transistor on a substrate including an insulator layer on a bulk layer, the bipolar transistor including an emitter region; and forming a back-gated transistor on the substrate, wherein a back-gate conductor of the back-gated transistor and the emitter region are in the same layer of material.
The illustrative aspects of the present invention are designed to solve the problems herein described and other problems not discussed, which are discoverable by a skilled artisan.
BRIEF DESCRIPTION OF THE DRAWINGSThese and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
DETAILED DESCRIPTION Turning to the drawings,
Turning to
Turning to the illustrative embodiment of the method of forming structure 100 (
As shown in
Next, as shown in
As shown in
Returning to
It should be recognized that the above-described method is only illustrative and that other steps may also be used to generate structure 100.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.
Claims
1. A structure comprising:
- a substrate including an insulator layer on a bulk layer; and
- a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer.
2. The structure of claim 1, wherein substantially all of the emitter region is in the insulator layer.
3. The structure of claim 1, further comprising a back-gate transistor in a second region of the substrate, the back-gate transistor comprising a back-gate conductor formed in the insulator layer.
4. The structure of claim 3, wherein the emitter region and the back-gate conductor are in respective portions of the same layer of material.
5. The structure of claim 4, wherein the emitter region and the back-gate conductor include one of: single crystal silicon and polysilicon.
6. The structure of claim 1, wherein a collector region extends over an extrinsic base region and is partially isolated therefrom by a portion of a dielectric.
7. The method of claim 1, wherein the insulator layer is one of: a dielectric material, a hydrogen (H2) implanted silicon and a helium (He) implanted silicon.
8. A structure comprising:
- an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region; and
- a back-gated transistor in a second region of the substrate,
- wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material.
9. The structure of claim 8, wherein the layer of material is included in the insulator layer.
10. The structure of claim 9, wherein substantially all of the emitter region is in the insulator layer.
11. The structure of claim 8, wherein the emitter region and the back-gate conductor include one of: single crystal silicon and polysilicon.
12. The structure of claim 8, wherein a collector region of the bipolar transistor extends over an extrinsic base region and is partially isolated therefrom by a portion of a dielectric.
13. A method of forming a structure, the method comprising the steps of:
- forming a bipolar transistor on a substrate including an insulator layer on a bulk layer, the bipolar transistor including an emitter region; and
- forming a back-gated transistor on the substrate,
- wherein a back-gate conductor of the back-gated transistor and the emitter region are in the same layer of material.
14. The method of claim 13, wherein the forming steps occur at least partially simultaneously.
15. The method of claim 13, wherein the emitter region and the back-gate conductor include one of: single crystal silicon and polysilicon.
16. The method of claim 13, wherein the layer of material includes the insulator layer.
17. The method of claim 13, wherein the bipolar transistor forming step includes forming at least a portion of an emitter region in the insulator layer.
18. The method of claim 17, wherein the emitter region forming step includes forming substantially all of the emitter region in the insulator layer.
19. The method of claim 13, wherein the bipolar transistor forming step includes forming a collector region that extends over an extrinsic base region and is partially isolated therefrom by a portion of a dielectric.
20. The method of claim 13, wherein the forming steps includes the step of inverting a partially formed structure.
Type: Application
Filed: Nov 9, 2005
Publication Date: May 10, 2007
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Andres Bryant (Burlington, VT), William Clark (Essex Junction, VT), Edward Nowak (Essex Junction, VT)
Application Number: 11/164,071
International Classification: H01L 27/082 (20060101);