MOS Transistors Including Silicide Layers on Source/Drain Regions
A MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region. An I-shaped spacer is on sidewalls of the gate electrode. A lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate electrode. A first silicide layer is on a surface of the heavily doped region and a second silicide layer is on the lightly doped region between the I-shaped spacer and the first silicide layer.
This application is a divisional of application Ser. No. 10/388,354 entitled Methods of Forming Silicide Layers on Source/Drain Regions of MOS Transistors, filed Mar. 13, 2003 and claims the benefit of Korean Patent Application No. 2002-17088, filed on Mar. 28, 2002, the disclosures of both are herein incorporated by reference in their entirety.
FIELD OF THE INVENTIONThe present invention relates to Metal-Oxide-Semiconductor (MOS) transistors and, more specifically, to MOS transistors having silicided source/drain regions.
BACKGROUNDSelf-aligned silicide (Salicide) processes have been widely used to lower resistances of gate and source/drain regions of transistors. Generally, a Salicide process is a method of simultaneously forming a silicide layer on a polysilicon gate electrode and on an active region of a silicon substrate. A Salicide process can lower the contact resistance and the sheet resistance.
The lightly doped region 10 can be self-aligned to the gate stack between a channel region that underlies the gate stack and the heavily doped region 14. The lightly doped region 10 allows an electric field between the source/drain region and the channel region to be decreased which may prevent or reduce the rapid acceleration of carriers emitted from the source (i.e., hot carrier effects).
SUMMARYEmbodiments according to the present invention can provide MOS transistors including silicide layers. Pursuant to these embodiments a MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region. An I-shaped spacer is on sidewalls of the gate electrode. A lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate electrode. A first silicide layer is on a surface of the heavily doped region and a second silicide layer is on the lightly doped region between the I-shaped spacer and the first silicide layer.
In some embodiments according to the invention, a MOS transistor includes a first silicide layer having a first thickness on a source/drain region self-aligned to a sidewall spacer of a gate electrode and a second silicide layer having a second thickness, less than the first thickness, on the source/drain region adjacent to the first silicide layer.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.
Furthermore, relative terms, such as “beneath”, may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as “below” other elements would then be oriented “above” the other elements. The exemplary term “below”, can therefore, encompasses both an orientation of above and below.
It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention. Like numbers refer to like elements throughout.
The foregoing structure can allow formation of the silicide layer on the surface of the lightly doped region 28. Thus, the resistance of contacts thereon may be reduced to improve the speed of the device. The I-shaped spacer 35 can prevent an electric short between the gate electrode 26 and the impurity regions 28 and 40. In contrast to embodiments according to the present invention, a gate spacer used to form an LDD region in a conventional structure may prevent the formation of silicide on the LDD region which could prevent further reductions in the resistance. While the length of the gate electrode may be shortened as the associated design rule for the device is reduced, using conventional approaches it may be difficult to correspondingly increase the area of the silicide layer by reducing the width of the gate spacer 12 as to do so may promote lateral diffusion of impurities in the source/drain region.
Methods of fabricating embodiments according to the present invention will be described with reference to the drawings.
Referring to
An insulation layer and a conductive layer for a gate electrode are formed on the substrate 20 and then patterned to form a gate insulation layer 24 and a gate electrode 26. The conductive layer for the gate electrode can be formed of silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), in addition to impurity-doped polysilicon. Impurity ions are implanted into the active region at a low concentration using the gate electrode 26 and the field region 22 as an ion implantation mask, to form a lightly doped region 28. In some embodiments according to the present invention, a thin insulation layer is formed on the substrate 20 and the gate electrode 26. The insulation layer is etched to form an insulating spacer 30. The insulating spacer 30 can be a silicon oxide layer. In some embodiments according to the present invention, the lightly doped region 28 can be formed after the insulating spacer 30 is formed, using for example, diffusion.
Referring to
Referring to
The heavily doped region 40 is formed by ion implantation using the gate electrode 26, the insulating spacer 30, the gate spacer 39, and the field region 22 as an ion implantation mask. The inner insulation layer 32 remaining on the substrate can provide a buffer layer during the high-concentration ion implantation process.
Referring to
In embodiments according to the present invention where the first outer insulation layer 34 is a silicon nitride layer and the patterned second outer insulation layer 36 is a silicon oxide layer, the patterned second outer insulation layer 36 is removed using a buffered oxide etchant (BOE), whereas the patterned first outer insulation layer 34 is removed with a wet etching using a phosphoric acid (such as H3PO4). As mentioned above, the first outer insulation layer 34 can be thinner than the inner insulation layer 32 which may promote formation of the L-shaped spacer 33 to have the desired shape.
In some embodiments according to the present invention, a thin layer of about 50 Ångstroms of the inner insulation layer 32 may remain on the substrate after the wet etching to act as a buffer layer to protect the substrate. The remaining layer of the inner insulation layer 32 may also prevent wet etching of the projected portion at the base of the L-shaped spacer 33.
Referring to
A wet cleaning process is carried out to remove a natural oxide layer on a surface of the heavily doped region 40 and on a surface of the gate electrode 26. A cobalt layer is deposited using, for example, sputtering. A cobalt monosilicide (CoSi) is formed by a first thermal process. The first thermal process is carried out at a temperature in a range between about 400° C. and about 600° C. in a conventional rapid thermal annealer. This can cause a silicide reaction in regions where the cobalt contacts silicon. The regions of the substrate having the silicide reaction are cleaned using a mixed solution of sulfuric acid (H2SO4), oxygenated water (H2O2), and water (H2O). Thus, the unsilicided cobalt layer can be removed. A second thermal process is carried out at a temperature of about 750° C. or higher. The second thermal process can promote the cobalt monosilicide (CoSi) to change phase to cobalt disilicide (CoSi2) which can have a low resistivity.
In some embodiments according to the present invention, the silicide layer may be formed using a one-step thermal process. For example, a cobalt layer can be formed and then annealed at about 750° C. or higher. Thereafter, a cleaning process is carried out to remove the unreacted metal, thereby forming the silicide layer.
Referring to
Referring to
Referring to
The I-shaped spacer 35 remaining on the sidewalls of the gate electrode 26 prevents an electric short between the gate electrode 26 and the impurity regions 28 and 40 due to the second silicide layer 46.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
As set forth before, according to some embodiments of the present invention, when a MOS transistor with an LDD structure is fabricated, a silicide layer can be formed even at a lightly doped region. As a result, a resistance of a source/drain region may be reduced.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims
1. A MOS transistor comprising:
- a substrate;
- a field region on the semiconductor substrate to define an active region;
- an I-shaped spacer on sidewalls of the gate electrode;
- a lightly doped region and a heavily doped region n the semiconductor substrate on sides of the gate electrode;
- a first silicide layer on a surface of the heavily doped region; and
- a second silicide layer on the lightly doped region between the I-shaped spacer and the first silicide layer.
2. The MOS transistor as claimed in claim 1, wherein the second silicide layer is thinner than the first silicide layer.
3. The MOS transistor as claimed in claim 1, further comprising a gate silicide layer on the gate electrode.
4. A MOS transistor comprising:
- a first silicide layer having a first thickness on a source/drain region self-aligned to a sidewall spacer of a gate electrode; and
- a second silicide layer having a second thickness, less than the first thickness, on the source/drain region adjacent to the first silicide layer.
5. The MOS transistor according to claim 4 further comprising:
- lightly and heavily doped source/drain regions adjacent to one another in a substrate having the gate electrode with the sidewall spacer thereon;
6. The MOS transistor according to claim 4 wherein a surface of the first silicide layer extends beyond an adjacent surface of the second silicide layer.
7. The MOS transistor according to claim 4 wherein the first silicide layer extends deeper into the source/drain region that the second silicide layer.
8. The MOS transistor according to claim 4 wherein the first silicide layer is elevated farther above the source/drain region that the second silicide layer.
Type: Application
Filed: Mar 29, 2007
Publication Date: Jul 26, 2007
Inventors: Young-Ki Lee (Gyeonggi-do), Heon-Jong Shin (Gyeonggi-do), Hwa-Sook Shin (Gyeonggi-do)
Application Number: 11/693,317
International Classification: H01L 29/76 (20060101); H01L 29/94 (20060101);